An epitaxial wafer, an epitaxial wafer preparation method, and a light-emitting diode

Abstract

The present invention discloses an epitaxial wafer, a method for preparing an epitaxial wafer, and a light-emitting diode. The epitaxial wafer includes a three-dimensional island layer, and the three-dimensional island layer includes a first superlattice layer and a second superlattice layer which are sequentially stacked; the first superlattice layer includes a first superlattice first sub-layer, a second sub-layer, a third sub-layer, a fourth sub-layer, and a fifth sub-layer which are sequentially stacked alternately at a preset period; the second superlattice layer includes a second superlattice first sub-layer and a second superlattice second sub-layer which are sequentially stacked alternately on the last first superlattice fifth sub-layer at a preset period; wherein, the first superlattice first sub-layer, the first superlattice third sub-layer, the first superlattice fifth sub-layer, and the second superlattice second sub-layer are all GaN layers, the first superlattice second sub-layer is an AlN layer, the first superlattice fourth sub-layer is an InN layer, and the second superlattice first sub-layer is an MgN layer. The present invention solves the problem of poor crystal quality of the epitaxial wafer in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an epitaxial wafer, a method for preparing an epitaxial wafer, and a light-emitting diode. Background Art

[0002] Due to its advantages of low heat generation efficiency, radiation resistance, high breakdown voltage, large electron saturation drift velocity, and small dielectric constant, GaN materials have been widely used in high-frequency, high-temperature, high-voltage electronic device fields, light-emitting diodes (LEDs), semiconductor lasers (LDs), etc., and have become a current research hotspot.

[0003] During the LED epitaxial growth process, due to the lack of a substrate material that matches GaN, hetero-substrates are usually used for epitaxial growth at present, including sapphire, SiC, Si, etc. Since there is a lattice mismatch between the GaN epitaxial layer and the substrate during hetero-epitaxial growth, a large number of dislocations and defects exist at the interface of the GaN thin film obtained by hetero-epitaxial growth, seriously affecting the crystal quality and performance of the material. For example, the lattice mismatch between the sapphire substrate and GaN is 14%, and the lattice mismatch between the Si substrate and GaN is 17%, and the thermal mismatch is 56%. Currently, the growth of GaN-based LED epitaxial layers generally first prepares an AlN (or AlGaN) buffer layer by MOCVD method or PVD method or a combination of both methods to reduce the dislocations generated by the lattice mismatch between the substrate and the epitaxial layer, and then continues to epitaxially grow a three-dimensional island-shaped GaN layer, a two-dimensional undoped GaN layer, an n-type doped GaN layer, an active layer, and a p-type doped GaN layer in MOCVD. Therefore, the growth quality of the three-dimensional island-shaped GaN layer is crucial for the crystal quality of the subsequent GaN epitaxial layer.

[0004] In the prior art, the commonly used method is to make GaN exhibit a three-dimensional growth mode by increasing the growth pressure and reducing the V / III ratio. Although the conventional adjustment of the growth pressure and V / III ratio can improve the crystal quality of the GaN epitaxial layer to a certain extent, the crystal quality of the epitaxial wafer is still poor. Summary of the Invention

[0005] Based on this, the object of the present invention is to provide an epitaxial wafer, a method for preparing an epitaxial wafer, and a light-emitting diode, aiming to solve the problem of poor crystal quality of the epitaxial wafer in the prior art.

[0006] The embodiments of the present invention are implemented as follows:

[0007] On the one hand, an epitaxial wafer is provided, including a three-dimensional island-shaped layer, and the three-dimensional island-shaped layer includes a first superlattice layer and a second superlattice layer that are sequentially stacked.

[0008] The first superlattice layer includes a first superlattice first sub-layer, a first superlattice second sub-layer, a first superlattice third sub-layer, a first superlattice fourth sub-layer, and a first superlattice fifth sub-layer that are alternately stacked in a preset period.

[0009] The second superlattice layer includes a second superlattice first sub-layer and a second superlattice second sub-layer that are alternately stacked in a preset period on the last first superlattice fifth sub-layer.

[0010] Among them, the first superlattice first sub-layer, the first superlattice third sub-layer, the first superlattice fifth sub-layer, and the second superlattice second sub-layer are all GaN layers, the first superlattice second sub-layer is an AlN layer, the first superlattice fourth sub-layer is an InN layer, and the second superlattice first sub-layer is an MgN layer.

[0011] In addition, the epitaxial wafer proposed according to the embodiment of the present invention may further have the following additional technical features:

[0012] Further, in the first superlattice layer, the growth thicknesses of the first superlattice second sub-layer and the first superlattice fourth sub-layer in a single period are both 1-5 nm.

[0013] Further, in the first superlattice layer, the growth thicknesses of the first superlattice first sub-layer, the first superlattice third sub-layer, and the first superlattice fifth sub-layer in a single period are all 10-15 nm.

[0014] Further, in the second superlattice layer, the growth thickness of the second superlattice second sub-layer in a single period is 10-20 nm.

[0015] Further, in the second superlattice layer, the growth thickness of the second superlattice first sub-layer in a single period is 1-5 nm.

[0016] Further, the preset period of the first superlattice layer is 10-15 times, and the preset period of the second superlattice layer is 10-20 times.

[0017] Further, the epitaxial wafer further includes a substrate, a buffer layer, a two-dimensional undoped GaN layer, an N-type doped GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type doped GaN layer, and a contact layer;

[0018] The buffer layer, the three-dimensional island layer, the two-dimensional undoped GaN layer, the N-type doped GaN layer, the multi-quantum well layer, the electron blocking layer, the P-type doped GaN layer, and the contact layer are sequentially stacked on the substrate.

[0019] On the other hand, an epitaxial wafer preparation method is provided for preparing the above epitaxial wafer, and the epitaxial wafer preparation method includes:

[0020] Provide a substrate;

[0021] Grow a buffer layer on the substrate;

[0022] Grow a first superlattice first sublayer, a first superlattice second sublayer, a first superlattice third sublayer, a first superlattice fourth sublayer, and a first superlattice fifth sublayer on the buffer layer in a preset period in sequence to form a first superlattice layer. Then, grow a second superlattice first sublayer and a second superlattice second sublayer on the last first superlattice fifth sublayer in a preset period in sequence to form a second superlattice layer for growing a three-dimensional island layer. Wherein, the first superlattice first sublayer, the first superlattice third sublayer, the first superlattice fifth sublayer, and the second superlattice second sublayer are all GaN layers, the first superlattice second sublayer is an AlN layer, the first superlattice fourth sublayer is an InN layer, and the second superlattice first sublayer is an MgN layer;

[0023] Grow a two-dimensional undoped GaN layer, an N-type doped GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type doped GaN layer, and a contact layer on the three-dimensional island layer in sequence.

[0024] Further, in the above epitaxial wafer preparation method, the growth temperature of the first superlattice layer and the second superlattice layer is 800 - 1000 °C, and the growth pressure is 50 - 200 torr.

[0025] In another aspect, a light-emitting diode is provided, including the above epitaxial wafer.

[0026] Compared with the prior art: In the embodiment of the present invention, by respectively setting the three-dimensional island layer into a first superlattice layer and a second superlattice layer, and inserting an AlN layer and an InN layer into the first superlattice layer GaN / AlN / GaN / InN / GaN, the lattice mismatch between AlN and GaN and the lattice mismatch between InN and GaN can be utilized to promote the growth of three-dimensional GaN islands, reduce the density of three-dimensional GaN islands, which is beneficial to reducing the dislocations generated by two-dimensional healing, thereby improving the crystal quality of the GaN epitaxial layer. And the tensile stress introduced by the growth of AlN on the GaN layer can be alleviated or offset by the compressive stress generated by the growth of InN on the GaN layer, reducing the stress in the epitaxial layer and lowering the epitaxial warpage; then inserting an MgN layer into the second superlattice layer MgN / GaN can inhibit the lateral growth of GaN islands and delay the healing of three-dimensional GaN islands, thereby enhancing the healing of three-dimensional GaN islands and the inhibition effect on dislocations again, so as to achieve the ultimate purpose of improving the crystal quality of the GaN epitaxial layer. Description of the Drawings

[0027] Figure 1Schematic structural diagram of an epitaxial wafer proposed in an embodiment of the present invention;

[0028] Figure 2 Schematic structural diagram of the first superlattice layer of the epitaxial wafer proposed in an embodiment of the present invention;

[0029] Figure 3 Schematic structural diagram of the second superlattice layer of the epitaxial wafer proposed in an embodiment of the present invention.

[0030] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. Specific Embodiments

[0031] For ease of understanding the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention is thorough and complete.

[0032] It should be noted that when an element is referred to as being "fixed on" another element, it can be directly on the other element or there can also be a middle element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be a middle element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used herein in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0034] In view of the problem of poor crystal quality of current epitaxial wafers, an embodiment of the present invention proposes an epitaxial wafer, an epitaxial wafer preparation method and a light-emitting diode, wherein:

[0035] Please refer to Figures 1 to 3 , the epitaxial wafer includes:

[0036] Substrate 1, a buffer layer 2, a three-dimensional island layer 3, a two-dimensional undoped GaN layer 4, an N-type doped GaN layer 5, a multi-quantum well layer 6, an electron blocking layer 7, a P-type doped GaN layer 8, and a contact layer 9 stacked on the substrate in sequence.

[0037] By way of example and not limitation, in this embodiment, the substrate 1 is a sapphire substrate, the buffer layer 2 is an AlGaN layer, the multi-quantum well layer 6 is composed of 5 to 12 periods of InGaN / GaN layers, where the InGaN layer is the well layer and the GaN layer is the barrier layer, the electron blocking layer 7 is an AlGaN layer, and the contact layer 9 is a GaN layer.

[0038] Furthermore, the three-dimensional island layer 3 includes a first superlattice layer 31 and a second superlattice layer 32 that are sequentially stacked; wherein, the first superlattice layer 31 includes a first superlattice first sub-layer 310, a first superlattice second sub-layer 311, a first superlattice third sub-layer 312, a first superlattice fourth sub-layer 313, and a first superlattice fifth sub-layer 314 that are sequentially stacked in a preset period, and the second superlattice layer 32 includes a second superlattice first sub-layer 320 and a second superlattice second sub-layer 321 that are sequentially stacked in a preset period on the last first superlattice fifth sub-layer 314.

[0039] Specifically, the first superlattice first sub-layer 310, the first superlattice third sub-layer 312, the first superlattice fifth sub-layer 314, and the second superlattice second sub-layer 321 are all GaN layers, the first superlattice second sub-layer 311 is an AlN layer, the first superlattice fourth sub-layer 313 is an InN layer, and the second superlattice first sub-layer 321 is an MgN layer.

[0040] It can be understood that by separately setting the three-dimensional island layer 3 into the first superlattice layer 31 and the second superlattice layer 32, and inserting the AlN layer and the InN layer into the first superlattice layer 31 GaN / AlN / GaN / InN / GaN, it is possible to promote the growth of three-dimensional GaN islands and reduce the density of three-dimensional GaN islands by virtue of the lattice mismatch between AlN and GaN and the lattice mismatch between InN and GaN, which is beneficial to reducing the dislocations generated by two-dimensional healing, thereby improving the crystal quality of the GaN epitaxial layer. Moreover, the tensile stress introduced by the growth of AlN on the GaN layer can be relieved or offset by the compressive stress generated by the growth of InN on the GaN layer, reducing the stress in the epitaxial layer and lowering the epitaxial warpage; subsequently, inserting the MgN layer into the second superlattice layer 32 MgN / GaN can inhibit the lateral growth of GaN islands and delay the healing of three-dimensional GaN islands, thereby enhancing the healing of three-dimensional GaN islands and the inhibition of dislocations again, so as to achieve the ultimate goal of improving the crystal quality of the GaN epitaxial crystal.

[0041] More specifically, within a single period of the first superlattice layer 31, the growth thickness of the second sub-layer 311 of the first superlattice is 1 - 5 nm, the growth thickness of the fourth sub-layer 313 of the first superlattice is 1 - 5 nm, the growth thickness of the first sub-layer 311 of the first superlattice is 10 - 15 nm, the growth thickness of the third sub-layer 312 of the first superlattice is 10 - 15 nm, and the growth thickness of the fifth sub-layer 314 of the first superlattice is 10 - 15 nm. Within a single period of the second superlattice layer 32, the growth thickness of the second sub-layer 321 of the second superlattice is 10 - 20 nm, and the growth thickness of the first sub-layer 320 of the second superlattice is 1 - 5 nm. The preset period of the first superlattice layer 31 is 10 - 15 times, and the preset period of the second superlattice layer 32 is 10 - 20 times.

[0042] On the other hand, the epitaxial wafer preparation method proposed in the embodiments of the present invention is used to prepare the above-mentioned epitaxial wafer, and the epitaxial wafer preparation method includes:

[0043] Providing a substrate;

[0044] Growing a buffer layer on the substrate;

[0045] Growing the first sub-layer, the second sub-layer, the third sub-layer, the fourth sub-layer, and the fifth sub-layer of the first superlattice on the buffer layer in sequence and alternately with a preset period to form the first superlattice layer, and then growing the first sub-layer and the second sub-layer of the second superlattice on the fifth sub-layer of the first superlattice in sequence and alternately with a preset period to grow a three-dimensional island layer. Among them, the first sub-layer, the third sub-layer, the fifth sub-layer of the first superlattice, and the second sub-layer of the second superlattice are all GaN layers, the second sub-layer of the first superlattice is an AlN layer, the fourth sub-layer of the first superlattice is an InN layer, and the first sub-layer of the second superlattice is an MgN layer;

[0046] Growing a two-dimensional undoped GaN layer, an N-type doped GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type doped GaN layer, and a contact layer on the three-dimensional island layer in sequence.

[0047] Among them, the growth temperature of both the first superlattice layer 31 and the second superlattice layer 32 is 800 - 1000 °C, and the growth pressure is 50 - 200 torr.

[0048] On the other hand, the light-emitting diode proposed in the embodiments of the present invention includes the above-mentioned epitaxial wafer.

[0049] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to related embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0050] Embodiment 1

[0051] Provide a sapphire substrate;

[0052] Transfer the substrate into an MOCVD system and perform in-situ annealing treatment in a hydrogen atmosphere. Among them, the annealing temperature is 1000°C - 1200°C, the annealing pressure is 150 Torr - 500 Torr, and the annealing time is between 5 minutes and 10 minutes;

[0053] After the annealing is completed, grow an AlGaN layer on the substrate under the conditions of a growth temperature of 600 - 900°C and a growth pressure of 50 - 200 torr to form a buffer layer with a thickness of 20 - 50 nm. Among them, the Al component of AlGaN is less than 1.0;

[0054] After the buffer layer is grown, control the growth temperature to 800 - 1000°C and the growth pressure to 50 - 200 torr, and grow GaN / AlN / GaN / InN / GaN layers in a preset cycle in sequence to grow the first superlattice layer. Then, grow MgN / GaN layers in a preset cycle on the last GaN layer in sequence to form the second superlattice layer, thereby growing a three-dimensional island layer on the buffer layer;

[0055] After the three-dimensional island layer is grown, adjust the temperature to 1050°C - 1200°C, adjust the growth pressure to 100 Torr - 300 Torr, and grow a two-dimensional undoped GaN layer with a growth thickness of 1.0 to 3.0 microns; after the growth of the two-dimensional undoped GaN layer is completed, under the conditions of a growth temperature of 1100°C - 1200°C and a pressure of 100 Torr - 300 Torr, grow a Si-doped N-type GaN layer with a thickness between 1.0 - 3.0 microns, and the Si doping concentration is 10 19 cm -3 -10 20 cm -3 between;

[0056] After the growth of the N-type doped GaN layer is completed, 5 to 12 cycles of InGaN / GaN layers are grown to form a multi-quantum well layer, where InGaN is the well layer and GaN is the barrier layer. The thickness of a single InGaN well layer is 2 - 4 nm, the growth temperature is 800°C - 900°C, the growth pressure is 100 Torr to 300 Torr, the thickness of a single GaN barrier layer is 8 - 20 nm, the growth temperature is 900°C - 1000°C, and the growth pressure is 100 Torr to 300 Torr;

[0057] After the growth of the multi-quantum well layer, an AlGaN layer with a growth thickness between 20 nm and 100 nm is grown at a growth temperature of 1000°C and 1100°C and a growth pressure of 50 Torr to 100 Torr to form an electron blocking layer, where the Al component is between 0.1 - 0.5;

[0058] After the growth of the electron blocking layer, a P-type doped GaN layer with a thickness between 30 nm and 200 nm is grown at a growth temperature of 950°C - 1050°C and a growth pressure of 100 Torr - 600 Torr, where the Mg doping concentration is between 10 19 cm -3 -10 20 cm -3 ;

[0059] After the growth of the P-type doped GaN layer is completed, a GaN layer with a thickness between 10 nm and 50 nm is grown under the conditions of a growth temperature range of 1000°C - 1100°C and a growth pressure range of 100 Torr - 300 Torr to form a contact layer;

[0060] After the growth of the epitaxial structure is completed, the temperature of the reaction chamber is lowered, and annealing treatment is performed in a nitrogen atmosphere. The annealing temperature range is 650°C - 850°C, and the annealing treatment is performed for 5 to 15 minutes until the epitaxial growth at room temperature is completed.

[0061] In addition, in specific implementation, trimethylaluminum (TMAl), trimethylgallium or triethylgallium (TMGa or TEGa), trimethylindium (TMIn), and ammonia are used as the precursors of group III sources and group V sources respectively, silane and bis(cyclopentadienyl)magnesium are used as the precursors of N-type dopants and P-type dopants respectively, and nitrogen and hydrogen are used as carrier gases.

[0062] Please refer to Table 1, which shows the corresponding performance data of 9 groups of epitaxial wafers prepared by using the preparation method in Embodiment 1 of the present invention above. Among them, the growth thicknesses of the second and third sub-layers of the first superlattice in the three-dimensional island layer are mainly changed.

[0063] Table 1

[0064]

[0065] Please refer to Table 2, which shows the corresponding performance data of 9 groups of epitaxial wafers prepared by adopting the preparation method in the above Embodiment 1 of the present invention. Among them, the growth temperature and pressure of the first superlattice layer in the three-dimensional island layer are mainly changed.

[0066] Table 2

[0067]

[0068] Please refer to Table 3, which shows the corresponding performance data of 9 groups of epitaxial wafers prepared by adopting the preparation method in the above Embodiment 1 of the present invention. Among them, the growth temperature and pressure of the first superlattice layer in the three-dimensional island layer are mainly changed.

[0069] Table 3

[0070]

[0071]

[0072] In addition, the above performances of the epitaxial wafers prepared from the existing three-dimensional island layer are tested, and the data in Table 4 are obtained. It should be noted that the existing three-dimensional island layers are all composed of GaN layers. Moreover, in order to ensure the reliability of the experiment, except that the structures and preparation methods of the three-dimensional island layers are different, the process parameters of the other layers for preparing the epitaxial wafers are kept consistent.

[0073] Table 4

[0074] Existing three-dimensional island layer XRD-(002) (Half-width of the preset plane) (arcsec) 186 XRD-(102) (Half-width of the preset plane) (arcsec) 237 Antistatic yield rate (%) 93.5

[0075] Combining Tables 1 to 4, it can be clearly seen that the surface defect degree of the epitaxial wafers prepared by the three-dimensional island layer of the embodiment of the present invention is significantly reduced and the antistatic yield is significantly improved. Furthermore, the crystal quality of the epitaxial wafers has been significantly improved.

[0076] In addition, combining Table 1, it can be clearly seen that the thicknesses of the AlN layer and the InN layer in the first superlattice layer GaN / AlN / GaN / InN / GaN in the three-dimensional island layer both have a certain influence on the improvement of the crystal quality of the epitaxial wafers. Moreover, reasonable thickness ranges all have a certain promoting effect on the improvement of the crystal quality. When the thicknesses of both the AlN layer and the InN layer are 2.0 nm, the improvement of the crystal quality of the epitaxial wafers is stably at a better value.

[0077] It can be clearly seen from Table 2 that the thickness of the first superlattice layer in the three-dimensional island layer is fixed, and both temperature and pressure have a certain impact on the improvement of the crystal quality of the epitaxial wafer. A reasonable temperature range and pressure range both have a certain promoting effect on the improvement of crystal quality. Moreover, when the growth temperature is 850 °C and the growth pressure is 100 torr, the improvement of the crystal quality of the epitaxial wafer is stably at a better value.

[0078] It can be clearly seen from Table 3 that the thickness of the first sub-layer MgN of the second superlattice layer, temperature, and pressure all have a certain impact on the improvement of the crystal quality of the epitaxial wafer. A reasonable temperature range and pressure range both have a certain promoting effect on the improvement of crystal quality. Moreover, when the growth temperature is 900 °C, the growth pressure is 150 torr, and the growth thickness is 3.0 nm, the improvement of the crystal quality of the epitaxial wafer is stably at a better value.

[0079] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent for the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention shall be subject to the appended claims.

Claims

1. An epitaxial wafer, comprising a three-dimensional island layer, Characterized in that, The three-dimensional island layer comprises a first superlattice layer and a second superlattice layer which are sequentially stacked; The first superlattice layer comprises a first superlattice first sub-layer, a first superlattice second sub-layer, a first superlattice third sub-layer, a first superlattice fourth sub-layer and a first superlattice fifth sub-layer which are sequentially stacked alternately at a preset period; The second superlattice layer comprises a second superlattice first sub-layer and a second superlattice second sub-layer which are sequentially stacked alternately on the last first superlattice fifth sub-layer at a preset period; Wherein, the first superlattice first sub-layer, the first superlattice third sub-layer, the first superlattice fifth sub-layer and the second superlattice second sub-layer are all GaN layers, the first superlattice second sub-layer is an AlN layer, the first superlattice fourth sub-layer is an InN layer, and the second superlattice first sub-layer is an MgN layer; The epitaxial wafer further comprises a substrate, a buffer layer, a two-dimensional undoped GaN layer, an N-type doped GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type doped GaN layer and a contact layer; The buffer layer, the three-dimensional island layer, the two-dimensional undoped GaN layer, the N-type doped GaN layer, the multi-quantum well layer, the electron blocking layer, the P-type doped GaN layer and the contact layer are sequentially stacked on the substrate.

2. The epitaxial wafer according to claim 1, Characterized in that, Within a single period of the first superlattice layer, the growth thickness of the first superlattice second sub-layer is 1-5 nm, and the growth thickness of the first superlattice fourth sub-layer is 1-5 nm.

3. The epitaxial wafer according to claim 1 or 2, Characterized in that, Within a single period of the first superlattice layer, the growth thickness of the first superlattice first sub-layer is 10-15 nm, the growth thickness of the first superlattice third sub-layer is 10-15 nm, and the growth thickness of the first superlattice fifth sub-layer is 10-15 nm.

4. The epitaxial wafer according to claim 1, Characterized in that, Within a single period of the second superlattice layer, the growth thickness of the second superlattice second sub-layer is 10-20 nm.

5. The epitaxial wafer according to claim 1 or 4, Characterized in that, Within a single period of the second superlattice layer, the growth thickness of the second superlattice first sub-layer is 1-5 nm.

6. The epitaxial wafer according to claim 1, Characterized in that, The preset period of the first superlattice layer is 10-15 times, and the preset period of the second superlattice layer is 10-20 times.

7. A method for preparing an epitaxial wafer, Characterized in that, For preparing the epitaxial wafer according to any one of claims 1 to 6, the method for preparing the epitaxial wafer comprises: Providing a substrate; Growing a buffer layer on the substrate; On the buffer layer, a first superlattice layer is formed by alternately growing a first sub-layer of the first superlattice, a second sub-layer of the first superlattice, a third sub-layer of the first superlattice, a fourth sub-layer of the first superlattice, and a fifth sub-layer of the first superlattice in a preset period. Then, on the last fifth sub-layer of the first superlattice, a second superlattice layer is formed by alternately growing a first sub-layer of the second superlattice and a second sub-layer of the second superlattice in a preset period to grow a three-dimensional island layer. Among them, the first sub-layer of the first superlattice, the third sub-layer of the first superlattice, the fifth sub-layer of the first superlattice, and the second sub-layer of the second superlattice are all GaN layers, the second sub-layer of the first superlattice is an AlN layer, the fourth sub-layer of the first superlattice is an InN layer, and the first sub-layer of the second superlattice is an MgN layer; a two-dimensional undoped GaN layer, an N-type doped GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type doped GaN layer, and a contact layer are sequentially grown on the three-dimensional island layer.

8. The method for preparing an epitaxial wafer according to claim 7, wherein, the growth temperature of both the first superlattice layer and the second superlattice layer is 800 - 1000 °C, and the growth pressure of both is 50 - 200 torr.

9. A light-emitting diode, wherein, it includes the epitaxial wafer according to any one of claims 1 to 6.

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