A supercapacitor charging and discharging control circuit and control method for an electricity meter

Abstract

A supercapacitor charging and discharging control circuit and method for an electricity meter, relating to the field of measuring electrical variables, is disclosed. The control circuit includes a power supply circuit connected to the main power input and a supercapacitor charging and discharging circuit. The power supply circuit is connected to a summarizing switching circuit, and the supercapacitor charging and discharging circuit is connected to the switching circuit. The output of the summarizing switching circuit provides voltage output to the electricity meter. The summarizing switching circuit includes a first input, a second input, a switching circuit connecting the first and second inputs, and an output connected to the switching circuit. The control method includes acquiring the state of the supercapacitor, determining the state transition within a certain time, and controlling the charging duty cycle accordingly. This invention reduces the waste of stored charge; it uses general-purpose chips to build the circuit, reducing usage costs; and it monitors the supercapacitor state in real time and adjusts the charging duty cycle, reducing the possibility of damage to the supercapacitor and extending its lifespan.

Description

Technical Field

[0001] This invention relates to the field of measuring electrical variables, and more particularly to electrical energy metering, specifically a supercapacitor charging and discharging control circuit and control method for an energy meter. Background Technology

[0002] With the development of smart grids, smart meters, an important component of the smart grid's electricity consumption, have been installed in almost every household after more than a decade of development and use. Their advantages, such as high accuracy and multiple functions, have been widely recognized in the industry. Their remote meter reading, local and main station settlement and fee control, and data security all adopt the latest technologies.

[0003] Clock malfunctions caused by low battery voltage in smart meters are the biggest problem with them. To address this issue, the State Grid Corporation of China introduced battery-replaceable meters and rapidly adopted them. These meters combine replaceable batteries with supercapacitors, which has somewhat solved the battery problem. However, this has led to frequent supercapacitor issues, particularly due to improper circuit design causing the supercapacitors to be constantly under high voltage, resulting in low charging efficiency, rapid degradation, and shortened lifespan. This, in turn, can cause clock malfunctions in smart meters. Summary of the Invention

[0004] This invention ensures the safe, efficient, and long-life use of supercapacitors by switching power supply with low loss and controlling the charging and discharging process of supercapacitors, thereby guaranteeing the stable operation of the electricity meter.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A supercapacitor charging and discharging control circuit for an electricity meter includes a power supply circuit connected to the main power input and a supercapacitor charging and discharging circuit. The power supply circuit is connected to a summary switching circuit, and the supercapacitor charging and discharging circuit is connected to the switching circuit. The output of the summary switching circuit provides voltage output to the electricity meter.

[0007] The summary switching circuit includes a first input, a second input, a switching circuit connecting the first input and the second input, and an output connected to the switching circuit.

[0008] The first input includes a TVS diode CT2 with one end grounded and the other end connected in parallel, and two ceramic capacitors CC5 and CC6.

[0009] The second input includes a TVS diode CT1 with one end grounded and the other end connected in parallel, and two ceramic capacitors CC1 and CC2.

[0010] The output includes an electrolytic capacitor CC7 with one end grounded and the other end connected in parallel, and a ceramic capacitor CC8.

[0011] The switching circuit includes: a third diode CD3 connected to the first input; the third diode CD3 connected to the drain of the second PMOS transistor CQ2; a second diode CD2 connected between the drain and source of the second PMOS transistor CQ2; a resistor CR2 and a capacitor CC4 connected between the gate and source of the second PMOS transistor CQ2; the gate of the second PMOS transistor CQ2 connected to the drain of the NMOS transistor CQ3; ​​the source of the NMOS transistor CQ3 grounded; the gate of the NMOS transistor CQ3 grounded via resistor CR3; and the common terminal of the gate of the NMOS transistor CQ3 and resistor CR3 connected to the first input.

[0012] The first PMOS transistor CQ1 is connected to the second input, the first diode CD1 is connected across the drain and source of the first PMOS transistor CQ1, the capacitor CC3 is connected across the gate and source of the first PMOS transistor CQ1, and the resistor CR1 is grounded at one end and connected to the gate of the first PMOS transistor CQ1 at the other end.

[0013] The source (S) of the first PMOS transistor CQ1 and the source (S) of the second PMOS transistor CQ2 are connected to the output.

[0014] Furthermore, the supercapacitor charging and discharging circuit includes a charging circuit connected to the main power input, a supercapacitor connected to the charging circuit, and a discharging circuit connected to the supercapacitor.

[0015] The charging circuit includes a voltage chip PU1 and a current sensing resistor PR1. The two ends of the current sensing resistor PR1 are connected to the sampling pin of the MCU. The drain of the third PMOS transistor PQ1 is connected to the current sensing resistor PR1, the source is connected to the source of the fourth PMOS transistor PQ2, and the gate is connected to the gate of the fourth PMOS transistor PQ2. A resistor PR3 and a capacitor PC1 are connected across the gate and source of the third PMOS transistor PQ1. The gate of the fourth PMOS transistor PQ2 is connected to the drain of the first NMOS transistor PQ5. The source of the first NMOS transistor PQ5 is grounded, and the gate is connected to the control pin of the MCU via a resistor PR5. The gate of the first NMOS transistor PQ5 is also connected to a resistor PR8 that is grounded on the other end.

[0016] The drain of the fourth PMOS transistor PQ2 is connected to diode PD1 and inductor L1. Inductor L1 is connected to the interface PJ1 of the supercapacitor. A supercapacitor or a supercapacitor group connected in series is plugged into the interface PJ1 of the supercapacitor.

[0017] The discharge circuit includes a fifth PMOS transistor PQ3 whose D pole is connected to the interface PJ1 of the supercapacitor. The S pole of the fifth PMOS transistor PQ3 is connected to the S pole of a sixth PMOS transistor PQ4, and the G pole is connected to the G pole of the sixth PMOS transistor PQ4. A resistor PR4 and a capacitor PC2 are connected in parallel between the G pole and the S pole of the fifth PMOS transistor PQ3. The G pole of the sixth PMOS transistor PQ4 is connected to the D pole of a second NMOS transistor PQ6. The S pole of the second NMOS transistor PQ6 is grounded, and the G pole is connected to the control pin of the MCU via a resistor PR6. The G pole of the second NMOS transistor PQ6 is also connected to a resistor PR9 whose other end is grounded.

[0018] The D pole of the sixth PMOS transistor PQ4 is connected to a first sampling resistor PR2 and a second sampling resistor PR7. The common end of the first sampling resistor PR2 and the second sampling resistor PR7 is connected to the sampling pin of the MCU. The D pole of the sixth PMOS transistor PQ4 is the output end.

[0019] Based on the above circuit, the present invention also proposes a method for controlling the charging and discharging of supercapacitors for an electric energy meter, including:

[0020] Obtain the highest charging voltage V 充 , the full-charge voltage V0 of the supercapacitor, and set the upper limit I of the charging current 设 , and obtain the time T required for the supercapacitor to be fully charged 充 ; obtain the maximum charging duty cycle X max , X max = 100; obtain the number N of series-connected supercapacitors.

[0021] Collect the voltage across the current detection resistor to obtain the charging current Ic, collect the voltage across the second sampling resistor to obtain the voltage Uc of the current supercapacitor, and obtain the current charging duty cycle.

[0022] The charging and discharging method includes a charging method and a supercapacitor detection method.

[0023] The charging method includes the following steps.

[0024] Step A1: If Uc < N * V0 * 98%, execute Step A2; otherwise, execute Step A3.

[0025] Step A2: If the duty cycle of the charging pulse is 0, set the duty cycle X% = (Uc + 0.2) / V 充 , start charging, and return to Step A1; otherwise, if Ic ≥ I 设 , decrease the duty cycle; if Ic < I 设 , increase the duty cycle, and execute Step A1.

[0026] Step A3: Stop charging and execute Step A1.

[0027] The supercapacitor detection method includes:

[0028] Get the current charging duty cycle X;

[0029] Step B1: Detect the current state of the supercapacitor.

[0030] State A: Ic > 300mA, Uc < 1V, X < 10.

[0031] State B: Ic < 100mA, Uc > N*V0*98%, X > 90.

[0032] State C: Ic=0, Uc<1V,

[0033] State D: 250mA>Ic>150mA, Uc <N* V0*(N-1) / N,

[0034] State E: Ic < 100mA, Uc < 0.03V, X > 90°

[0035] State F: Ic < 100mA, Uc < 0.03V, X < 10,

[0036] Step B2: Start timing from the last time the capacitor's current state was detected, and determine the changes in the supercapacitor's state.

[0037] State change 1, in T 充 The supercapacitor transitions from state A to state B, indicating that the supercapacitor is functioning normally.

[0038] State change 2, in T 充 If the supercapacitor remains in state A, it indicates an internal short circuit. In this case, charging and discharging will be stopped and a warning will be issued.

[0039] State Change 3: Within 10 seconds, the supercapacitor changes from state B to state C, indicating that the supercapacitor has no capacitance characteristics. At this time, charging and discharging are turned off and a warning is issued.

[0040] State change 4, in T 充 The supercapacitor transitions from state A to state D, indicating internal damage. Adjusting the maximum duty cycle X... max Issue a warning;

[0041] State change 5, in T 充 When the supercapacitor transitions from state F to state E, it indicates that the supercapacitor's lifespan has expired or there is another malfunction. At this point, charging and discharging are stopped, and a warning is issued.

[0042] This invention improves the charging and discharging control circuit of supercapacitors on the one hand, and detects the capacitor state on the other hand, judges the capacitor condition based on the capacitor state and state transition, and controls the charging of the capacitor according to the judgment, and provides timely alarms in case of faults.

[0043] Beneficial effects: The circuit built using MOSFETs reduces the voltage drop from 0.4V to 0.1V, effectively increasing the capacitance and reducing the waste of stored charge; the use of general-purpose chips to build the circuit, eliminating the need for dedicated chips, significantly reduces operating costs; it effectively reduces the real-time requirements of the program for charge and discharge management, simplifying the development process; real-time monitoring of the supercapacitor's status and adjustment of the charging duty cycle reduce the possibility of damage to the supercapacitor and extend its lifespan. Attached Figure Description

[0044] Figure 1 This is a system composition diagram of the present invention.

[0045] Figure 2 It is a switching circuit.

[0046] Figure 3 It is a charging and discharging circuit.

[0047] Figure 4 This is a flowchart of the supercapacitor charging control process. Detailed Implementation

[0048] See Figure 1 A supercapacitor charging and discharging control circuit for an electricity meter is disclosed. The circuit includes a power supply circuit connected to the main power input and a supercapacitor charging and discharging circuit. The power supply circuit is connected to a switching circuit, and the supercapacitor charging and discharging circuit is connected to the switching circuit. The output of the switching circuit is combined to provide voltage output for the electricity meter.

[0049] See Figure 2 The switching circuit includes a first input, a second input, a switching circuit connecting the first and second inputs, and an output connected to the switching circuit. In the diagram, the first input is connected to... Figure 1 The power supply circuit in the middle, the second input connection Figure 1 The discharge circuit in the middle.

[0050] The first input includes a TVS diode CT2 with one end grounded and the other end connected in parallel, and two ceramic capacitors CC5 and CC6.

[0051] The second input includes a TVS diode CT1 with one end grounded and the other end connected in parallel, and two ceramic capacitors CC1 and CC2.

[0052] TVS diodes are transient diodes that can clamp a safe voltage to protect downstream circuitry. Ceramic capacitors can filter out differential-mode interference signals on the input line, making the voltage line more stable.

[0053] The output includes an electrolytic capacitor CC7 with one end grounded and the other end connected in parallel, and a ceramic capacitor CC8. The electrolytic capacitor has a certain charge storage capacity, which can make the output voltage more stable when the back-end power supply is switched to the front-end power supply, and is not affected by transient voltage changes caused by power switching.

[0054] The switching circuit includes:

[0055] The third diode CD3 is connected to the first input. The third diode CD3 is connected to the drain of the second PMOS transistor CQ2. The second diode CD2 is connected between the drain and source of the second PMOS transistor CQ2. The resistor CR2 and capacitor CC4 are connected between the gate and source of the second PMOS transistor CQ2. The gate of the second PMOS transistor CQ2 is connected to the drain of the NMOS transistor CQ3. The source of the NMOS transistor CQ3 is grounded. The gate of the NMOS transistor CQ3 is grounded through the resistor CR3. The common terminal of the gate of the NMOS transistor CQ3 and the resistor CR3 is connected to the first input.

[0056] The first PMOS transistor CQ1 is connected to the second input, the first diode CD1 is connected across the drain and source of the first PMOS transistor CQ1, the capacitor CC3 is connected across the gate and source of the first PMOS transistor CQ1, and the resistor CR1 is grounded at one end and connected to the gate of the first PMOS transistor CQ1 at the other end.

[0057] The source (S) of the first PMOS transistor CQ1 and the source (S) of the second PMOS transistor CQ2 are connected to the output.

[0058] Ceramic capacitors CC3 and CC4 serve as soft-start absorption capacitors for PMOS transistors CQ1 and CQ2, while resistor CR2 provides a defined voltage level to the gate of PMOS transistor CQ2 when NMOS transistor CQ3 is not conducting.

[0059] The above switching circuit design achieves single-phase conduction capability, low forward transient current voltage (<80mV@1A), low reverse leakage current (<1μA@-12V), and low cost, without using operational amplifiers, comparators, or various integrated chips.

[0060] Working process: When the first input is powered and stable, the current flows to the output through the third diode CD3 and the second PMOS transistor CQ2. At this time, the second PMOS transistor CQ2 is forward-biased, and there is no voltage difference between the G and S pins of the first PMOS transistor CQ1, so the first PMOS transistor CQ1 cannot be turned on.

[0061] When the first input power is off and the second input power is on, the NMOS transistor CQ3 is turned off due to insufficient front-end voltage at this time. The second PMOS transistor CQ2 is not conducting, and the first PMOS transistor CQ1 is conducting, switching to the second input power supply. When the first input power is on, the NMOS transistor CQ3 conducts, and it returns to the first power supply again.

[0062] In the supercapacitor matching circuit, ordinary rectifier diodes are generally used. Advantages: Unidirectional conductivity, small reverse leakage current; Disadvantages: Large forward voltage difference, uncertain voltage difference under small current. When used in conjunction with supercapacitors, it will cause waste of part of the supercapacitor's corresponding capacity due to voltage drop, and large reverse leakage current, resulting in too high charging voltage and affecting the life of the supercapacitor.

[0063] Using MOS transistors can effectively solve the above problems. MOS transistors, advantages: small forward voltage difference, large transient current, small leakage current; Disadvantages: Do not have unidirectional conductivity, and additional control logic is required to prevent reverse leakage.

[0064] The above circuit can meet the design requirements.

[0065] When using a conventional diode, due to a certain voltage drop in the diode, a voltage drop (about 0.3V) will occur before the supercapacitor discharges. The two voltage drops can be close to 1V. If the supercapacitor is 5V and the required voltage is 3.3V, then the actual charge used by the supercapacitor (the available charge value of the capacitor is the product of the effective voltage and the capacitance value) is:

[0066] Q = C * U = C * (5V - 3.3V - 1V) = 0.7C

[0067] Q is energy, C is capacitance value, and U is the voltage difference used.

[0068] If the above switching circuit is used, due to the absence of the forward voltage drop of the diode, the actual energy used is:

[0069] Q = C * U = C * (5V - 3.3V - 0.3V) = 1.4C

[0070] It can be seen that the above circuit realizes low-loss switching and efficient utilization of charges.

[0071] See Figure 3 .

[0072] Design principle of supercapacitor charge and discharge circuit: mainly for the duty cycle control of charging, no duty cycle control for discharging. Since there is a switching circuit at the back end and voltage drop cannot occur on the actual load side, the default state of discharging here is常开.

[0073] The supercapacitor charge and discharge circuit includes a charging circuit connected to the main power input, a supercapacitor connected to the charging circuit, and a discharging circuit connected to the supercapacitor.

[0074] The charging circuit includes a voltage chip PU1 and a current sensing resistor PR1. The two ends of the current sensing resistor PR1 are connected to the sampling pin of the MCU. The drain of the third PMOS transistor PQ1 is connected to the current sensing resistor PR1, the source is connected to the source of the fourth PMOS transistor PQ2, and the gate is connected to the gate of the fourth PMOS transistor PQ2. A resistor PR3 and a capacitor PC1 are connected in parallel across the gate and source of the third PMOS transistor PQ1. The gate of the fourth PMOS transistor PQ2 is connected to the drain of the first NMOS transistor PQ5. The source of the first NMOS transistor PQ5 is grounded, and the gate is connected to the control pin of the MCU via resistor PR5. This gate is the charging control pin. The gate of the first NMOS transistor PQ5 is also connected to a resistor PR8 that is grounded on the other end.

[0075] The drain of the fourth PMOS transistor PQ2 is connected to diode PD1 and inductor L1. Inductor L1 is connected to the interface PJ1 of the supercapacitor. A supercapacitor or a supercapacitor group connected in series is plugged into the interface PJ1 of the supercapacitor.

[0076] The discharge circuit includes a fifth PMOS transistor PQ3 whose drain (D) is connected to the interface J1 of the supercapacitor. The source (S) of the fifth PMOS transistor PQ3 is connected to the source (S) of the sixth PMOS transistor PQ4, and the gate (G) is connected to the gate (G) of the sixth PMOS transistor PQ4. A resistor PR4 and a capacitor PC2 are connected in parallel across the gate (G) and source (S) of the fifth PMOS transistor PQ3. The gate (G) of the sixth PMOS transistor PQ4 is connected to the drain (D) of the second NMOS transistor PQ6. The source (S) of the second NMOS transistor PQ6 is grounded, and the gate (G) is connected to the control pin of the MCU via resistor PR6. This control pin is the discharge control pin. The gate (G) of the second NMOS transistor PQ6 is also connected to a resistor PR9, which is grounded on the other end.

[0077] The drain of the sixth PMOS transistor PQ4 is connected to the first sampling resistor PR2 and the second sampling resistor PR7. The common terminal of the first sampling resistor PR2 and the second sampling resistor PR7 is connected to the sampling pin of the MCU. The drain of the sixth PMOS transistor PQ4 is the output terminal.

[0078] In the charging circuit:

[0079] The voltage chip PU1 is connected to two parallel ceramic capacitors PC3, PC4, PC5, and PC6, with one end of each capacitor grounded. These components create a stable constant voltage, high current power output to prevent overvoltage charging of the downstream supercapacitor during the charging process.

[0080] PR1 is a current sensing resistor. The two ends of PR1 are connected to the sampling pins of the MCU to collect the voltage at the terminals of PR1 and calculate the charging current.

[0081] The third PMOS transistor PQ1, the fourth PMOS transistor PQ2, resistor PR3, ceramic capacitor PC1, the first NMOS transistor PQ5, resistor PR5, and resistor PR8 together form a controllable switch. Due to the dual PMOS transistors, when the first NMOS transistor PQ5 is not conducting, current cannot flow from left to right or from right to left. Ceramic capacitor PC1 acts as a soft-start capacitor for PQ1 and PQ2, reducing the large spikes generated during the turn-on and turn-off of the PMOS transistors. Resistor PR3 provides a stable voltage level to the gate (G) of PMOS transistors PQ1 and PQ2 when the first NMOS transistor PQ5 is not conducting.

[0082] Diode PD1 and inductor L1 act as a smoothing filter. Due to the continuous switching of the front-end PMOS transistor, unstable charging levels are generated. After filtering by inductor L1, the charging becomes more stable. When the PMOS transistor is on, it provides the inductor current. Due to the characteristics of inductance, the current generated in the inductor cannot change abruptly. Diode PD1 can provide the inductor current when the PMOS transistor is off.

[0083] In the discharge circuit:

[0084] The fifth PMOS transistor PQ3, the second PMOS transistor PQ4, resistor PR4, ceramic capacitor PC2, the second NMOS transistor PQ6, resistor PR6, and resistor PR9 together form a controllable switch. Due to the dual PMOS transistors, when the second NMOS transistor PQ6 is not conducting, current cannot flow from left to right or from right to left. Ceramic capacitor PC2 acts as a soft-start capacitor for PQ3 and PQ4, reducing the large spikes generated during the turn-on and turn-off of the PMOS transistors. Resistor PR4 provides a stable voltage level to the gate (G) of PMOS transistors PQ3 and PQ4 when the second NMOS transistor PQ6 is not conducting.

[0085] The first sampling resistor PR2 and the second sampling resistor PR7 form a monitoring loop. When PMOS transistors PQ3 and PQ4 are turned on, the first sampling resistor PR2 and the second sampling resistor PR7 are working. Due to the voltage divider characteristic of the resistors, after obtaining the voltage across the second sampling resistor PR7, the output voltage value can be deduced. Based on different voltage values, the state of the supercapacitor can be determined.

[0086] In existing technologies, the commonly used charging method for electricity meters is to charge supercapacitors using an LDO (Low Discharge Loop) and a current-limiting resistor, which is uncontrollable.

[0087] J1 is a supercapacitor or connection interface.

[0088] To ensure the safety of all components, the resistor value in this charging circuit is approximately 75Ω (resistance after parallel connection). The voltage output is 5.3V, which charges the capacitor through a diode with a voltage drop of approximately 0.3V.

[0089] As the voltage of the supercapacitor increases, the voltage drop across the supercapacitor decreases. At this point, the resistance of the charging current-limiting resistor remains unchanged, and the charging current decreases. This process takes a long time to ensure that the supercapacitor is fully charged, and the power consumption generated by the current flowing through the current-limiting resistor is all released as heat, resulting in low actual charging efficiency.

[0090] In this embodiment, the charging circuit uses a controllable switch, and the voltage chip PU1 output can provide overvoltage protection.

[0091] The supercapacitor is controlled by a program, and the original current-limiting resistor is replaced with an inductor. Due to the inductor's characteristic that the current cannot change abruptly, power is supplied by the voltage chip PU1 when the switching transistor is on, and by the freewheeling diode when the switching transistor is off. By continuously switching the transistor on and off, the charging current can be limited. The DC impedance of the inductor is much smaller than that of the current-limiting resistor in existing technology. Therefore, in practical applications, the current can be dynamically adjusted to maximize the charging current and increase the charging speed.

[0092] Since there is no current-limiting resistor, there is no significant power loss, which improves charging efficiency.

[0093] For charging according to existing technology, see [link / reference]. Figure 1 Assuming the main power input has a load capacity of 12V±1V and 600mA, the full-charge voltage of the supercapacitor is 5.5V, and the voltage of the supercapacitor is 0 at the beginning of charging.

[0094] To ensure simple control, an LDO is used for charging, with a current-limiting resistor R. Lim Select 50Ω, supercapacitor internal resistance R SC =145mΩ, R ALL =R Lim +R SC .

[0095] Uin is the LDO output. Assuming Uin = 5V, the charging current is:

[0096] Isc=Uin / R ALL =5V / (50Ω+145mΩ)≈99.71mA,

[0097] Power across the current-limiting resistor: Pr = Isc 2 ×R Lim =0.09971 2 ×50≈497.11mW

[0098] The efficiency value is: η=(Isc) 2 ×R SC ) / ( Isc 2 ×R All=145mΩ / 50.145Ω=0.00289.

[0099] Current-limiting resistors consume a lot of power and have very low efficiency. If the resistance is reduced further, the charging current will increase, resulting in even greater power loss.

[0100] When the supercapacitor is close to full charge (e.g., 4.9V), the charging current is:

[0101] Isc = (5V – 4.9V) / R Lim =0.1V / 50Ω=2mA.

[0102] At this point, the charging current gradually decreases, the charging speed slows down, and it becomes difficult to fully charge the battery.

[0103] Using the charging circuit provided by this invention, with inductor current limiting and a duty cycle of 10%, the equivalent charging voltage is:

[0104] Uc = Uin × 10% = 5V × 10% = 0.5V

[0105] Uin is the output of voltage chip PU1. In this embodiment, Uin = 5V.

[0106] Inductance 1mH DC resistance R L Approximately 1.15Ω, charging current:

[0107] Isc=Uc / R ALL =0.5V / (1.15Ω+145mΩ)≈386.10mA.

[0108] Power on inductor:

[0109] PL = Isc 2 ×R L =0.3861 2 ×1.15≈17.14mW.

[0110] For the remaining 90% of the cycle, the freewheeling diode provides freewheeling charge.

[0111] The efficiency value is: η=(Isc) 2 ×R sc ) / ( Isc 2 ×R All )= R sc / R All =145 mΩ / (1.15Ω+145mΩ) ≈0.11

[0112] The efficiency is greater than that of existing technologies. As the charging voltage increases, the duty cycle within one cycle increases, such as to 100%. When the supercapacitor is close to full charge (e.g., 4.9V), the charging current is:

[0113] Isc = (5V - 4.9V) / R All = 0.1V / (1.15Ω + 145mΩ) ≈ 77.22mA

[0114] At this time, the charging current decreases but is still greater than the charging current of the prior art, and it is easier to be fully charged than the prior art.

[0115] In summary, the charging efficiency of the present invention is improved, the charging current is large, and the charging speed of the super capacitor is faster.

[0116] Based on the above circuit, the present invention also proposes a method for controlling the charge and discharge of the super capacitor used in the electric energy meter, which includes two aspects.

[0117] First, obtain and set the following parameters: the highest charging voltage V 充 , the full - charge voltage V0 of the super capacitor, the time T for the super capacitor to be fully charged 充 , and the number N of series - connected super capacitors.

[0118] Set the upper limit I of the charging current 设 , the maximum charging duty cycle Xmax = 100, and obtain the current charging duty cycle.

[0119] The time T for the super capacitor to be fully charged 充 : when the charging voltage is V 充 , it is the time for the voltage of the super capacitor to be fully charged from 0V to V0.

[0120] In practical applications, multiple super capacitors are generally connected in series. In this embodiment, N = 2.

[0121] Collect the voltage Upr1 at both ends of the current - detection resistor PR1 to obtain the charging current:

[0122] Ic = Upr11÷Rpr1;

[0123] Collect the voltage Upr7 at both ends of the second sampling resistor PR7 to obtain the current voltage of the super capacitor:

[0124] Uc = Upr7÷Rpr7×(Rpr7 + Rpr2).

[0125] Charging control of the super capacitor:

[0126] Step A1: If Uc < N * V0 * 98%, execute Step A2; otherwise, execute Step A3.

[0127] Step A2: At this time, the super capacitor is not fully charged, and charging control is carried out. If the duty cycle of the charging pulse is 0 and charging is not started, set the duty cycle X%=(Uc + 0.2) / V 充 , start charging, and return to Step A1; otherwise, if Ic ≥ I设 , reduce the duty cycle if Ic < I 设 , increase the duty cycle, and execute step A1.

[0128] Step A3: When the super capacitor has been charged to 98% of full charge, it is considered fully charged. The MCU outputs a low level to the Charge terminal of PR5 to turn off the charging, execute step A1, and continue to monitor.

[0129] In step A2, when reducing the duty cycle, reduce V 充 *0.5%; when increasing the duty cycle, increase V 充 *0.4%. If V 充 is 5.7V, then the adjustment amount each time is to reduce or increase the equivalent charging voltage by 5.7V * 0.5 ≈ 28mV or 5.7V * 0.4 ≈ 23mV. When adjusting the duty cycle, ensure that the duty cycle is less than Xmax and greater than 0%.

[0130] The MCU adjusts the pulse width (i.e., the duty cycle) according to the detected charging current and outputs it to the Charge terminal of PR5 to adjust the charging voltage by turning on and off the controllable switch.

[0131] In this embodiment, the capacitor discharge is always on, and the MCU outputs a high level (duty cycle 100%) to the Discharge terminal of PR6.

[0132] Due to the real-time detection of the charging current and the real-time adjustment of the duty cycle, the current is maintained at a reasonable level, so that the charging voltage reaches V charge.

[0133] Super capacitor detection:

[0134] Step B1: Detect the current state of the super capacitor.

[0135] There can be one super capacitor or multiple super capacitors connected in series. Here, all super capacitors are regarded as one entity. When judging the state of the super capacitor, only care about the charging current Ic, the voltage Uc of the current super capacitor, and the charging duty cycle. According to the different values of the above parameters, there are very many states for the super capacitor. In this embodiment, only care about the following states:

[0136] State A: Ic > 300mA, Uc < 1V, X < 10: Initial charging;

[0137] State B: Ic < 100mA, Uc > N * V0 * 98%, X > 90: Almost fully charged;

[0138] State C: Ic = 0, Uc < 1V: Not started charging;

[0139] State D: 250mA > Ic > 150mA, Uc < N * V0 * (N - 1) / N: The capacitor voltage cannot rise;

[0140] State E: Ic < 100 mA, Uc < 0.03 V, X > 90: Excessive internal resistance;

[0141] State F: Ic < 100 mA, Uc < 0.03 V, X < 10: Small charging current;

[0142] Other numerical combinations can be defined as State G.

[0143] Step B2: Start timing from the last detection of the current state of the capacitor, and judge the change of the supercapacitor state:

[0144] State change 1: Within T 充 The supercapacitor changes from State A to State B, indicating that the supercapacitor is normal.

[0145] State change 2: Within T 充 The supercapacitor remains in State A unchanged, indicating that the supercapacitor is internally short-circuited. At this time, charge and discharge are turned off and a warning is issued.

[0146] State change 3: Within 10 seconds, the supercapacitor changes from State B to State C, indicating that the supercapacitor has no capacitance characteristics. At this time, charge and discharge are turned off and a warning is issued.

[0147] State change 4: Within T 充 The supercapacitor changes from State A to State D, indicating that the supercapacitor is internally damaged. Adjust the maximum duty cycle X max , and issue a warning.

[0148] State change 5: Within T 充 The supercapacitor changes from State F to State E, indicating that the supercapacitor has exhausted its life or other faults. At this time, charge and discharge are turned off and a warning is issued.

[0149] Steps B1 and B2 are executed synchronously.

[0150] Under normal circumstances, when the supercapacitor starts charging, after T 充 The voltage can generally be fully charged. The voltage of a single supercapacitor is close to V0. If it is a series of N supercapacitors, the voltage can be close to N * V0.

[0151] In State change 4, the supercapacitor changes from State A to State D. State D is 250 mA > Ic > 150 mA, Uc < N * V0 * (N - 1) / N, indicating that one of the supercapacitors is damaged. In this embodiment, N = 2, which is two supercapacitors in series, and the full charge voltage of each supercapacitor is 2.5 V. Modify the maximum duty cycle X max = X max * (N - 1) / N to ensure that overvoltage charging does not occur.

[0152] If three or more supercapacitors are connected in series, the maximum duty cycle can be further determined and modified. In this embodiment, if state change 4 is detected, a warning is issued and the supercapacitor is replaced. Therefore, only the case of damage to one supercapacitor is considered.

Claims

1. A supercapacitor charging and discharging control circuit for an electricity meter, the circuit comprising a power supply circuit connected to a main power input and a supercapacitor charging and discharging circuit, the power supply circuit being connected to a sum-and-go switching circuit, the supercapacitor charging and discharging circuit being connected to a switching circuit, the output of the sum-and-go switching circuit providing voltage output to the electricity meter, characterized in that: The aggregation switching circuit includes a first input, a second input, a switching circuit connecting the first input and the second input, and an output connecting the switching circuit. The first input includes a TVS diode CT2 with one end grounded and the other end connected in parallel, and two ceramic capacitors CC5 and CC6; The second input includes a TVS diode CT1 with one end grounded and the other end connected in parallel, and two ceramic capacitors CC1 and CC2; The output includes an electrolytic capacitor CC7 with one end grounded and the other end connected in parallel, and a ceramic capacitor CC8. The switching circuit includes: The third diode CD3 is connected to the first input. The third diode CD3 is connected to the drain of the second PMOS transistor CQ2. The second diode CD2 is connected across the drain and source of the second PMOS transistor CQ2. The resistor CR2 and capacitor CC4 are connected across the gate and source of the second PMOS transistor CQ2. The gate of the second PMOS transistor CQ2 is connected to the drain of the NMOS transistor CQ3. The source of the NMOS transistor CQ3 is grounded. The gate of the NMOS transistor CQ3 is grounded through the resistor CR3. The common terminal of the gate of the NMOS transistor CQ3 and the resistor CR3 is connected to the first input. The first PMOS transistor CQ1 is connected to the second input, the first diode CD1 is connected across the drain and source of the first PMOS transistor CQ1, the capacitor CC3 is connected across the gate and source of the first PMOS transistor CQ1, and the resistor CR1 is grounded at one end and connected to the gate of the first PMOS transistor CQ1 at the other end. The source (S) of the first PMOS transistor CQ1 and the source (S) of the second PMOS transistor CQ2 are connected to the output.

2. The supercapacitor charging and discharging control circuit for an energy meter according to claim 1, characterized in that: The supercapacitor charging and discharging circuit includes a charging circuit connected to the main power input, a supercapacitor connected to the charging circuit, and a discharging circuit connected to the supercapacitor. The charging circuit includes a voltage chip PU1 and a current sensing resistor PR1, with the two ends of the current sensing resistor PR1 connected to the sampling pin of the MCU. The drain of the third PMOS transistor PQ1 is connected to the current sensing resistor PR1, the source is connected to the source of the fourth PMOS transistor PQ2, and the gate is connected to the gate of the fourth PMOS transistor PQ2. A resistor PR3 and a capacitor PC1 are connected across the gate and source of the third PMOS transistor PQ1. The gate of the fourth PMOS transistor PQ2 is connected to the drain of the first NMOS transistor PQ5. The source of the first NMOS transistor PQ5 is grounded, and the gate is connected to the control pin of the MCU through a resistor PR5. The gate of the first NMOS transistor PQ5 is also connected to a resistor PR8 that is grounded on the other end. The D terminal of the fourth PMOS tube PQ2 is connected with the diode PD1 and the inductor L1, the inductor L1 is connected with the interface PJ1 of the super capacitor, and the super capacitor or the super capacitor group in series is inserted into the interface PJ1 of the super capacitor; The discharge circuit comprises a fifth PMOS tube PQ3 connected with the interface PJ1 of the super capacitor at the D terminal, the S terminal of the fifth PMOS tube PQ3 is connected with the S terminal of a sixth PMOS tube PQ4, the G terminal of the fifth PMOS tube PQ3 is connected with the G terminal of the sixth PMOS tube PQ4, and the resistor PR4 and the capacitor PC2 are connected in parallel between the G terminal and the S terminal of the fifth PMOS tube PQ3; The G terminal of the sixth PMOS tube PQ4 is connected with the D terminal of a second NMOS tube PQ6, the S terminal of the second NMOS tube PQ6 is grounded, the G terminal of the second NMOS tube PQ6 is connected with the control pin of the MCU through the resistor PR6, and the G terminal of the second NMOS tube PQ6 is also connected with the resistor PR9 grounded at the other end; The D terminal of the sixth PMOS tube PQ4 is connected with the first sampling resistor PR2 and the second sampling resistor PR7, and the common terminal of the first sampling resistor PR2 and the second sampling resistor PR7 is connected with the sampling pin of the MCU; The D terminal of the sixth PMOS tube PQ4 is an output terminal.

3. The super capacitor charging and discharging control circuit for the electric energy meter according to claim 2, characterized in that: The voltage chip PU1 is connected with two parallel capacitors at both ends, and one end of the capacitor is grounded.

4. A super capacitor charging and discharging control method for an electric energy meter, based on the super capacitor charging and discharging control circuit for the electric energy meter according to any one of claims 1-3, characterized in that: Get the highest charging voltage V 充 , the full voltage of the super capacitor V0, set the upper limit of the charging current I 设 , get the time T when the super capacitor is fully charged 充 ; Get the maximum duty cycle X of charging max , X max =100; Get the number of super capacitors in series N; The voltage across the current detection resistor (PR1) is collected to obtain the charging current Ic, and the voltage across the second sampling resistor (PR7) is collected to obtain the current voltage Uc of the super capacitor; The charging and discharging method comprises a charging method and a super capacitor detection method; The charging method comprises the following steps: Step A1, if Uc < N*V0*98%, step A2 is executed, otherwise step A3 is executed; Step A2, if the duty cycle of the charging pulse is 0, set the duty cycle X% = (Uc+0.2) / V 充 , start charging, return to step Al; otherwise, if Ic≥I 设 , decrease the duty cycle, if Ic<I 设 , increase the duty cycle, perform step Al; Step A3, the charging is closed, and step A1 is executed; The super capacitor detection method comprises: The current duty cycle X of the charging is obtained; Step B1, the current state of the super capacitor is detected: State A: Ic > 300mA, Uc < 1V, X < 10, State B: Ic < 100mA, Uc > N*V0*98%, X > 90, State C: Ic = 0, Uc < 1V, State D: 250mA > Ic > 150mA, Uc < N*V0*(N-1) / N, State E: Ic < 100mA, Uc < 0.03V, X > 90, State F: Ic < 100mA, Uc < 0.03V, X < 10, Step B2, the time since the last detection of the current state of the capacitor is counted, and the change of the state of the super capacitor is determined: State change 1, at T 充 The super capacitor is converted from state A to state B, indicating that the super capacitor is normal. State change 2, at T 充 The super capacitor keeps state A unchanged, which indicates that the super capacitor has internal short circuit. At this time, the charging and discharging is closed, and a warning is issued. State change 3, within 10 seconds, the super capacitor changes from state B to state C, indicating that the super capacitor has no capacitance characteristics, at this time the charging and discharging is closed, and a warning is issued; State change 4, within T 充 the supercap goes from state A to state D, indicating internal damage to the supercap, adjust maximum duty cycle X max , issue a warning; State change 5, at T 充 The supercap goes from state F to state E, indicating that the supercap is at the end of its life or has other faults, at which point the charge and discharge is turned off and a warning is issued.

5. The super capacitor charging and discharging control method for the electric energy meter according to claim 4, characterized in that: In step A2, when reducing the duty cycle, V 充 * 0.5%; when increasing the duty cycle, V 充 * 0.4%.

6. The super capacitor charging and discharging control method for the electric energy meter according to claim 4, characterized in that: In step A2, the duty cycle is less than X max greater than 0%.

7. The super capacitor charge-discharge control method for electric energy meter according to claim 4, characterized in that: Step B2 State change 4, maximum duty cycle X max = X max (N-1) / N.

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