Isolated switching converter and controller and control method thereof

Abstract

The application discloses an isolated switching converter, a controller and a control method thereof. The switching converter comprises a transformer with a primary winding and a secondary winding, a primary switch tube coupled to the primary winding, and a secondary switch tube coupled to the secondary winding. The control method comprises: sampling and holding the maximum value of the voltage across the secondary switch tube to provide a first voltage signal; providing a second voltage signal smaller than the first voltage signal based on the first voltage signal; starting timing when the voltage across the secondary switch tube reaches the second voltage signal and ending timing when the voltage across the secondary switch tube increases to the first voltage signal, and the timing time is a first time length; and adjusting the turn-on time length of the secondary switch tube in the second turn-on to make the first time length of the next switching cycle close to a first time threshold. According to the embodiment of the application, the primary switch tube can be completely turned on at zero voltage under a wide input and output range.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more particularly to isolated switching converters employing soft-switching technology, their controllers, and control methods. Background Technology

[0002] The Universal Serial Bus (USB) Power Delivery (PD) standard has begun to gain popularity among smart device and laptop manufacturers. The USB PD standard allows for higher power levels (up to 100 W) and adaptive output voltages (e.g., 5V~28V), a trend that demands higher power, faster speeds, and smaller isolated switching power supplies.

[0003] However, as silicon-based devices approach their theoretical performance limits, further performance improvements to existing isolated power supplies become more difficult, making it challenging to meet the higher power delivery requirements of the PD standard while maintaining high efficiency and low cost. Summary of the Invention

[0004] In view of one or more problems existing in the prior art, the present invention aims to provide an isolated switching converter and its controller and control method that can meet the higher power transmission requirements of the PD standard while maintaining high efficiency and low cost.

[0005] According to an embodiment of the present invention, a controller for an isolated switching converter includes a transformer having a primary winding and a secondary winding, a primary switching transistor coupled to the primary winding, and a secondary switching transistor coupled to the secondary winding. The controller includes: a maximum value detection circuit coupled to the secondary switching transistor to detect the voltage across the secondary switching transistor and providing a first voltage signal representing the maximum value of the voltage across the secondary switching transistor; a voltage divider circuit receiving the first voltage signal and providing a second voltage signal less than the first voltage signal; a timing circuit starting timing when the voltage across the secondary switching transistor reaches the second voltage signal and ending timing when the voltage across the secondary switching transistor increases to the first voltage signal, the timing time of the timing circuit being a first duration; and a conduction duration control circuit providing a conduction duration control signal to control the conduction duration of the secondary switching transistor during a second conduction, such that the first duration of the next switching cycle is close to a first time threshold.

[0006] An isolated switching converter according to an embodiment of the present invention includes the controller as described above.

[0007] According to an embodiment of the present invention, a control method for an isolated switching converter includes a transformer having a primary winding and a secondary winding, a primary switching transistor coupled to the primary winding, a secondary switching transistor coupled to the secondary winding, and an isolation circuit. The control method includes: sampling and holding the maximum value of the voltage across the secondary switching transistor to provide a first voltage signal; providing a second voltage signal less than the first voltage signal based on the first voltage signal; starting a timer when the voltage across the secondary switching transistor reaches the second voltage signal and ending the timer when the voltage across the secondary switching transistor increases to the first voltage signal, the timer duration being a first duration; and adjusting the conduction duration of the secondary switching transistor during its second conduction so that the first duration of the next switching cycle is close to a first time threshold.

[0008] In embodiments of the present invention, based on a comparison between a first duration and a first time threshold, the conduction duration of the secondary switch during its second turn-on is adjusted in real time, so that the first duration of the next switching cycle approaches the first time threshold, thereby enabling the primary switch to achieve near-theoretical zero-voltage conduction. Furthermore, employing a wide-bandgap device with a smaller output capacitance and higher operating frequency than silicon-based devices can further reduce the voltage value of the primary switch during zero-voltage conduction, minimizing energy consumption and reducing the size of the isolated switching converter, thus achieving higher power density and better efficiency. Attached Figure Description

[0009] Figure 1 This is a block diagram of an isolated switching converter 100 according to an embodiment of the present invention;

[0010] Figure 2 This is a flowchart of a control method 200 for an isolated switching converter 100 according to an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram illustrating the principle of conduction duration control according to an embodiment of the present invention;

[0012] Figure 4 This is a circuit schematic diagram of a controller 30A for an isolated switching converter according to an embodiment of the present invention;

[0013] Figure 5 This is a waveform diagram of an isolated switching converter according to an embodiment of the present invention;

[0014] Figure 6 The circuit diagram is of a timing circuit 303A and a threshold generation circuit 304A according to an embodiment of the present invention.

[0015] Figure 7 A circuit diagram of a conduction duration control circuit 305A according to an embodiment of the present invention;

[0016] Figure 8 This is a flowchart of a method 204 for generating a conduction duration control signal according to an embodiment of the present invention. Detailed Implementation

[0017] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0018] Throughout this specification, references to “an embodiment,” “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “connected to” or “coupled” to another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0019] This invention can be applied to any isolated switching converter. In the following detailed description, for the sake of brevity, only a flyback converter will be used as an example to explain the specific working principle of this invention.

[0020] Figure 1 This is a block diagram of an isolated switching converter 100 according to an embodiment of the present invention. Figure 1As shown, the isolated switching converter 100 includes a transformer T, a primary switch 10, a secondary switch 20, and a controller 30. The transformer T has a primary winding, a secondary winding, and an auxiliary winding to provide isolation. Both the primary and secondary windings have a first terminal and a second terminal. The first terminal of the primary winding receives the input voltage Vin, and the first terminal of the secondary winding provides the DC output voltage Vo. The second terminal is coupled to the secondary reference ground (SGND). The primary switch 10 is coupled between the second terminal of the primary winding and the primary reference ground (PGND). The secondary switch 20 is coupled between the second terminal of the secondary winding and the load. However, those skilled in the art will understand that the secondary switch 20 can also be coupled between the first terminal of the secondary winding and the load.

[0021] The primary switch 10 is coupled to the primary winding to control the transfer of energy stored in the primary winding to the secondary winding. The secondary switch 20 is coupled to the secondary winding and acts as a synchronous rectifier diode instead of a conventional rectifier diode to reduce losses and improve the efficiency of the isolated switching converter 100. Furthermore, by utilizing parasitic elements of the circuit (such as the output capacitance of the primary switch 10 and the magnetizing inductance of the transformer) to turn on the primary switch 10 under zero-voltage conditions, switching losses can be further reduced.

[0022] exist Figure 1 In the illustrated embodiment, the switching converter 100 operates in discontinuous current mode, with the primary switch 10 conducting at zero voltage. Before the primary switch 10 achieves zero-voltage conduction, the secondary switch 20 is turned on twice. Specifically, the first conduction of the secondary switch 20 ends after the current flowing through it crosses zero, and then the secondary switch 20 is turned on again to generate a negative current flowing through the magnetizing inductance of the transformer T. This negative current is used to discharge the output capacitor of the primary switch 10. In embodiments of the invention, based on a first duration t within each switching cycle... D Compared with the first time threshold t D_ref By comparing the two, the on-time TON of the second turn-on of the secondary switch 20 is adjusted in real time to fully discharge the output capacitor of the primary switch 10, so that the first duration t in the subsequent switching cycle is adjusted accordingly. D Approaching the first time threshold t D_ref This achieves full zero-voltage turn-on (Full ZVS) for primary switch 10.

[0023] exist Figure 1In the illustrated embodiment, the controller 30 includes a maximum value detection circuit 301, a voltage divider circuit 302, a timing circuit 303, a threshold generation circuit 304, a conduction duration control circuit 305, a secondary logic circuit 306, a second turn-off detection circuit 307, an isolation circuit 308, a voltage zero-crossing detection circuit 309, and a primary logic circuit 310. In one embodiment, the controller 30 includes an integrated circuit chip and multiple pins.

[0024] like Figure 1 As shown, the maximum value detection circuit 301 is coupled to the drain terminal of the secondary switch 20 via pin SRD to detect the voltage V across the secondary switch. Sec_SR It also provides a first voltage signal V at the output terminal, representing the maximum voltage across the secondary switch. SRD The voltage divider circuit 302 is coupled to the output of the maximum value detection circuit 301 to receive the first voltage signal V. SRD It provides a second voltage signal k*V at its output terminal. SRD Where k is a value greater than 0 and less than 1. In one embodiment, the voltage divider circuit 302 divides the first voltage signal V... SRD Voltage division is performed to provide a second voltage signal k*V. SRD The voltage divider circuit 302 may include a resistor divider or a capacitor divider. In another embodiment, the voltage divider circuit 302 divides the bias voltage signal (1-k)*V SRD From the first voltage signal V SRD Subtract from the middle to provide a second voltage signal k*V at the output. SRD .

[0025] exist Figure 1 In the illustrated embodiment, the timing circuit 303 has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal is coupled to the drain terminal of the secondary switching transistor 20 via pin SRD, and receives the voltage V across the secondary switching transistor 20. Sec_SR The second input terminal is coupled to the output terminal of the maximum value detection circuit 301 to receive the first voltage signal V. SRD The third input terminal is coupled to the output terminal of the voltage divider circuit 302 to receive the second voltage signal k*V. SRD The timing circuit 303 draws voltage V from the secondary switching transistor. Sec_SR Increase to the second voltage signal k*V SRD The timing starts when the voltage V across the secondary switch is reached. Sec_SR Increase to the first voltage signal V SRD When the timer ends, the timing circuit 303 has a timing duration of the first duration t. D In one embodiment, the timing circuit 303 provides a first control signal T at its output. D The first control signal TD The effective duration width is equal to the first duration t D In one embodiment, the timing circuit 303 may include a combination of multiple comparators and gate circuits.

[0026] exist Figure 1 In the illustrated embodiment, the threshold generation circuit 304 is used to generate a second control signal T. DREF The second control signal T DREF The effective duration width is equal to the first time threshold t D_ref In one embodiment, the threshold generation circuit 304 is coupled to a reference resistor R external to the controller 30 via a pin ZVS. TD In one embodiment, the user can select a reference resistor R. TD To set the first time threshold t D_ref .

[0027] exist Figure 1 In the illustrated embodiment, the conduction duration control circuit 305 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a first control signal T. D The second input terminal receives the second control signal T. DREF Based on the first control signal T D Second control signal T DREF The conduction duration control circuit 305 will control the first duration t D Compared with the first time threshold t D_ref In comparison, based on the comparison result, the conduction duration TON of the secondary switch 20 is adjusted for the second conduction, and a conduction duration control signal ZOFF is generated at its output to control the turn-off of the secondary switch 20, so that the first duration t in the next switching cycle is adjusted. D Compared with the first time threshold t D_ref Approaching. In one embodiment, when the first duration t D Less than the first time threshold t D_ref When the first duration t is reached, the conduction duration control circuit 305 extends the conduction duration TON; when the first duration t is reached... D Greater than the first time threshold t D_ref At that time, the conduction duration control circuit 305 shortens the conduction duration TON so that the first duration t of the subsequent switching cycle is longer. D Approaching the first time threshold t D_ref .

[0028] Continue as Figure 1As shown, the secondary logic circuit 306 is coupled to the conduction duration control circuit 305 to receive the conduction duration control signal ZOFF. Based on the conduction duration control signal ZOFF, a secondary control signal CTRLS is generated and coupled to the control terminal of the secondary switch 20 via the pin SDrv to control the conduction and turn-off of the secondary switch 20.

[0029] When the second turn-off detection circuit 307 detects the second turn-off of the secondary switch 20, it provides a primary turn-on enable signal PRON to the input of the isolation circuit 308. The isolation circuit 308 generates a synchronization signal SYNC at its output, electrically isolated from the primary turn-on enable signal PRON, to achieve electrical isolation between the primary and secondary sides. The isolation circuit 308 may include an optocoupler, a transformer, a capacitive isolation device, or any other suitable electrical isolation device. In other embodiments, the isolation circuit 308 may be located external to the controller integrated circuit.

[0030] The voltage zero-crossing detection circuit 309 detects the voltage V across the primary switching transistor 10. Pri_DS The system detects whether the voltage has crossed zero and generates a zero-crossing detection signal PON. In one embodiment, the zero-crossing detection circuit 309 is coupled to the auxiliary winding of the transformer T and receives the voltage V across the primary switch via the ZCD pin of the controller 30. Pri_DS The detection signal V ZCD and the voltage detection signal V ZCD With zero-crossing threshold V ZCD_TH A comparison is performed, and a zero-crossing voltage detection signal PON is provided at the output. In one embodiment, the zero-crossing threshold V... ZCD_TH It is 20mV.

[0031] Primary logic circuit 310 is coupled to the output of isolation circuit 308 to receive synchronization signal SYNC, and coupled to voltage zero-crossing detection circuit 309 to receive voltage zero-crossing detection signal PON. Based on the synchronization signal SYNC and the voltage zero-crossing detection signal PON, it generates primary control signal CTRLP, and provides this primary control signal to the control terminal of primary switch 10 via pin PDrv to control primary switch 10. In some embodiments, when the synchronization signal SYNC arrives and the voltage V across the primary switch 10... Pri_DS At zero crossing, the primary switch 10, after a delay t Delay It is then turned on by zero voltage.

[0032] Generally, silicon-based devices (such as MOSFETs) require significant energy to fully discharge their large output capacitance to achieve zero-voltage turn-on. In practical applications, due to cost and loss considerations, the output capacitance of silicon-based devices is often not fully discharged. Therefore, when implementing zero-voltage turn-on technology, only partial zero-voltage turn-on can be achieved, and the voltage across the silicon-based device is often not 0V but 15~25V. Such partial zero-voltage turn-on not only increases turn-on losses but also causes large voltage spikes across the secondary switch, generating electromagnetic interference.

[0033] In one embodiment of the invention, the primary switch 10 may include an emerging wide-bandgap device, such as a gallium nitride (GaN) or silicon carbide (SiC) based device, instead of a conventional silicon-based device. Wide-bandgap devices can operate at higher switching frequencies without sacrificing efficiency, while having a much lower output capacitance than silicon-based devices. Therefore, such devices will further reduce the size of the isolation converter while providing a significant efficiency improvement. Furthermore, the on-time control circuit 305 of the invention can determine the on-time based on a first duration t detected in the current cycle. D Compared with the first time threshold t D_ref Based on the comparison results, the on-time TON of the secondary switch is dynamically adjusted to adaptively achieve complete discharge of the output capacitor of the primary power switch according to the actual circuit operation. In one embodiment of the invention, the zero-crossing threshold V... ZCD_TH It is in the tens of millivolts, which is much smaller than the voltage at which a silicon-based device conducts at zero voltage.

[0034] Figure 2 This is a flowchart of a control method 200 for an isolated switching converter 100 according to an embodiment of the present invention. The control method 200 includes steps 201 to 204.

[0035] In step 201, the maximum value of the voltage across the secondary switch 20 is sampled and held to provide a first voltage signal V. SRD .

[0036] In step 202, based on the first voltage signal, a voltage value less than the first voltage signal V is provided. SRD The second voltage signal k*V SRD In one embodiment, k is a number greater than 0 and less than 1.

[0037] In one embodiment, for the first voltage signal V SRD Perform voltage division to provide a second voltage signal k*V SRD In another embodiment, a bias voltage signal (1-k)*V is used. SRD From the first voltage signal V SRD Subtract from the middle to provide the second voltage signal k*VSRD .

[0038] In step 203, the voltage V across the secondary switch is... Sec_SR Reaching the second voltage signal k*V SRD The timing starts at a certain time and ends when the voltage V across the secondary switch transistor is reached. Sec_SR Increase to the first voltage signal V SRD The timer has ended, and the timing duration is the first duration t. D .

[0039] In step 204, the conduction duration TON of the second turn-on of the secondary switch 20 is adjusted so that the first duration t of the next switching cycle is adjusted. D and the first time threshold t D_ref Approaching. In one embodiment, when the first duration t D Less than the first time threshold t D_ref When the first duration t is reached, the conduction time TON of the secondary switch 20 is extended; when the first duration t is reached... D Greater than the first time threshold t D_ref When this happens, the on-time TON of the secondary switch 20 is shortened.

[0040] exist Figure 2 In the illustrated embodiment, the control method 200 further includes steps 205-208.

[0041] In step 205, when the secondary turn-off of the secondary switch 20 is detected, a primary turn-on enable signal PRON is provided to the input of the isolation circuit. In step 206, a synchronization signal SYNC, electrically isolated from the primary turn-on enable signal PRON, is coupled to the output of the isolation circuit. In step 207, it is detected whether the voltage across the primary switch 10 has crossed zero, i.e., whether the voltage across the primary switch 10 is less than the zero-crossing threshold, and a zero-crossing voltage detection signal is generated. In step 208, when the zero-crossing voltage across the primary switch 10 is detected, the primary switch 10 delays for a period of time t. Delay It was then switched on.

[0042] The following is based on Figure 3 This will explain the working principle of the present invention to achieve completely zero voltage conduction.

[0043] Figure 3 This is a schematic diagram illustrating the principle of conduction duration control according to an embodiment of the present invention. Figure 3 As shown in curve 1, after the secondary switch 20 completes its first conduction, it does not conduct a second time; that is, the conduction time TON is 0. After the secondary switch 20 completes its first conduction, the voltage V across the secondary switch is... Sec_SR The oscillation period of the sinusoidal oscillation centered on the output voltage Vo of the switching converter is Ts.

[0044] As the curve rises sequentially from curve 1 to curve 5, the conduction time TON of the secondary switch 20 gradually increases. When the primary switch 10 is turned on, the voltage V across the secondary switch gradually increases. Sec_SR This is then gradually increased. When the primary switch 10 achieves complete zero-voltage conduction, the voltage V across the secondary switch is... Sec_SR It is raised to curve 5. Therefore, the voltage V across the secondary switch is... Sec_SR Following curve 5 from the second voltage signal k*V SRD Rise to the first voltage signal V SRD The duration is set to the first time threshold t. D_ref .according to Figure 3 In the embodiment shown, the first time threshold t D_ref Set as:

[0045]

[0046] Where k is the ratio of the second voltage signal to the first voltage signal. In one embodiment, k = 0.75.

[0047] Continue as Figure 3 As shown in curve 3, when the primary switch 10 is turned on, its negative current is insufficient to reduce the voltage V across the secondary switch. Sec_SR Pull up to k*V SRD In this case, the voltage V across the secondary switch 20 is... Sec_SR From the second voltage signal k*V SRD Rise to the first voltage signal V SRD The duration is timed as 0, i.e., the first duration t. D It is 0. Clearly, the first time threshold t... D_ref Greater than the first duration t D Response to the first time threshold t D_ref With the first duration t D The first time difference (at this point, t) D_ref The secondary switch 20 is turned on for the second time, and the on-time TON is increased to further raise the voltage V across the secondary switch in the next switching cycle. Sec_SR , so that its first duration t D Approaching the first time threshold t D_ref .like Figure 3 As shown in curve 4, the voltage V across the secondary switch is... Sec_SR When the primary switch 10 is turned on, it continues to be raised, so that the first time duration t D Approaching the first time threshold t D_Ref Until the voltage V across the secondary switch transistor... Sec_SR Following curve 5, the first duration t DEqual to the first time threshold t D_Ref Only then can complete zero-voltage conduction be achieved.

[0048] It is evident that, to achieve complete zero-voltage conduction of the primary switch 10, the conduction time TON of the secondary switch 20 during its second conduction can be increased. A longer conduction time TON can result in a higher amplitude negative current, and a lower voltage V across the primary switch 10 will be generated when the primary switch 10 is turned on. Pri_DS .

[0049] However, if the conduction time TON of the secondary switch 20 is too long during the second conduction, it will cause the first conduction time t to be too long. D Exceeding the first time threshold t D_Ref This results in unnecessary energy waste. In this situation, in response to the first duration t D Compared with the first time threshold t D_ref The second time difference will cause the conduction duration control circuit 305 to shorten the conduction duration TON of the secondary switch 20, so that the first duration t of the next switching cycle will be shortened. D Decrease and approach the first time threshold t D_ref This provides the minimum energy required to enable the primary switch 10 to achieve zero-voltage turn-on. Therefore, the zero-voltage turn-on technology of the present invention can save the conduction losses of the primary switch 10.

[0050] Taking k = 0.75 as an example, the voltage V across the secondary switch is... Sec_SR Follow curve 5 from 0.75*V SRD Rise to V SRD The duration is set to t D_Ref This value is determined by the external reference resistor R. TD Settings. Theoretically, regardless of the first voltage signal V SRD What is the output voltage Vo? For complete zero-voltage conduction, what is the first time threshold t? D_Ref It is a fixed value. Therefore, by setting an appropriate resistor R... TD This allows for complete zero-voltage conduction under different input and output voltages. Therefore, by employing embodiments of the present invention, the isolated switching converter 100 can meet the high power density, high switching frequency, high efficiency, and electromagnetic interference standards required for USB PD applications, while maintaining the overall low cost of the isolated switching converter.

[0051] Figure 4 This is a circuit schematic diagram of a controller 30A for an isolated switching converter according to an embodiment of the present invention. Figure 4 The controller 30A shown is Figure 1 The controller 30 shown is basically similar, the difference being that... Figure 3The controller 30A shown further includes a primary turn-off detection circuit 311, a current zero-crossing detection circuit 312, a quasi-resonant control circuit 313, and a current comparison circuit 314 located on the secondary side.

[0052] exist Figure 4 In the illustrated embodiment, the primary turn-off detection circuit 311 detects whether the primary switch 10 is turned off and generates a primary turn-off detection signal PROFF. The primary turn-off detection circuit 311 can determine whether the primary switch 10 is turned off based on electrical parameters such as the voltage across the secondary switch 20, the current flowing through the secondary switch 20, and the voltage across the secondary winding. The primary turn-off detection circuit 311 can also obtain a signal indicating whether the primary switch 10 is turned off from the primary side through other means.

[0053] The current zero-crossing detection circuit 312 detects whether the current flowing through the secondary switch 20 crosses zero and generates a zero-crossing detection signal ZCD1. The quasi-resonant control circuit 313 is coupled to the secondary switch 20 to detect the resonant voltage of the switching converter and generates a second turn-on enable signal ZON at the target trough of the resonant voltage. Those skilled in the art will understand that this invention can be applied to any isolated switching converter operating under discontinuous current mode. Figure 4 The quasi-resonant control given is merely exemplary; isolated flyback converters with discontinuous current mode controlled by other methods also satisfy the spirit and scope of this invention.

[0054] As mentioned above, the conduction duration control circuit 305 adjusts the conduction duration TON of the secondary switch transistor during its second conduction, and generates the conduction duration control signal ZOFF when the conduction duration of the secondary switch transistor 20 reaches TON.

[0055] The secondary logic circuit 306A has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, and an output terminal. The first input terminal is coupled to the primary turn-off detection circuit 311 to receive the primary turn-off detection signal PROFF. The second input terminal is coupled to the output terminal of the current zero-crossing detection circuit 312 to receive the current zero-crossing detection signal ZCD1. The third input terminal is coupled to the quasi-resonant control circuit 313 to receive the second turn-on enable signal ZON. The fourth input terminal is coupled to the conduction duration control circuit 305A to receive the conduction duration control signal ZOFF. The secondary logic circuit 306A generates a secondary control signal CTRLS based on the primary turn-off detection signal PROFF and the current zero-crossing detection signal ZCD1 to control the first switching of the secondary switch 20. Furthermore, the secondary logic circuit 306A also generates a secondary control signal CTRLS based on the second turn-on enable signal ZON and the conduction duration control signal ZOFF to control the second switching of the secondary switch 20. When the secondary switch 20 is turned off for the second time, the shutdown detection circuit 307 provides the primary turn-on enable signal PRON.

[0056] In addition, the switching converter 100A also includes a current comparison circuit 314. The current comparison circuit 314 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives a primary current sampling signal ISENP representing the current flowing through the primary switch 10, and the second input terminal receives a first threshold voltage VTH1. The current comparison circuit 314 compares the primary current sampling signal ISENP with the first threshold voltage VTH1 and generates a current comparison signal POFF at its output terminal. A primary logic circuit 310 is coupled to the output terminal of the current comparison circuit 314 to receive the current comparison signal POFF and, based on the current comparison signal POFF, the zero-crossing voltage detection signal PON, and the synchronization signal SYNC, generates a primary control signal CTRLP to control the primary switch 10. When the current ISENP flowing through the primary switch 10 reaches the first threshold voltage VTH1, the primary switch 10 is turned off. The first threshold voltage VTH1 can be a constant value or can vary with the synchronization signal SYNC.

[0057] Figure 5 This is a waveform diagram of an isolated switching converter according to an embodiment of the present invention. Figure 5 As shown, during one switching cycle of the switching converter, for example at time t1, the primary control signal CTRLP changes from high to low, and the primary switch 10 is turned off. After the primary switch 10 is turned off, the voltage V across the secondary switch 20... Sec_SR The change from positive voltage to negative voltage causes the secondary control signal CTRLS to change from low level to high level, and the secondary switch 20 is turned on for the first time.

[0058] Subsequently, at time t2, the secondary current ISENS flowing through the secondary switch 20 decreases to zero, the secondary control signal CTRLS changes from high level to low level, and the secondary switch 20 is turned off, thus ending the first conduction of the secondary switch 20.

[0059] Next, when the current flowing through both the primary and secondary sides is zero, the parasitic capacitance between the energy storage element and the switching transistor begins to resonate, generating a resonant voltage. The waveform of this resonant voltage is detected by the quasi-resonant circuit 313 located on the secondary side. At time t3, due to the use of quasi-resonant control, the voltage V across the secondary switching transistor 20 is detected. Sec_SR When the resonant voltage reaches the target trough of the current working cycle (e.g., the third trough), the second turn-on enable signal ZON changes from low to high, and the secondary control signal CTRLS also goes high, turning on the secondary switch 20 for the second time.

[0060] At time t4, when the effective level of the conduction duration control signal ZOFF arrives, the secondary control signal CTRLS changes from high to low, and the secondary switch 20 is turned off for the second time, ending the second conduction of the secondary switch 20. For example... Figure 5 As shown, the conduction time of the secondary switch 20 for the second time is TON1.

[0061] Furthermore, the primary turn-on enable circuit 307 detects the second turn-off of the secondary switch 20 and provides the primary turn-on enable signal PRON. When the rising edge of the primary turn-on enable signal PRON arrives, almost simultaneously, the synchronization signal SYNC output by the isolation circuit 308 also changes from low to high. Subsequently, the voltage zero-crossing detection circuit 309 detects the voltage V on the auxiliary winding. ZCD Zero crossing, primary switch 10 in delay t Delay It was then switched on.

[0062] like Figure 5 As shown, when the primary switch 10 is turned on at point A, the voltage V across the primary switch is... Pri_DS It's still quite large; the voltage V across the secondary switch is... Sec_SR It was quickly pulled up to the second voltage signal k*V SRD The timing circuit 303 starts timing until the voltage V across the secondary switching transistor reaches its maximum value. Sec_SR Increase to the first voltage signal V SRD When the timer stops, the timing circuit 303 stops timing, and the timing duration is the first duration t. D1 .like Figure 5 As shown, the first duration t D1 Very short, much shorter than the first time threshold t D_ref .

[0063] According to an embodiment of the present invention, in order to achieve complete zero-voltage conduction, in the next switching cycle, the conduction duration control circuit 305 is based on a first duration t. D1 The first time threshold t provided by the threshold generation circuit 304 D_ref Increase or extend the conduction time TON of the secondary switch 20 for the second conduction, so that the first time t D2 Gradually approaching the first time threshold t D_ref .

[0064] like Figure 5 As shown, in the next switching cycle, the conduction time TON2 of the secondary switch 20 increases, and when the primary switch 10 is turned on at point B, the voltage V across the primary switch increases. Pri_DS Much lower than the voltage level when it was turned on at point A 。 Then the timing circuit 303 operates to detect the voltage V across the secondary switch transistor. Sec_SR From the second voltage signal k*V SRD Increase to the first voltage signal V SRD The duration of the first duration t D2 From the first duration t D2 Still less than the first time threshold t D_ref The conduction duration control circuit 305 is based on the first time threshold t. D_ref With the first duration t D2 The first time difference increases the conduction time TON3 of the secondary switch 20 for the second conduction. Subsequently, when the primary switch 10 conducts at point C, the voltage V across the primary switch... Pri_DS The voltage level is further reduced, becoming even lower than the voltage level at point B when the circuit is turned on. At point C, the primary switch 10 achieves zero-voltage turn-on. In the next switching cycle, the first duration t... D3 Approaching the first time threshold t D_ref .

[0065] As can be seen, according to an embodiment of the present invention, the conduction duration control circuit 305 is based on a first duration t D Compared with the first time threshold t D_ref By comparing the two, the conduction duration TON of the secondary switch is continuously adjusted so that the first duration t of the next switching cycle is adjusted accordingly. D Approaching the first time threshold t D_ref Finally, after several switching cycles, the primary switch 10 achieves complete zero-voltage conduction.

[0066] Figure 6 This is a circuit schematic diagram of a timing circuit 303A and a threshold generation circuit 304A according to an embodiment of the present invention. Figure 6As shown, the timing circuit 303A includes a first comparator circuit 3031, a second comparator circuit 3032, and a logic circuit 3033. The first comparator circuit 3031 compares the voltage V across the secondary switching transistor. Sec_SR With the first voltage signal V SRD A comparison is performed, generating a first comparison signal CP1 at the output. In one embodiment, when the voltage V across the secondary switch transistor... Sec_SR Increase to the first voltage signal V SRD At that time, the first comparison signal CP1 is at a high level. Figure 6 In the illustrated embodiment, the first comparison circuit 3031 includes a comparator CMP1. The inverting input of the comparator CMP1 is coupled to the output of the maximum value detection circuit 301 to receive the first voltage signal V. SRD The non-inverting input is coupled to the SRD pin of the controller 30A to receive the voltage V across the secondary switch. Sec_SR The output terminal provides the first comparison signal CP1.

[0067] The second comparator circuit 3032 compares the voltage V across the secondary switch transistor. Sec_SR With the second voltage signal k*V SRD A comparison is performed, generating a second comparison signal CP2 at the output. In one embodiment, when the voltage V across the secondary switch transistor... Sec_SR Increase to the second voltage signal k*V SRD At that time, the second comparison signal CP2 is at a high level. Figure 5 In the illustrated embodiment, the second comparison circuit 3032 includes a comparator CMP2. The inverting input of the comparator CMP2 is coupled to the output of the voltage divider circuit 302 to receive the second voltage signal k*V. SRD The non-inverting input is coupled to the SRD pin of the controller 30A to receive the voltage V across the secondary switch. Sec_SR The output provides a second comparison signal CP2.

[0068] Logic circuit 3033 generates a first control signal T based on the first comparison signal CP1 and the second comparison signal CP2. D In one embodiment, the first control signal T D The high-level width is the first duration t D .exist Figure 6 In the illustrated embodiment, the logic circuit 3033 includes an RS flip-flop FF1. The RS flip-flop FF1 has a set terminal, a reset terminal, and an output terminal, wherein the set terminal receives a second comparison signal CP2, the reset terminal receives a first comparison signal CP1, and the output terminal generates a first control signal T. D The effective duration of the first control signal is the first duration t. D .

[0069] The threshold generation circuit 304A is used to provide an effective duration of the first time threshold t. D_ref The second control signal T DREF .exist Figure 6 In the illustrated embodiment, the threshold generation circuit 304A includes a current mirror circuit 3041, a reference capacitor Cs, a switch control unit 3042, and a third comparison circuit 3043. The current mirror circuit 3041 has a current setting terminal and a current output terminal, wherein the current setting terminal is coupled to the reference resistor R via the ZVS terminal of the controller 30A. TD The control current Is is set. The reference capacitor Cs has a first terminal and a second terminal, wherein the first terminal is coupled to the current output terminal of the current mirror circuit 3041, and the second terminal is coupled to the secondary reference ground.

[0070] The switch control unit 3042 is coupled to the output of the second comparison circuit 3032 to receive the second comparison signal CP2. In response to the second comparison signal CP2, it charges the reference capacitor Cs, and the charging current is the control current Is. Figure 6 As shown, the switch control unit 3042 includes an RS flip-flop FF2, switching transistors Q1 and Q2. The RS flip-flop FF2 has a set terminal, a reset terminal, and an output terminal. The set terminal is coupled to the output terminal of the second comparator circuit 3032 to receive the second comparator signal CP2, and the reset terminal is coupled to receive the second control signal T. DREF The output terminal controls the control terminal of the normally closed switch Q1. The normally closed switch Q1 is coupled between the power supply VP and the first terminal of the reference capacitor Cs. The normally open switch Q2 is connected in parallel with the reference capacitor Cs, and its control terminal is coupled to receive the second control signal T. DREF .

[0071] The third comparator circuit 3043 compares the voltage VCs across the reference capacitor Cs with the reference voltage Vref, and generates a second control signal T based on the comparison result. DREF .exist Figure 6 In the illustrated embodiment, the third comparison circuit includes a comparator CMP3. The inverting input of comparator CMP3 is coupled to the first terminal of the reference capacitor Cs to receive the voltage VCs across the reference capacitor, the non-inverting input receives the reference voltage Vref, and the output provides a second control signal T. DREF .

[0072] In one embodiment, the threshold generation circuit 304A further includes a single trigger circuit 3044 coupled between the output of the third comparator circuit 3043 and the control terminal of the normally open switch Q2, for resetting the voltage across the reference capacitor Cs when the voltage VCs across the reference capacitor reaches the reference voltage Vref.

[0073] Continue as Figure 6 As shown, the conduction duration control circuit 305 receives the first control signal T. D The first end and receiving the second control signal T DREF The second end, based on the first control signal T D Second control signal T DREF The output provides a conduction duration control signal ZOFF to control the conduction duration TON of the secondary switch 20 during its second conduction.

[0074] Figure 7 This is a circuit diagram of a conduction duration control circuit 305A according to an embodiment of the present invention. Figure 7 In the embodiment shown, the conduction duration control circuit 305A includes a duration comparison circuit 3051, a charging control unit 3052, a discharging control unit 3053, a first capacitor C1, a second capacitor C2, and a fourth comparison circuit 3054.

[0075] The duration comparison circuit 3051 has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal is coupled to the output terminal of the timing circuit 303A to receive the first control signal T. D The second input terminal is coupled to the output terminal of the threshold generation circuit 304A to receive the second control signal T. DREF The duration comparison circuit 3051 is based on the first control signal T. D Second control signal T DREF A first enable signal T1 is provided at the first output terminal, and a second enable signal T2 is provided at the second output terminal. The first enable signal T1 represents a first time threshold t. D_ref With the first duration t D The first time difference. The second enable signal T1 represents the first time duration t. D Compared with the first time threshold t D_ref The second time difference.

[0076] exist Figure 7 In the illustrated embodiment, the duration comparison circuit 3051 includes a first AND gate circuit AND1 and a second AND gate single-channel AND2. The first AND gate circuit AND1 has a first input terminal, a second inverting input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the timing circuit 303A to receive the second control signal T. DREF The second inverting input receives the first control signal T. D At the output terminal, a value representing the first duration t is generated. D Less than the first time threshold t D_refThe first enable signal T1. The second AND gate circuit AND2 has a first input terminal, a second inverting input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the timing circuit 303A to receive the first control signal T. D The second inverting input receives the second control signal T. DREF At the output terminal, a value representing the first duration t is generated. D Greater than the first time threshold t D_ref The second enable signal T2.

[0077] The charging control unit 3052 receives a first enable signal T1 and, based on the first enable signal T1, controls the first charging current source I1 to charge the first capacitor C1. For example... Figure 7 As shown, the charging control unit 3052 is coupled between the output terminal of the first charging current source I1 and the first terminal of the first capacitor C1. The power supply terminal of the first charging current source I1 is coupled to the power supply, and the second terminal of the first capacitor C1 is grounded. The charging time of the first charging current source I1 on the capacitor C1 is determined by a first time difference. Figure 7 In the illustrated embodiment, the charging control unit 3052 includes a switching transistor S1 coupled between the output terminal of the first charging current source I1 and the first terminal of the first capacitor C1. In other embodiments, the first charging current source I1 has an enable control terminal that charges the first capacitor C1 only when the first enable signal T1 is valid.

[0078] The discharge control unit 3053 receives a second enable signal T2 and controls the first discharge current source I2 to discharge the first capacitor C1 based on the second enable signal T2. Figure 7 As shown, the discharge control unit 3053 is coupled between the first terminal of the first capacitor C1 and the input terminal of the discharge current source I2, and the output terminal of the first discharge current source I2 is grounded. The discharge duration of the first discharge current source I2 on the capacitor C1 is determined by the second time difference. Figure 7 In the illustrated embodiment, the discharge control unit 3053 includes a switch S2 coupled between the input terminal of the first discharge current source I2 and the first terminal of the first capacitor C1. In other embodiments, the first discharge current source I2 has an enable control terminal that discharges the first capacitor C1 only when the second enable signal T2 is valid.

[0079] The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal is coupled to the output terminal of the first charging current source I1 via a switch S3, and the second terminal is connected to the secondary reference ground. The switch S3 is controlled by a second turn-on enable signal ZON. When the secondary switch 20 is turned on for the second time, the first charging current source I1 begins to charge the second capacitor C2, and the voltage VC2 across the second capacitor begins to increase. The fourth comparator circuit 3054 compares the voltage VC1 across the first capacitor with the voltage VC2 across the second capacitor, generating a conduction duration control signal ZOFF. In one embodiment, when the voltage VC2 across the second capacitor increases to the voltage VC1 across the first capacitor, the conduction duration control signal ZOFF flips to a high level, and the secondary switch 20 is turned off. Figure 7 In the illustrated embodiment, the fourth comparator circuit 3054 includes a comparator CMP4. The non-inverting input of the comparator CMP4 is coupled to the first terminal of the second capacitor C2 to receive the voltage VC2 across the second capacitor, and the inverting input is coupled to the second terminal of the first capacitor C1 to receive the voltage VC1 across the first capacitor. Its output provides an on-time control signal ZOFF.

[0080] exist Figure 7 In the illustrated embodiment, when the secondary switch 20 begins to conduct for the second time, i.e., when the second turn-on enable signal ZON changes from low to high, the voltage VC2 across the second capacitor C2 increases from zero. Until the voltage across the second capacitor C2 reaches the voltage VC1 across the first capacitor, the output of the fourth comparator circuit 3054 flips, and its output conduction duration control signal ZOFF changes from low to high, turning off the secondary switch 20 for the second time. Subsequently, the voltage VC2 across the second capacitor C2 is reset to zero by the output of the single trigger circuit 3055.

[0081] Figure 8 This is a flowchart of a method 204 for generating a conduction duration control signal according to an embodiment of the present invention. Figure 8 In the illustrated embodiment, the method 204 for generating the conduction duration control signal further includes steps 2041 to 2045.

[0082] In step 2041, if the first duration is less than a first time threshold, in response to the first time difference between the first time threshold and the first duration, the first capacitor is charged using a first charging current source. The charging duration of the first capacitor is determined by the first time difference.

[0083] In step 2042, if the first duration is greater than a first time threshold, and in response to a second time difference between the first duration and the first time threshold, the first capacitor is discharged using a first discharge current source. The discharge duration of the first capacitor is determined by the second time difference.

[0084] In step 2043, in response to the second turn-on of the secondary switch, the second capacitor is charged using the first charging current source, so that the voltage across the second capacitor increases from zero.

[0085] In step 2044, the voltage across the first capacitor is compared with the voltage across the second capacitor.

[0086] In step 2045, when the voltage across the second capacitor increases to the voltage across the first capacitor, a conduction duration control signal is generated to turn off the secondary switch.

[0087] In a further embodiment, method 204 further includes step 2046. In step 2046, the voltage across the second capacitor is reset to zero.

[0088] In the specification, terms such as "first" and "second" may be used merely to distinguish one entity or action from another, and do not necessarily imply any relationship or order between these entities or actions. Numerical orders such as "first," "second," and "third" refer only to different individuals among a plurality and do not imply any order or sequence, unless specifically defined in the language of the claims. The order of the text in any claim does not imply that the processing steps must be performed in a provisional or logical order according to such order, unless specifically specified in the language of the claims. Without departing from the scope of the invention, these processing steps may be interchanged in any order, provided that such interchange does not contradict the language of the claims and does not result in logical absurdity.

[0089] The above description and embodiments are merely exemplary and are not intended to limit the scope of the invention. Variations and modifications to the disclosed embodiments are possible, and other feasible alternative embodiments and equivalent variations of elements in the embodiments can be understood by those skilled in the art. Other variations and modifications to the embodiments disclosed in this invention do not depart from the spirit and scope of protection of this invention.

Claims

1. A controller for an isolated switching converter, the switching converter including a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, and a secondary switch coupled to the secondary winding, the controller comprising: The maximum value detection circuit is coupled to the secondary switch to detect the voltage across the secondary switch and provide a first voltage signal representing the maximum value of the voltage across the secondary switch. The voltage divider circuit receives a first voltage signal and provides a second voltage signal that is lower than the first voltage signal. The timing circuit starts timing when the voltage across the secondary switch reaches the second voltage signal and ends timing when the voltage across the secondary switch increases to the first voltage signal. The timing time of the timing circuit is the first duration. as well as The conduction duration control circuit compares the first duration of the current cycle with the first time threshold. Based on the comparison result, it provides a conduction duration control signal to adjust the conduction duration of the second conduction of the secondary switch, so that the first duration of the next switching cycle is close to the first time threshold. The first time threshold is set based on the oscillation period of the voltage across the secondary switch after the first conduction of the secondary switch, which is a sinusoidal oscillation centered on the output voltage of the isolated switching converter.

2. The controller of claim 1, further comprising: When the secondary switch is turned off again, the detection circuit provides a primary turn-on enable signal. An isolation circuit has an input terminal that receives a primary turn-on enable signal and an output terminal that generates a synchronization signal that is electrically isolated from the primary turn-on enable signal. The voltage zero-crossing detection circuit detects whether the voltage across the primary switching transistor crosses zero and generates a voltage zero-crossing detection signal. The primary logic circuit is coupled to the output of the isolation circuit to receive the synchronization signal and coupled to the voltage zero-crossing detection circuit to receive the voltage zero-crossing detection signal. The primary control signal is generated based on the synchronization signal and the voltage zero-crossing detection signal.

3. The controller of claim 1, wherein the first time threshold t D_ref Set as: Where Ts is the oscillation period, and k is the ratio of the second voltage signal to the first voltage signal.

4. The controller of claim 3, wherein k is 0.

75.

5. The controller of claim 1, wherein the timing circuit comprises: The first comparator circuit compares the voltage across the secondary switch with a first voltage signal and generates a first comparison signal at the output. The second comparator circuit compares the second voltage signal with the voltage across the secondary switch and generates a second comparison signal at the output. as well as The logic circuit has a set terminal, a reset terminal and an output terminal, wherein the set terminal receives a second comparison signal, the reset terminal receives a first comparison signal, and the output terminal generates a first control signal, the effective duration of which is a first duration.

6. The controller of claim 5, further comprising a threshold generation circuit, providing a second control signal with an effective duration of a first time threshold, the threshold generation circuit comprising: A current mirror circuit has a current setting terminal and a current output terminal, wherein the current setting terminal is coupled to a reference resistor to set the control current; The reference capacitor has a first terminal coupled to the current output terminal of the current mirror circuit and a second terminal coupled to the reference ground; A switch control unit, in response to a second comparison signal, charges a reference capacitor with the control current; as well as The third comparator circuit compares the voltage across the reference capacitor with the reference voltage to generate a second control signal.

7. The controller of claim 1, wherein the on-time control circuit comprises: The charging control unit, in response to a first time difference between a first time threshold and a first duration, couples a first charging current source to a first capacitor to charge the first capacitor. The discharge control unit, in response to a second time difference between a first duration and a first time threshold, couples the first capacitor to a first discharge current source to discharge the first capacitor; In response to the second turn-on of the secondary switch, the first charging current source is coupled to the second capacitor to charge the second capacitor; as well as The fourth comparator circuit compares the voltage across the first capacitor with the voltage across the second capacitor to generate a conduction duration control signal.

8. The controller of claim 1, wherein at least one of the primary switch and the secondary switch comprises a gallium nitride device or a silicon carbide device.

9. An isolated switching converter, comprising a controller as claimed in any one of claims 1 to 8.

10. A control method for an isolated switching converter, the switching converter comprising a transformer having a primary winding and a secondary winding, a primary switching transistor coupled to the primary winding, and a secondary switching transistor coupled to the secondary winding, the control method comprising: The maximum value of the voltage across the secondary switch is sampled and held to provide the first voltage signal; Based on the first voltage signal, a second voltage signal smaller than the first voltage signal is provided; The timing starts when the voltage across the secondary switch reaches the second voltage signal and ends when the voltage across the secondary switch increases to the first voltage signal. The timing duration is the first duration. as well as The first duration is compared with the first time threshold. Based on the comparison result, the conduction duration of the second conduction of the secondary switch is adjusted so that the first duration of the next switching cycle is close to the first time threshold. The first time threshold is set based on the oscillation period of the voltage across the secondary switch after the first conduction of the secondary switch, which is a sinusoidal oscillation centered on the output voltage of the isolated switching converter.

11. The control method of claim 10, wherein the first time threshold is set as follows: Where Ts is the oscillation period, and k is the ratio of the second voltage signal to the first voltage signal.

12. The control method of claim 11, wherein the ratio k is 0.

75.

13. The control method of claim 11, wherein the method for setting the first time threshold includes: Adjust the reference resistor to set the control current; as well as Timing begins when the voltage across the secondary switch reaches the second voltage signal. The reference capacitor is charged with a control current. Timing ends when the voltage across the reference capacitor increases from zero to the reference voltage. The timing time is the first time threshold.

14. The control method of claim 10, wherein the method for adjusting the conduction duration of the second conduction of the secondary switch comprises: In response to the first duration being less than the first time threshold, the conduction duration of the secondary switch being turned on for the second time is extended; as well as In response to the first time duration being greater than the first time threshold, the conduction time of the secondary switch being turned on for the second time is shortened.

15. The control method as described in claim 14, wherein: In response to a first time difference between a first time threshold and a first duration, a first charging current source is coupled to a first capacitor to charge the first capacitor. In response to a second time difference between a first duration and a first time threshold, a first discharge current source is coupled to a first capacitor to discharge the first capacitor. In response to the second turn-on of the secondary switch, the first charging current source is coupled to the second capacitor to charge the second capacitor; as well as When the voltage across the second capacitor reaches the voltage across the first capacitor, the secondary switch is turned off.

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