A broadband input buffer for high-speed and high-precision analog-to-digital converters

Abstract

The present invention relates to a broadband input buffer for use in a high-speed, high-precision analog-to-digital converter. The broadband input buffer comprises: a P-transistor source follower module, a first capacitor-resistor network module, an N-transistor source follower module, a second capacitor-resistor network module, a current source module, and a current mirror module. Based on a two-stage buffer circuit structure comprising a P-transistor source follower module and an N-transistor source follower module, the present invention employs technologies such as a current mirror module, a compensation capacitor, and a capacitor-resistor network module to improve linearity. Furthermore, by introducing an operational amplifier to obtain a constant bias current, nonlinearity is suppressed, resulting in a buffer with high bandwidth, large swing, and high linearity. This significantly reduces the impact of distortion on the input signal from sampling switches and package inductance, ensuring the accuracy of the subsequent analog-to-digital converter.

Description

Technical Field

[0001] The invention belongs to the technical field of buffers and relates to a broadband input buffer applied to a high-speed and high-precision analog-to-digital converter. Background Art

[0002] Analog-to-digital converters (ADCs) are widely used in information acquisition and processing systems to convert analog signals. As input frequencies increase to GHz, input sampling becomes increasingly challenging. However, any distortion caused by the sampling network at the digital output is difficult to eliminate. Input buffers, with their low output impedance and high input impedance, are often used to isolate the input signal from downstream ADC modules, providing a strong signal driver.

[0003] As a crucial module for isolating the input signal from the sampling circuit, the input buffer is an essential building block in high-speed, high-precision analog-to-digital converters. It has long been a research hotspot in analog circuit design. Various optimization designs, such as compensation capacitors, substrate coupling, and op amp assist, have been proposed to improve input buffer linearity. Even in the face of the boom in deep N-well transistors, the idea of ​​reducing parasitic capacitance in the input buffer through AC floating N-well technology and negative substrate biasing has been proposed, thereby improving overall linearity. However, with the continuous advancement of microelectronics manufacturing processes, the size of electronic components continues to decrease, and while the power supply voltage decreases proportionally, the threshold voltage of transistors cannot decrease linearly with it.

[0004] Therefore, it is particularly necessary to design an input buffer for high-speed and high-precision analog-to-digital converters. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a broadband input buffer for a high-speed and high-precision analog-to-digital converter. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] An embodiment of the present invention provides a broadband input buffer for a high-speed and high-precision analog-to-digital converter, the broadband input buffer comprising:

[0007] The P-tube source follower module is used to buffer the input signal to obtain a first-level buffer signal;

[0008] a first capacitor-resistor network module, connected to the P-tube source follower module, and configured to generate a control voltage according to the input signal, so as to enable the drain voltage of the P-tube source follower module to follow the input signal;

[0009] An N-tube source follower module, connected to the P-tube source follower module, configured to perform buffering processing on the first-stage buffer signal to obtain a second-stage buffer signal and output the second-stage buffer signal;

[0010] a second capacitor-resistor network module, connected to the N-transistor source follower module, and configured to generate a control voltage according to the first-stage buffer signal, so as to enable the drain voltage of the N-transistor source follower module to follow the first-stage buffer signal;

[0011] a current source module connected to the P-tube source follower module and the N-tube source follower module, and configured to provide a constant current bias to the N-tube source follower module, wherein the current source module maintains a constant drain voltage of the N-tube source follower module through an operational amplifier amp, and the current source module absorbs current changes caused by the sampling capacitor through a compensation capacitor;

[0012] The current mirror module is connected to the P-tube source follower module and the N-tube source follower module, and is used to transmit the constant current of the N-tube source follower module to the P-tube source follower module, so that the P-tube source follower module has a constant current.

[0013] In one embodiment of the present invention, the P-type transistor source follower module includes a transistor M1 and a transistor M3, wherein:

[0014] The gate of the transistor M1 is connected to the signal input end and the first capacitor-resistor network module, the source of the transistor M1 is connected to the current mirror module, the drain of the transistor M1 is connected to the source of the transistor M3, the gate of the transistor M3 is connected to the first capacitor-resistor network module, and the drain of the transistor M3 is grounded.

[0015] In one embodiment of the present invention, the transistor M1 and the transistor M3 are both PMOS transistors.

[0016] In one embodiment of the present invention, the first capacitor-resistor network module includes a resistor R1 and a capacitor C1, wherein:

[0017] The first end of the resistor R1 is connected to the bias voltage input terminal V b4 The second end of the resistor R1 is connected to the gate of the transistor M3 and the first end of the capacitor C1, and the second end of the capacitor C1 is connected to the gate of the transistor M1.

[0018] In one embodiment of the present invention, the N-transistor source follower module includes a transistor M2 and a transistor M4, wherein:

[0019] The gate of the transistor M2 is connected to the source of the transistor M1, the source of the transistor M2 is connected to the current source module, the drain of the transistor M2 is connected to the source of the transistor M4, the gate of the transistor M4 is connected to the second capacitor-resistor network module, and the drain of the transistor M4 is connected to the current mirror module.

[0020] In one embodiment of the present invention, the transistor M2 and the transistor M4 are both NMOS transistors.

[0021] In one embodiment of the present invention, the second capacitor-resistor network module includes a resistor R2 and a capacitor C2, wherein:

[0022] The first end of the resistor R2 is connected to the bias voltage input terminal V b5 The second end of the resistor R2 is connected to the gate of the transistor M4 and the first end of the capacitor C2, and the second end of the capacitor C2 is connected to the gate of the transistor M2.

[0023] In one embodiment of the present invention, the current source module includes a capacitor Cc, an operational amplifier amp, a transistor M8, and a transistor M9, wherein:

[0024] The first end of the capacitor Cc is connected to the source of the transistor M1 and the gate of the transistor M2, the second end of the capacitor Cc is connected to the negative input terminal of the operational amplifier amp, and the positive input terminal of the operational amplifier amp is connected to the bias voltage input terminal V b1 The drain of the transistor M8 is connected to the source of the transistor M2, the source of the transistor M8 is connected to the second end of the capacitor Cc, the negative input terminal of the operational amplifier amp, and the drain of the transistor M9, the gate of the transistor M8 is connected to the output terminal of the operational amplifier amp, and the gate of the transistor M9 is connected to the bias voltage input terminal V b2 The source of the transistor M9 is grounded.

[0025] In one embodiment of the present invention, the current mirror module includes a transistor M5, a transistor M6, and a transistor M7, wherein:

[0026] The drain of the transistor M5 is connected to the source of the transistor M1, the first end of the capacitor Cc, the second end of the capacitor C2, and the gate of the transistor M1. The source of the transistor M5 is connected to the drain of the transistor M6. The gate of the transistor M5 is connected to the bias voltage input terminal V b3 The gate of the transistor M6 is connected to the gate of the transistor M7, the drain of the transistor M7, and the drain of the transistor M4. The source of the transistor M6 is connected to the power supply voltage terminal, and the source of the transistor M7 is connected to the power supply voltage terminal.

[0027] In one embodiment of the present invention, the transistor M5 , the transistor M6 , and the transistor M7 are all PMOS transistors, and the transistor M8 and the transistor M9 are all NMOS transistors.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The present invention is based on a two-stage buffer circuit structure of a P-tube source follower module and an N-tube source follower module, and adopts technologies such as a current mirror module, a compensation capacitor, and a capacitor-resistor network module to improve linearity. By introducing an operational amplifier, a constant bias current is obtained, and nonlinearity is suppressed. The buffer has the characteristics of high bandwidth, large swing, and high linearity, which greatly alleviates the influence of distortion on the sampling switch and the package inductor on the input signal, and ensures the accuracy of the subsequent analog-to-digital converter.

[0030] Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It should be understood, however, that the drawings are designed for illustrative purposes only and are not intended to limit the scope of the present invention, as reference should be made to the appended claims. It should also be understood that, unless otherwise indicated, the drawings are not necessarily drawn to scale and are intended merely to conceptually illustrate the structures and processes described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 1 is a schematic structural diagram of a broadband input buffer applied to a high-speed and high-precision analog-to-digital converter provided by an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of a specific circuit structure of a broadband input buffer applied to a high-speed and high-precision analog-to-digital converter provided by an embodiment of the present invention;

[0033] Figure 3 This is a structural diagram of an analog-to-digital converter provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0035] Example 1

[0036] See Figure 1 , Figure 1 1 is a schematic structural diagram of a broadband input buffer for a high-speed, high-precision analog-to-digital converter provided by an embodiment of the present invention. The present invention provides a broadband input buffer for a high-speed, high-precision analog-to-digital converter, the broadband input buffer comprising:

[0037] The P-tube source follower module is used to buffer the input signal to obtain a first-level buffer signal;

[0038] The first capacitor-resistor network module is connected to the P-tube source follower module and is used to generate a control voltage according to the input signal to enable the drain voltage of the P-tube source follower module to follow the input signal;

[0039] The N-tube source follower module is connected to the P-tube source follower module and is used to buffer the first-stage buffer signal to obtain a second-stage buffer signal and output the second-stage buffer signal;

[0040] a second capacitor-resistor network module, connected to the N-tube source follower module, for generating a control voltage according to the first-stage buffer signal, so as to enable the drain voltage of the N-tube source follower module to follow the first-stage buffer signal;

[0041] The current source module is connected to the P-tube source follower module and the N-tube source follower module to provide a constant current bias to the N-tube source follower module. The current source module uses the operational amplifier amp to keep the drain voltage of the N-tube source follower module constant. The current source module absorbs the current change caused by the sampling capacitor through the compensation capacitor.

[0042] The current mirror module is connected to the P-tube source follower module and the N-tube source follower module, and is used to transmit the constant current of the N-tube source follower module to the P-tube source follower module, so that the P-tube source follower module has a constant current.

[0043] Specifically, the P-tube source follower module and the N-tube source follower module are divided into two stages to buffer the input signal to obtain a buffered signal (i.e., a second-stage buffered signal) output by the N-tube source follower module. The two-stage structure alleviates the distortion caused by the sampling switch and the package inductance; the first capacitor-resistor network module and the second capacitor-resistor network module are used to generate a control voltage according to the input signal to achieve the source end and drain end voltage of the MOS tube following the input voltage (i.e., the input signal); the current source module is used to provide a constant current bias to the second-stage N-tube source follower module, wherein an operational amplifier amp is introduced to keep the drain end voltage of the MOS tube basically constant and suppress the influence of the channel length modulation effect; the compensation capacitor is introduced to absorb the current change caused by the sampling capacitor, while avoiding the limitation of the input bandwidth when the compensation capacitor is introduced into the first-stage P-tube source follower module; the current mirror module is used to transfer the constant current of the second-stage N-tube source follower module to the first-stage P-tube source follower module.

[0044] In a specific embodiment, see Figure 2 The P-tube source follower module includes a transistor M1 and a transistor M3, wherein:

[0045] The gate of transistor M1 is connected to the signal input end and the first capacitor-resistor network module, the source of transistor M1 is connected to the current mirror module, the drain of transistor M1 is connected to the source of transistor M3, the gate of transistor M3 is connected to the first capacitor-resistor network module, and the drain of transistor M3 is grounded.

[0046] Preferably, the transistor M1 and the transistor M3 are both PMOS transistors.

[0047] In a specific embodiment, see Figure 2 The first capacitor-resistor network module includes a resistor R1 and a capacitor C1, wherein:

[0048] The first end of the resistor R1 is connected to the bias voltage input terminal V b4 The second end of the resistor R1 is connected to the gate of the transistor M3 and the first end of the capacitor C1, and the second end of the capacitor C1 is connected to the gate of the transistor M1.

[0049] In this embodiment, the input signal is coupled to the gate of the cascade transistor M3 through the bootstrap capacitor C1. The voltage of the source of the transistor M3 (i.e., the drain of the transistor M1) follows the input signal through the following effect of the source of the transistor M3, so that the source and drain voltages of the transistor M1 are constant, thereby suppressing the channel length modulation effect and improving the linearity.

[0050] In a specific embodiment, see Figure 2 The N-tube source follower module includes a transistor M2 and a transistor M4, wherein:

[0051] The gate of transistor M2 is connected to the source of transistor M1, the source of transistor M2 is connected to the current source module, the drain of transistor M2 is connected to the source of transistor M4, the gate of transistor M4 is connected to the second capacitor resistor network module, and the drain of transistor M4 is connected to the current mirror module.

[0052] Preferably, the transistor M2 and the transistor M4 are both NMOS transistors.

[0053] In a specific embodiment, see Figure 2 The second capacitor-resistor network module includes a resistor R2 and a capacitor C2, wherein:

[0054] The first end of the resistor R2 is connected to the bias voltage input terminal V b5 The second end of the resistor R2 is connected to the gate of the transistor M4 and the first end of the capacitor C2, and the second end of the capacitor C2 is connected to the gate of the transistor M2.

[0055] Specifically, the output signal of the first-stage P-transistor source follower module is coupled to the gate of cascade transistor M4 via bootstrap capacitor C2, causing the voltage at the source of transistor M4 (i.e., the drain of transistor M2) to track the input signal, improving linearity. Simultaneously, the Vgs of transistor M2 (Vgs is the voltage difference between the gate and source) compensates for the Vgs of transistor M1 in the first-stage P-transistor source follower module, eliminating voltage offsets. The N-transistor source follower module and the P-transistor source follower module form a two-stage buffer structure, significantly reducing the impact of distortion generated by the sampling capacitor and package inductance on the input signal.

[0056] The first capacitor-resistor network module and the second capacitor-resistor network module achieve voltage following through bootstrap capacitors, and filter out clutter on the gates of transistors M1 and M2 through a filter network composed of pF-level large capacitors and GΩ-level large resistors.

[0057] In a specific embodiment, see Figure 2 The current source module includes a capacitor Cc, an operational amplifier amp, a transistor M8, and a transistor M9, wherein:

[0058] The first end of the capacitor Cc is connected to the source of the transistor M1 and the gate of the transistor M2, the second end of the capacitor Cc is connected to the negative input terminal of the operational amplifier amp, and the positive input terminal of the operational amplifier amp is connected to the bias voltage input terminal V b1 The drain of transistor M8 is connected to the source of transistor M2, the source of transistor M8 is connected to the second end of capacitor Cc, the negative input terminal of operational amplifier amp, and the drain of transistor M9, the gate of transistor M8 is connected to the output terminal of operational amplifier amp, and the gate of transistor M9 is connected to the bias voltage input terminal V b2 The source of transistor M9 is connected to ground.

[0059] Specifically, transistor M8 and transistor M9 adopt a common source and common gate structure. The common source and common gate transistor M8 improves the output impedance of the load current source module. Due to its large gm (transistor transconductance), the source of transistor M8 (i.e., the drain of transistor M9) can be considered as a virtual ground point. Since the capacitance of the compensation capacitor Cc is the same as that of the sampling capacitor C L Equal, the current i flowing through the compensation capacitor Cc connected between this point and the input signal of the second-stage N-tube source follower module c and the sampling capacitor C L The current i flowing through L Equal, so that the current flowing through transistor M2 is equal to the constant bias current provided by the current source module, and is not affected by the sampling switch The influence of the sampling switch is suppressed, and the nonlinearity of the sampling switch is suppressed. Transistors M8 and M9 both operate in the saturation region. The compensation capacitor Cc couples the output of the P-tube source follower module to the negative input terminal of the operational amplifier amp. Due to the clamping effect of the operational amplifier amp and the isolation effect of the cascode structure, the dependence between the drain voltage of transistor M9 (that is, the source voltage of transistor M8) and the input signal is weakened. Therefore, the current source module can provide a constant bias current, suppressing the nonlinearity caused by the channel length modulation effect of the input transistor.

[0060] In a specific embodiment, see Figure 2 , the current mirror module includes a transistor M5, a transistor M6, and a transistor M7, wherein:

[0061] The drain of transistor M5 is connected to the source of transistor M1, the first end of capacitor Cc, the second end of capacitor C2, and the gate of transistor M1. The source of transistor M5 is connected to the drain of transistor M6. The gate of transistor M5 is connected to the bias voltage input terminal V b3 The gate of the transistor M6 is connected to the gate of the transistor M7, the drain of the transistor M7, and the drain of the transistor M4. The source of the transistor M6 is connected to the power supply voltage terminal, and the source of the transistor M7 is connected to the power supply voltage terminal.

[0062] Specifically, the constant bias current flowing through the second-stage P-transistor source follower module is amplified by the current mirror module and then provides bias to the first-stage N-transistor source follower module. The constant bias current and the common-source common-gate structure composed of transistors M5 and M6 improve linearity.

[0063] Preferably, the transistor M5 , the transistor M6 , and the transistor M7 are all PMOS transistors, and the transistor M8 and the transistor M9 are all NMOS transistors.

[0064] In summary, the present invention is based on a two-stage buffer circuit structure of a P-tube source follower module and an N-tube source follower module, and adopts technologies such as a current mirror module, a compensation capacitor, and a capacitor-resistor network module to improve linearity. By introducing an operational amplifier, a constant bias current is obtained, which suppresses nonlinearity, so that the buffer has the characteristics of high bandwidth, large swing, and high linearity, greatly alleviating the influence of distortion on the sampling switch and the package inductor on the input signal, and ensuring the accuracy of the subsequent analog-to-digital converter.

[0065] In the description of an invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the invention, "plurality" means two or more, unless otherwise specifically defined.

[0066] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features, structures, materials, or characteristic data points described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristic data points described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0067] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A broadband input buffer for a high-speed, high-precision analog-to-digital converter, characterized in that: The broadband input buffer comprises: A P-type transistor source follower module is configured to buffer an input signal to obtain a first-stage buffered signal. The P-type transistor source follower module includes a transistor M1 and a transistor M3, wherein: the gate of the transistor M1 is connected to the signal input terminal and the first capacitor-resistor network module; the source of the transistor M1 is connected to the current mirror module; the drain of the transistor M1 is connected to the source of the transistor M3; the gate of the transistor M3 is connected to the first capacitor-resistor network module; and the drain of the transistor M3 is grounded. The first capacitor-resistor network module is connected to the P-tube source follower module and is used to generate a control voltage according to the input signal to enable the drain voltage of the P-tube source follower module to follow the input signal; the first capacitor-resistor network module includes a resistor R1 and a capacitor C1, wherein: the first end of the resistor R1 is connected to the bias voltage input terminal V b4 , the second end of the resistor R1 is connected to the gate of the transistor M3 and the first end of the capacitor C1, and the second end of the capacitor C1 is connected to the gate of the transistor M1; an N-transistor source follower module, connected to the P-transistor source follower module, configured to perform buffering processing on the first-stage buffer signal to obtain a second-stage buffer signal and output the second-stage buffer signal; the N-transistor source follower module includes a transistor M2 and a transistor M4, wherein: the gate of the transistor M2 is connected to the source of the transistor M1, the source of the transistor M2 is connected to the current source module, the drain of the transistor M2 is connected to the source of the transistor M4, the gate of the transistor M4 is connected to the second capacitor-resistor network module, and the drain of the transistor M4 is connected to the current mirror module; The second capacitor-resistor network module is connected to the N-tube source follower module and is used to generate a control voltage according to the first-stage buffer signal to enable the drain voltage of the N-tube source follower module to follow the first-stage buffer signal; the second capacitor-resistor network module includes a resistor R2 and a capacitor C2, wherein: the first end of the resistor R2 is connected to the bias voltage input terminal V b5 , the second end of the resistor R2 is connected to the gate of the transistor M4 and the first end of the capacitor C2, and the second end of the capacitor C2 is connected to the gate of the transistor M2; A current source module is connected to the P-tube source follower module and the N-tube source follower module, and is used to provide a constant current bias to the N-tube source follower module, wherein the current source module maintains a constant drain voltage of the N-tube source follower module through the operational amplifier amp, and the current source module absorbs the current change caused by the sampling capacitor through the compensation capacitor; the current source module includes a capacitor Cc, an operational amplifier amp, a transistor M8, and a transistor M9, wherein: the first end of the capacitor Cc is connected to the source of the transistor M1 and the gate of the transistor M2, the second end of the capacitor Cc is connected to the negative phase input terminal of the operational amplifier amp, and the positive phase input terminal of the operational amplifier amp is connected to the bias voltage input terminal V b1 The drain of the transistor M8 is connected to the source of the transistor M2, the source of the transistor M8 is connected to the second end of the capacitor Cc, the negative input terminal of the operational amplifier amp, and the drain of the transistor M9, the gate of the transistor M8 is connected to the output terminal of the operational amplifier amp, and the gate of the transistor M9 is connected to the bias voltage input terminal V b2 Connecting, the source of the transistor M9 is grounded; A current mirror module is connected to the P-tube source follower module and the N-tube source follower module, and is used to transmit the constant current of the N-tube source follower module to the P-tube source follower module, so that the P-tube source follower module has a constant current; the current mirror module includes a transistor M5, a transistor M6, and a transistor M7, wherein: the drain of the transistor M5 is connected to the source of the transistor M1, the first end of the capacitor Cc, the second end of the capacitor C2, and the gate of the transistor M2; the source of the transistor M5 is connected to the drain of the transistor M6; the gate of the transistor M5 is connected to the bias voltage input terminal V b3 The gate of the transistor M6 is connected to the gate of the transistor M7, the drain of the transistor M7, and the drain of the transistor M4. The source of the transistor M6 is connected to the power supply voltage terminal, and the source of the transistor M7 is connected to the power supply voltage terminal.

2. The broadband input buffer for a high-speed and high-precision analog-to-digital converter according to claim 1, wherein: The transistor M1 and the transistor M3 are both PMOS transistors.

3. The broadband input buffer for a high-speed and high-precision analog-to-digital converter according to claim 1, wherein: The transistor M2 and the transistor M4 are both NMOS transistors.

4. The broadband input buffer for a high-speed and high-precision analog-to-digital converter according to claim 1, wherein: The transistor M5 , the transistor M6 , and the transistor M7 are all PMOS transistors, and the transistor M8 and the transistor M9 are both NMOS transistors.

Images