Dual-interface card manufacturing process and dual-interface card

Abstract

The present application discloses a manufacturing process for a dual-interface card and a dual-interface card. The manufacturing process for the dual-interface card includes: providing a first base layer, where a plurality of first holes are preset at intervals in the first base layer; providing an intermediate layer, where a plurality of coils are embedded at intervals inside the intermediate layer; providing a second base layer; stacking the first base layer, the intermediate layer, and the second base layer in sequence; before or after stacking the first base layer, the intermediate layer, and the second base layer, respectively providing chip modules corresponding to each of the first holes, and electrically connecting the chip modules to the corresponding coils; fixedly connecting the first base layer, the intermediate layer, the second base layer, and each chip module to form a substrate; and blanking the substrate to form a plurality of cards. The manufacturing process for the dual-interface card provided by the embodiments of the present application can effectively shorten the production process and improve the production efficiency.

Description

Technical Field

[0001] The present application belongs to the technical field of dual-interface cards, and in particular, relates to a dual-interface card manufacturing process and a dual-interface card. Background Art

[0002] The dual interface card is a multifunctional card that has both contact interface communication function and contactless interface communication function. The manufacturing process of the dual interface card usually includes the card body production and chip packaging. After the card body is manufactured, a slot is processed at a designated position of the card body, and the chip is packaged in the slot.

[0003] In the prior art, when processing and slotting the card body, the slots need to be completed one by one, resulting in low production efficiency of the card body. Summary of the invention

[0004] The embodiments of the present application provide a dual-interface card manufacturing process and a dual-interface card, which can shorten the production process of card production and improve production efficiency.

[0005] On the one hand, an embodiment of the present application provides a dual-interface card manufacturing process, comprising the following steps: setting a first base layer, the first base layer being pre-set with a plurality of first holes arranged at intervals; setting an intermediate layer, the interior of the intermediate layer being pre-buried with a plurality of coils arranged at intervals, so that at least a portion of each coil is exposed on a surface of the intermediate layer facing the first base layer; setting a second base layer; stacking the first base layer, the intermediate layer and the second base layer in sequence, so that each coil is arranged corresponding to a first hole before or after the first base layer, the intermediate layer and the second base layer are stacked, and chip modules are respectively arranged corresponding to each first hole, so that at least a portion of each chip module is located in the corresponding first hole, and the chip module is electrically connected to the corresponding coil; the first base layer, the intermediate layer, the second base layer and each chip module are fixedly connected to form a substrate; and the substrate is punched into a plurality of cards, each of which includes a chip module.

[0006] On the other hand, an embodiment of the present application provides a dual-interface card, including a first base layer, an intermediate layer and a chip module, wherein the first base layer and the intermediate layer are stacked; a first hole is opened in the first base layer, and at least a portion of the chip module is installed in the first hole; a coil is buried in the intermediate layer, and at least a portion of the coil is exposed and laid on the surface of the intermediate layer facing the first base layer, and the chip module is electrically connected to the portion of the coil exposed on the surface of the intermediate layer facing the first base layer through a conductive medium.

[0007] The embodiments of the present application provide a dual-interface card manufacturing process and a dual-interface card. Among them, in the dual-interface card manufacturing process of the embodiments of the present application, by presetting a plurality of first holes in the first base layer, chip modules can be respectively arranged in each first hole. After fixing the first base layer, the intermediate layer, the second base layer and each chip module, a substrate with a plurality of chip modules can be obtained. After punching the substrate, a plurality of cards can be obtained, thereby effectively shortening the production process and improving the production efficiency. Description of the Drawings

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0009] Figure 1 Schematic structural diagram of a dual-interface card provided by some embodiments of the present application;

[0010] Figure 2 Show Figure 1 Partial enlarged view of area A therein;

[0011] Figure 3 Schematic structural diagram of a dual-interface card provided by other embodiments of the present application;

[0012] Figure 4 Show Figure 3 Partial enlarged view of area B therein;

[0013] Figure 5 Top view of an intermediate layer of a dual-interface card provided by an embodiment of the present application;

[0014] Figure 6 Top view of another intermediate layer of a dual-interface card provided by an embodiment of the present application;

[0015] Figure 7 Top view of an insulating layer used for a carrier tape of a chip module for manufacturing a dual-interface card provided by an embodiment of the present application;

[0016] Figure 8 Schematic structural diagram of the stacked structure of an upper copper foil and a lower copper foil after etching and an insulating layer used for a carrier tape of a chip module for manufacturing a dual-interface card provided by an embodiment of the present application;

[0017] Figure 9 Schematic diagram of an etching shape of a lower copper foil used for a carrier tape of a chip module for manufacturing a dual-interface card provided by an embodiment of the present application after etching;

[0018] Figure 10Schematic diagram of another etching shape after etching the lower copper foil used for the carrier tape of the chip module of the dual-interface card provided in the embodiments of the present application;

[0019] Figure 11 Schematic diagram of yet another etching shape after etching the lower copper foil used for the carrier tape of the chip module of the dual-interface card provided in the embodiments of the present application;

[0020] Figure 12 Cross-sectional view of the chip module of the dual-interface card provided in the embodiments of the present application.

[0021] Description of reference numerals:

[0022] 1. First base layer; 11. First hole; 12. First substrate; 13. First protective film; 2. Intermediate layer; 21. Second hole; 22. Coil; 3. Second base layer; 31. Second substrate; 32. Second protective film; 4. Chip module; 41. Conductive sheet; 42. Carrier tape; 421. Pad; 422. Insulating layer; 4221. Reserved hole; 4222. Spacing portion; 4223. Reserved area; 423. Upper copper foil; 4231. Forming hole; 424. Lower copper foil; 43. Chip. Detailed implementation manners

[0023] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0024] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, elements defined by the statement "including..." do not exclude the presence of additional identical elements in the process, method, article or device including the said elements.

[0025] Conventional dual-interface card manufacturing usually adopts the butt welding process, which is divided into two sub-processes: card body production and welding and encapsulation. Card body production mainly involves manufacturing individual card bodies, and welding and encapsulation is to encapsulate the chip module in the card body to form a finished card.

[0026] In the sub-process of card body production, it includes:

[0027] Stack the upper base layer, coil layer, and lower base layer in sequence and perform lamination;

[0028] Die-cut the laminated upper base layer, coil layer, and lower base layer to form multiple individual card bodies.

[0029] In the sub-process of welding and encapsulation, it includes:

[0030] Mill grooves on the individual card body to form outer grooves and inner grooves;

[0031] Arrange the coil, and pick out the part of the coil exposed in the coil layer from the outer groove to the outside of the card body;

[0032] Weld the part of the coil picked out to the outside of the card body to the pad at the outside of the card body;

[0033] Install the chip module, place the chip module and the coil picked out to the outside of the card body in the outer groove. Among them, the carrier tape is placed in the outer groove, and the chip is placed in the inner groove;

[0034] Encapsulate the chip module in the card body to complete the production of the card. Generally, the hot melt pressing method is used to heat the chip module so that the chip module is press-fitted and encapsulated in the card body.

[0035] During the daily production process, the inventor found the following disadvantages of the butt welding process:

[0036] a. In the sub-process of welding and encapsulation, since groove milling operation needs to be performed on the card body, and groove milling operation is difficult to carry out in batches. Only one card body can be grooved at a time. Therefore, in the sub-process of card body production, the laminated upper base layer, coil layer, and lower base layer need to be die-cut to form multiple individual card bodies. Due to the need to perform groove milling operation on individual card bodies, the sub-process of welding and encapsulation can only operate on individual card bodies, resulting in a long production process and low production efficiency.

[0037] b. During the process of grooving an individual card body, it is necessary to mill and form outer grooves and inner grooves. During the process of milling the outer groove, once there are errors in the milling position or depth, the milling cutter will damage the coil located in the coil layer, and even cause the coil to break, affecting the non-contact communication after the card is formed and resulting in defective products.

[0038] c. During the process of soldering the coil to the pad, first, part of the coil is picked out from the outer groove to the outside of the clamping body. The coil picked out to the outside of the clamping body is soldered to the pad outside the clamping body, and the probability of virtual soldering is relatively high. In the actual production process, the probability of virtual soldering is approximately maintained at 2%. For the cards with virtual soldering, some can be remedied through manual operation and manual touch soldering, while the remaining cards that are difficult to remedy are directly scrapped, resulting in a lower yield rate of this part of the process compared to other processes, directly affecting the yield rate of card production.

[0039] d. Since the soldering of the coil to the chip module is located outside the clamping body and machine soldering is used, the length of the solder joints is generally long. After the chip module is encapsulated, during the three rounds of testing of the card, the card will bend, and the solder joints between the coil and the chip module will bend with the bending of the card. For some cards, due to the long solder joints between the coil and the chip module, the solder joints between the coil and the chip module are subjected to a large bending moment, which is likely to cause damage to the solder joints and de-soldering, and the card cannot pass the qualified test of the product.

[0040] e. After the coil is soldered to the chip module, the coil needs to be reorganized and placed in the outer groove. The coil will be folded, thus occupying a part of the thickness space, and the outer end of the chip module extends beyond the clamping body, resulting in poor flatness of the formed card. To solve this problem, during the milling process of the clamping body, the sum of the depths of the inner groove and the outer groove can be increased, but this will cause the thickness of the back of the clamping body to decrease, and the clamping body is prone to back imprints, affecting the appearance of the card.

[0041] f. Since the clamping body is first laminated and formed, and then the chip module is encapsulated in the clamping body. During the encapsulation process, a hot press head is required to heat and press the chip module separately. At the same time, to avoid the hot press head contacting the clamping body and affecting the appearance of the clamping body, the shape of the hot press head is the same as that of the chip module. Therefore, for special-shaped chip modules, the hot press head needs to be replaced to carry out the operation.

[0042] g. When the chip module is encapsulated in the clamping body, only the chip module is heated to soften the part of the clamping body in contact with the chip module, and the encapsulation of the chip module and the clamping body is completed. However, most of the softened part of the clamping body is concentrated in the coil layer in contact with the carrier tape. Due to the installation gap between the chip module and the upper base layer, the softening effect of the upper base layer is poor, resulting in difficulty in eliminating the installation gap between the chip module and the clamping body, affecting the appearance of the card. If the clamping body and the chip module are heated simultaneously for encapsulation, it will cause deformation of the clamping body, which has a greater impact on the appearance of the clamping body.

[0043] Example 1

[0044] This example provides a dual-interface card.

[0045] Combined with Figure 1 and Figure 2As shown in the figure, the dual-interface card includes a first base layer 1, an intermediate layer 2, and a chip module 4. The first base layer 1 and the intermediate layer 2 are stacked, and the chip module 4 is encapsulated within the first base layer 1 and the intermediate layer 2. One side of the chip module 4 is exposed on the surface of the first base layer 1 away from the intermediate layer 2.

[0046] The first base layer 1 is provided with a first hole 11 that penetrates the first base layer 1, and at least a part of the chip module 4 is installed in the first hole 11.

[0047] A coil 22 is embedded in the intermediate layer 2, and at least a part of the coil 22 is laid and exposed on the surface of the intermediate layer 2 facing the first base layer 1. The chip module 4 is electrically connected to at least a part of the coil 22 exposed on the surface of the intermediate layer 2 facing the first base layer 1 through a conductive medium.

[0048] The part of the coil 22 exposed on the surface of the intermediate layer 2 facing the first base layer 1 is laid on the intermediate layer 2, so that the arrangement of the coil 22 is relatively flat and does not occupy too much space in the first hole 11. After the chip module 4 is disposed in the first hole 11, it is electrically connected to the coil 22 through a conductive medium, and there is no need to pick out the coil 22 from the first hole 11, thus solving the problem of card quality caused by the coil 22 occupying the space in the first hole 11 and affecting the installation of the chip module 4.

[0049] Optionally, the coil 22 has a connection end that is laid and exposed on the surface of the intermediate layer 2 facing the first base layer 1. The chip module 4 is electrically connected to the connection end through a conductive medium, which is beneficial to improving the reliability of the electrical connection between the coil 22 and the chip module 4.

[0050] Optionally, the first hole 11 penetrates the first base layer 1 to facilitate the electrical connection between the chip module 4 and the coil 22.

[0051] The chip module 4 includes a carrier tape 42 and a chip 43. The chip 43 is soldered to the first side of the carrier tape 42. A solder pad 421 is formed on the first side of the carrier tape 42. Both the solder pad 421 and the chip 43 are electrically connected to the carrier tape 42. An encapsulating adhesive is provided outside the chip 43 to protect the chip 43. The electrical connection between the chip module 4 and the coil 22 is specifically that the coil 22 is electrically connected to the solder pad 421 through a conductive medium.

[0052] In some embodiments, the conductive medium between the coil 22 and the solder pad 421 is a conductive coating, and the conductive coating can be selected as solder paste. The conductive coating is applied to the part of the coil 22 exposed on the surface of the intermediate layer 2 facing the first base layer 1. Optionally, the conductive coating is applied to the connection end of the coil 22. The solder pad 421 in the chip module 4 contacts the conductive coating, and the solder paste melts when heated and can achieve the soldering of the solder pad 421 and the coil 22 after cooling.

[0053] The solder paste is applied to the part of the coil 22 exposed to the surface of the intermediate layer 2 facing the first base layer 1, which can control the amount of the solder paste. The coil 22 and the pad 421 are electrically connected through the solder paste. The solder paste is heated and melted and then solidified after cooling, which can realize the welding of the coil 22 and the pad 421. The coil 22 and the pad 421 are welded with the solder paste, which has the advantages of short solder joints and good welding effect. Since the solder joints between the coil 22 and the pad 421 are relatively short, when the card is bent, the bending moment borne by the solder joints is small, so the solder joints are not easily damaged, and the qualified rate of the product in three rounds of tests is relatively high, which can solve the problem of the relatively low qualified rate of the cards produced by the butt welding process in three rounds of tests, that is, problem d.

[0054] In some other embodiments, such as Figure 3 and Figure 4 , the conductive medium between the coil 22 and the chip module 4 is the conductive sheet 41. One part of the conductive sheet 41 is fixedly connected to the chip module 4, and the other part of the conductive sheet 41 is electrically connected to the coil 22. The conductive sheet 41 is made of a conductive material, such as copper foil.

[0055] Optionally, the conductive sheet 41 is located between the first base layer 1 and the intermediate layer 2, or the conductive sheet 41 is located in the first hole 11.

[0056] Exemplarily, the conductive sheet 41 has a strip-shaped sheet structure. One end of the conductive sheet 41 is connected to the chip module 4 in the first hole 11, and the other end of the conductive sheet 41 extends to the area between the first base layer 1 except the first hole 11 and the intermediate layer 2 and is electrically connected to the coil 22.

[0057] The conductive sheet 41 and the pad 421 are integrally formed or welded.

[0058] The conductive sheet 41 and the coil 22 are in contact connection or welded. When using the conductive sheet 41 to connect the pad 421 and the coil 22, if the welding method is adopted, the solder joints between the conductive sheet 41 and the coil 22 can be welded with the solder paste, which has the advantages of short solder joints and high connection reliability; if the contact connection method is adopted, there are no solder joints between the conductive sheet 41 and the coil 22. Whether the conductive sheet 41 and the coil 22 are in contact connection or welded, it can solve the problem of the relatively low qualified rate of the cards produced by the butt welding process in three rounds of tests, that is, problem d.

[0059] In some examples, the coil 22 has two connection ends, there are two conductive sheets 41, and the chip module 4 is electrically connected to the two connection ends through the two conductive sheets 41 respectively. After the coil 22, the conductive sheet 41 and the chip module 4 are electrically connected, a loop is formed.

[0060] Optionally, such as Figure 5As shown, the connecting ends of the two ends of the coil 22 are bent inwardly towards the area surrounded by the coil 22, so that the two connecting ends are located on both sides of the chip module 4, facilitating the electrical connection between the two conductive sheets 41 on the chip module 4 and the two connecting ends of the coil 22.

[0061] Optionally, as Figure 6 shown, the end portions of the connecting ends of the coil 22 are bent so that the end portions of the connecting ends are parallel to the length direction of the conductive sheet 41, which can increase the contact area between the conductive sheet 41 and the connecting ends of the coil 22, thereby improving the reliability and stability of the electrical connection between the conductive sheet 41 and the coil 22. Further, the portion of the connecting end of the coil 22 parallel to the conductive sheet 41 is provided in a wavy or zigzag shape to increase the contact stability between the conductive sheet 41 and the coil 22.

[0062] Optionally, the length of the conductive sheet 41 is the same as the length of the carrier tape 42, so that the conductive sheet 41 has enough length to contact the coil 22 to achieve electrical connection.

[0063] In some examples, the connecting ends of the coil 22 are straight, the conductive sheet 41 is in a strip-shaped sheet structure, and the connecting ends of the coil 22 and the conductive sheet 41 are arranged in a cross manner, optionally, perpendicularly. During the installation of the chip module 4, the coil 22 and the conductive sheet 41 can be smoothly brought into contact with each other.

[0064] When the conductive sheet 41 and the coil 22 are in a contact connection, the connecting ends of the coil 22 can be bent into a wavy or zigzag shape to increase the contact area between the conductive sheet 41 and the coil 22 and also increase the contact stability between the conductive sheet 41 and the coil 22.

[0065] In some embodiments, the intermediate layer 2 is provided with a second hole 21, and the second hole 21 communicates with the first hole 11. After the chip module 4 is installed in the first base layer 1 and the intermediate layer 2, at least a part of the chip module 4 is disposed in the second hole 21.

[0066] Optionally, a part of the chip module 4 is disposed in the first hole 11, and another part is disposed in the second hole 21, and the part of the chip module 4 disposed in the first hole 11 is the carrier tape 42, and the part disposed in the second hole 21 is the chip 43.

[0067] Optionally, in a direction perpendicular to the first base layer 1, the projection of the second hole 21 falls within the projection of the first hole 11. The first hole 11 and the second hole 21 form a stepped hole that decreases in size from the first base layer 1 to the intermediate layer 2, and the connecting ends of the coil 22 can be exposed at the stepped surface formed by the first hole 11 and the second hole 21. When the chip module 4 is installed in the stepped hole, the carrier tape 42 is accommodated in the first hole 11, and the pads 421 on the carrier tape 42 can be aligned with the connecting ends of the coil 22 and electrically connected through a conductive medium, and the chip 43 and the encapsulating glue outside the chip 43 are accommodated in the second hole 21.

[0068] Optionally, the chip 43 is welded to the middle part of the carrier tape 42, and the center lines of the first hole 11 and the second hole 21 coincide, so that the chip 43 and the carrier tape 42 can be smoothly placed in the second hole 21 and the first hole 11. Of course, the chip 43 can also be welded to other parts of the carrier tape 42, and the positions of the first hole 11 and the second hole 21 should be appropriately adjusted according to the positions of the chip 43 and the carrier tape 42 to ensure that after the chip module 4 is installed, the chip 43 is placed in the second hole 21 and the carrier tape 42 is placed in the first hole 11.

[0069] During the installation process, the length and width of the projection of the first hole 11 on the intermediate layer 2 are slightly larger than the length and width of the projection of the carrier tape 42 on the intermediate layer 2, the length and width of the projection of the second hole 21 on the intermediate layer 2 are slightly smaller than the length and width of the projection of the first hole 11 on the intermediate layer 2, and the length and width of the projection of the second hole 21 on the intermediate layer 2 are larger than the length and width of the encapsulating glue outside the chip 43 on the intermediate layer 2. That is, after the carrier tape 42 is installed in the first hole 11, the carrier tape 42 and the first hole 11 are in clearance fit, and after the chip 43 is installed in the second hole 21, the chip 43 and the second hole 21 are in clearance fit, so that the chip module 4 can be smoothly installed in the first hole 11 and the second hole 21. After the chip module 4 is installed in the first hole 11 and the second hole 21, the first base layer 1, the intermediate layer 2 and the chip module 4 can be laminated by heating and laminating. During the lamination process, the first base layer 1 will undergo plastic deformation to seal the gap between the first hole 11 and the carrier tape 42.

[0070] In some examples, in the direction perpendicular to the first base layer 1, the projection of the second hole 21 partially coincides with the projection of the first hole 11, or the projection of the first hole 11 falls within the projection of the second hole 21. In these examples, the conductive medium between the coil 22 and the chip module 4 is the conductive sheet 41, and the conductive sheet 41 is located between the first base layer 1 and the intermediate layer 2 to ensure that the part of the coil 22 exposed on the surface of the intermediate layer 2 facing the first base layer 1 is electrically connected to the chip module 4 through the conductive sheet 41.

[0071] In some embodiments, the dual-interface card further includes a second base layer 3, and the second base layer 3 is disposed on the side of the intermediate layer 2 away from the first base layer 1. The first base layer 1, the intermediate layer 2 and the second base layer 3 are sequentially laminated and fixed by lamination.

[0072] Optionally, the second base layer 3 includes a second substrate 31 and a second protective film 32, and the second protective film 32 is located on the side of the second substrate 31 away from the intermediate layer 2. A lower printing layer can be selectively disposed between the second protective film 32 and the second substrate 31. The second protective film 32 is mainly used to protect the second substrate 31, and the lower printing layer is used to provide the printed pattern of the card.

[0073] Optionally, the first base layer 1 includes a first substrate 12 and a first protective film 13, and the first protective film 13 is located on the side of the first substrate 12 away from the intermediate layer 2. A printing layer may be selectively provided between the first protective film 13 and the first substrate 12. The first protective film 13 is mainly used to protect the first substrate 12, and the printing layer is used to provide the printing pattern of the card.

[0074] Embodiment 2

[0075] This embodiment provides a dual-interface board manufacturing process for manufacturing the dual-interface board described in Embodiment 1, including steps S1 to S8.

[0076] S1: Set the first base layer 1. Among them, the first base layer 1 is preset with a plurality of first holes 11 arranged at intervals.

[0077] S2: Set the intermediate layer 2. Among them, a plurality of coils 22 arranged at intervals are embedded inside the intermediate layer 2, so that at least a part of each coil 22 is exposed on the surface of the intermediate layer 2 facing the first base layer 1.

[0078] S3: Set the second base layer 3.

[0079] S4: Stack the first base layer 1, the intermediate layer 2, and the second base layer 3 in sequence, so that each coil 22 is correspondingly arranged with the first hole 11.

[0080] S5: Before or after stacking the first base layer 1, the intermediate layer 2, and the second base layer 3, chip modules 4 are respectively arranged corresponding to the first holes 11, so that at least a part of each chip module 4 is located in the corresponding first hole 11.

[0081] S6: Electrically connect the chip module 4 and the coil 22.

[0082] S7: Fix and connect the first base layer 1, the intermediate layer 2, the second base layer 3, and each chip module 4 to form a substrate.

[0083] S8: Punch the substrate to form a plurality of cards, and each card includes a chip module 4.

[0084] In the above double-interface card manufacturing process, the first holes 11 are preset in the first base layer 1. Before or after the first base layer 1, the intermediate layer 2, and the second base layer 3 are stacked in sequence, the chip module 4 is then disposed in the corresponding first holes 11, and the electrical connection between the chip module 4 and the coil 22 is completed. After that, the first base layer 1, the intermediate layer 2, the second base layer 3, and each chip module 4 are fixedly connected to form a substrate. Finally, the substrate is blanked to form multiple cards. By adopting the above double-interface card manufacturing process, the first base layer 1 with the preset first holes 11 can use a large panel, and the intermediate layer 2 and the second base layer 3 can also use large panels. The chip modules 4 can be batch-set in the first holes 11. Therefore, the production process can adopt large-sheet production, and multiple cards can be produced simultaneously through one production process, which can greatly shorten the production process and improve production efficiency, solving the problems of long production process and low production efficiency in the butt welding process, that is, problem a.

[0085] Meanwhile, since the first holes 11 are preset in the first base layer 1, the process of forming the first holes 11 is carried out separately and will not affect the coil 22 in the intermediate layer 2, solving the problem that the coil 22 will be damaged during the process of forming the first holes 11, that is, problem b.

[0086] In some embodiments, before the step S1 of setting the first base layer 1, it includes: manufacturing the first base layer 1 and stamping each first hole 11 in the first base layer 1 at one time. Adopting stamping to form the first holes 11 is convenient for batch forming of the first holes 11, and has a fast forming speed and low cost.

[0087] Optionally, the first base layer 1 includes a first substrate 12 and a first protective film 13. After the first substrate 12 and the first protective film 13 are stacked, the first base layer 1 is formed by lamination, or after the first substrate 12 and the first protective film 13 are aligned, they are initially fixed to form the first base layer 1. The means of initially fixing the first substrate 12 and the first protective film 13 after alignment can be spot welding.

[0088] In some embodiments, in step S2, making at least a part of each of the coils 22 expose on the surface of the intermediate layer 2 facing the first base layer 1 includes: the coil 22 has a connection end, and making the connection ends of each coil 22 expose on the surface of the intermediate layer 2 facing the first base layer 1. A conductive medium can be coated on the connection ends of the coil 22 and / or the rest of the coil 22.

[0089] In some embodiments, in step S3, before the step S3 of setting the second base layer 3, it includes manufacturing the second base layer 3. Optionally, the second base layer 3 includes a second substrate 31 and a second protective film 32. After the second substrate 31 and the second protective film 32 are stacked, the second base layer 3 is formed by lamination, or after the second substrate 31 and the second protective film 32 are aligned, they are initially fixed to form the second base layer 3.

[0090] In some embodiments, step S6 of electrically connecting the chip module 4 and the coil 22 includes: covering a conductive medium at the connection end of the coil 22 so that the chip module 4 is in contact with the conductive medium.

[0091] Optionally, before covering the conductive medium on the coil 22, the paint layer at the covering position of the conductive medium on the coil 22 is removed to facilitate better electrical connection between the coil 22 and the chip module 4 through the conductive medium.

[0092] Optionally, the conductive medium is solder paste. The solder paste is coated at the connection end of the coil 22 so that the chip module 4 is in contact with the solder paste. After the solder paste is heated and melted and then cooled, the coil 22 and the chip module 4 can be soldered through the solder paste.

[0093] Optionally, the conductive medium is a conductive sheet 41. One end of the conductive sheet 41 is fixedly connected to the chip module 4, and the other end of the conductive sheet 41 is connected to the connection end of the coil 22. Among them, the connection between the conductive sheet 41 and the connection end of the coil 22 can be welding or contact electrical connection.

[0094] The chip module 4 includes a carrier tape 42 and a chip 43, and the carrier tape 42 has pads 421. The conductive sheet 41 and the pads 421 are fixedly connected by welding or integrally formed.

[0095] Optionally, in step S5, before arranging the chip module 4 in each first hole 11, manufacturing the chip module 4 is further included.

[0096] Manufacturing the chip module 4 includes: electrically connecting the chip 43 to the first side of the carrier tape 42, and arranging pads 421 on the first side of the carrier tape 42, and the conductive medium is electrically connected to the pads 421.

[0097] In some examples, when the conductive medium is the conductive sheet 41, in the step of manufacturing the chip module 4, the electrical connection between the conductive medium and the pads 421 includes: welding the conductive sheet 41 to the pads 421.

[0098] In some other examples, when the conductive medium is the conductive sheet 41, the carrier tape 42 includes a top copper foil 423, an insulating layer 422, and a bottom copper foil 424 that are sequentially stacked, and the conductive medium and the pads 421 are integrally formed to achieve electrical connection. The insulating layer 422 can be a glass cloth.

[0099] The step of manufacturing the chip module 4 further includes manufacturing the carrier tape 42. Specifically, as shown in Figure 7 and Figure 8 shown, manufacturing the carrier tape 42 includes steps S051 to S055.

[0100] S051: Arrange the insulating layer 422, the top copper foil 423, and the bottom copper foil 424.

[0101] The insulating layer 422 is preset with a plurality of reserved holes 4221, and the arrangement of the insulating layer 422 is as Figure 7 shown. The insulating layer 422 has a plurality of spaced portions 4222. The plurality of spaced portions 4222 crisscross each other to form a plurality of forming areas. Each forming area has two reserved holes 4221. The part of the insulating layer 422 between the two reserved holes 4221 in each forming area is a reserved area 4223. Each reserved area 4223 corresponds to the carrier tape 42 of a single chip module 4 and has the same shape.

[0102] The length and width of the upper copper foil 423 and the lower copper foil 424 are generally the same as those of the insulating layer 422 to facilitate the alignment of the insulating layer 422, the upper copper foil 423, and the lower copper foil 424.

[0103] Before setting the insulating layer 422, the reserved holes 4221 are processed and formed in the insulating layer 422, generally by stamping.

[0104] S052: Stack and align the upper copper foil 423, the insulating layer 422, and the lower copper foil 424 in sequence and perform lamination to form the carrier tape body.

[0105] The carrier tape body that can be formed after the lamination of the upper copper foil 423, the insulating layer 422, and the lower copper foil 424 has a relatively stable structure and serves as the mother body for producing the carrier tape 42.

[0106] S053: Etch the upper copper foil 423 to form forming holes 4231 that are completely corresponding to the reserved holes 4221 on the upper copper foil 423.

[0107] As Figure 8 shown, through the effect of etching, the part of the upper copper foil 423 corresponding to the reserved holes 4221 is etched away, so as to form forming holes 4231 that are completely corresponding to the reserved holes 4221 on the upper copper foil 423. After etching, the corresponding upper copper foil 423 in each forming area corresponds to the reserved area 4223 and has the same shape.

[0108] S054: Etch the lower copper foil 424. After etching, at least a part of the lower copper foil 424 forms a plurality of conductive sheets 41.

[0109] As Figure 8 shown, by etching the lower copper foil 424 according to the design requirements, at least a part of the remaining lower copper foil 424 after etching is the conductive sheet 41.

[0110] Each carrier tape 42 corresponds to two conductive sheets 41. The two conductive sheets 41 are located on the first side and the second side of each carrier tape 42. A part of the conductive sheet 41 corresponds to and is electrically connected to the coil pad 421 of the carrier tape 42, and the other part of the conductive sheet 41 extends beyond the first side or the second side of the corresponding carrier tape 42.

[0111] The shape of the conductive sheet 41 has various forms. Exemplarily, as Figure 9 shown, the conductive sheet 41 is square, and the width of the conductive sheet 41 is the same as the width of the carrier tape 42. Or, as Figure 10 shown, the conductive sheet 41 is T-shaped, the head of the T-shaped conductive sheet 41 corresponds to and is electrically connected to the coil pad 421 of the carrier tape 42, and the tail of the T-shaped conductive sheet 41 extends beyond the first side or the second side of the carrier tape 42. Or, as Figure 11 shown, the conductive sheet 41 is strip-shaped.

[0112] Among them, the larger the width of the conductive sheet 41, the better the contact effect between the conductive sheet 41 and the coil 22, and the width of the conductive sheet 41 can be greater than the width corresponding to a single carrier tape 42. Of course, according to needs, the width of the conductive sheet 41 can also be set to be less than or equal to the width of a single carrier tape 42.

[0113] S055: Die-cut the carrier tape body to form a plurality of carrier tapes 42.

[0114] After the carrier tape body is die-cut, each forming area forms a carrier tape 42 with a conductive sheet 41, and the specific structure is as Figure 12 shown.

[0115] The carrier tape 42 is manufactured by using steps S051 to S055. The carrier tape 42 is produced in a large-sheet manner, that is, a relatively large upper copper foil 423, an insulating layer 422, and a lower copper foil 424 are used for production. After the upper copper foil 423, the insulating layer 422, and the lower copper foil 424 are laminated, a large-sheet carrier tape body is formed. After the carrier tape body is etched and die-cut, each large-sheet carrier tape body can be made into a plurality of carrier tapes 42 used in the chip module 4, greatly improving the processing efficiency. Figure 7 and Figure 8 are only partial structural schematic diagrams of the insulating layer 422 and the carrier tape body in the large-sheet production. In the actual production process, a plurality of forming areas can be arranged horizontally on the carrier tape body, and a plurality of forming areas can also be arranged vertically on the carrier tape body. A carrier tape 42 with a conductive sheet 41 can be formed in each forming area.

[0116] In step S054, the etched lower copper foil 424 can be directly formed into the conductive sheet 41. Or, a part of the etched lower copper foil 424 is the conductive sheet 41. After die-cutting through step S055, the lower copper foil 424 can be separated after die-cutting, and the part connected to the reserved area 4223 is the conductive sheet 41.

[0117] Among them, the upper copper foil 423 and the lower copper foil 424 also include other functional areas that are the same as those in the prior art and are not clearly shown in the figure.

[0118] Optionally, before or after step S055, it includes: welding the chip 43 to the lower copper foil 424. After completing step S055, a plurality of complete chip modules 4 are formed. Among them, if the chip 43 is welded to the lower copper foil 424 before step S054, the solder paste for welding can be coated on the lower copper foil 424, and then the chip 43 is batch-mounted and welded to the lower copper foil 424 by a mounter, realizing batch production and improving production efficiency.

[0119] In some embodiments, the intermediate layer 2 provided in step S2 is preset with a plurality of second holes 21 arranged at intervals. Before step S2 of setting the intermediate layer 2, it includes: manufacturing the intermediate layer 2, stamping a plurality of second holes 21 in the intermediate layer 2 at one time. In the state where the first base layer 1, the intermediate layer 2, and the second base layer 3 are stacked, each second hole 21 communicates with a first hole 11, the carrier tape 42 of each chip module 4 is disposed in the corresponding first hole 11, and the chip 43 of each chip module 4 is disposed in the corresponding second hole 21.

[0120] Opening the second holes 21 in the intermediate layer 2 can accommodate the chips 43 in the chip modules 4 through the second holes 21, achieving better protection for the chips 43. Adopting the stamping and forming method to open the second holes 21 can improve the processing efficiency and reduce the processing cost.

[0121] In some embodiments, in step S7, fixedly connecting the first base layer 1, the intermediate layer 2, the second base layer 3, and each chip module 4 to form a substrate includes:

[0122] S71: Pre-positioning the first base layer 1, the intermediate layer, and the second base layer 3;

[0123] S72: Laminating and fixing the first base layer 1, the intermediate layer 2, the second base layer 3, and the chip module 4.

[0124] Pre-positioning the first base layer 1, the intermediate layer, and the second base layer 3 can improve the stability after the first base layer 1, the intermediate layer, and the second base layer 3 are stacked, and avoid the offset of the first base layer 1, the intermediate layer 2, and the second base layer 3 during the lamination and fixing process. The pre-positioning method of the first base layer 1, the intermediate layer 2, and the second base layer 3 can be spot welding.

[0125] In some embodiments, in step S5, before stacking the first base layer 1, the intermediate layer 2, and the second base layer 3, chip modules 4 are respectively arranged corresponding to the first holes 11, so that at least a part of each chip module 4 is located in the corresponding first hole 11.

[0126] Exemplarily, the carrier tape 42 of the chip module 4 is received in the corresponding first hole 11, and the conductive sheet 41 is attached to the surface of the first base layer 1 facing the intermediate layer 2. After the chip module 4 is received in the corresponding first hole 11, the first base layer 1, the intermediate layer 2, and the second base layer 3 are stacked, and the conductive sheet 41 can be in contact electrical connection with the coil 22, or soldered to the coil 22 using solder paste.

[0127] In some other embodiments, in step S5, after the first base layer 1, the intermediate layer 2, and the second base layer 3 are stacked, the chip module 4 is respectively provided corresponding to each first hole 11, so that at least a part of each chip module 4 is located in the corresponding first hole 11.

[0128] Exemplarily, the carrier tape 42 of the chip module 4 is received in the first hole 11, the chip 43 is received in the second hole 21, and the part of the coil 22 exposed on the surface of the intermediate layer 2 facing the first base layer 1 contacts or is soldered using solder paste with the pad 421, so that the coil 22 is electrically connected to the chip module 4.

[0129] In the above example, the pad 421 and the chip 43 are located on one side surface of the carrier tape 42 facing the intermediate layer 2. The chip 43 only occupies a part of the carrier tape 42. Generally, the chip 43 is located in the middle part of the carrier tape 42. The projection of the connection end of each coil 22 on the intermediate layer 2 falls into the projection of the first hole 11 on the intermediate layer 2, that is, a part of the surface of the intermediate layer 2 facing the first base layer 1 is exposed in the first hole 11. The connection end of the coil 22 can extend to the surface of the intermediate layer 2 exposed in the first hole 11. When installing the chip module 4, the chip 43 is received in the second hole 21, the carrier tape 42 is received in the first hole 11, and a part of the surface of the carrier tape 42 facing the chip 43 is opposite to a part of the surface of the intermediate layer 2 exposed in the first hole 11, so as to smoothly realize the electrical connection between the pad 421 and the connection end of the coil 22.

[0130] In the embodiments of the present application, steps S1 to S3 are not in a sequential order. After steps S1, S2, and S3 are completed, the implementation order of steps S4 to S7 can include the following two ways.

[0131] Exemplarily, one implementation order of steps S4 to S7 is:

[0132] First, execute step S4 to stack the first base layer 1, the intermediate layer 2, and the second base layer 3 in sequence, so that each coil 22 is disposed opposite to the first hole 11;

[0133] After that, execute step S71 in step S7 to pre-position the sequentially stacked first base layer 1, intermediate layer 2, and second base layer 3;

[0134] After that, step S5 is executed, and a chip module 4 is respectively arranged corresponding to each first hole 11, so that at least a part of each chip module 4 is located in the corresponding first hole 11; in this process, the chip module 4 is electrically connected to the part of the coil 22 exposed on the surface of the intermediate layer 2 facing the first base layer 1, and step S6 is completed;

[0135] Finally, step S72 in step S7 is executed to laminate and fix the first base layer 1, the intermediate layer 2, and the second base layer 3 on which the chip module 4 is arranged and stacked in sequence.

[0136] Exemplarily, another implementation sequence of steps S4 to S7 is:

[0137] First, step S5 is executed, and a chip module 4 is respectively arranged corresponding to each first hole 11, so that at least a part of each chip module 4 is located in the corresponding first hole 11, wherein the pad 421 of the chip module 4 is located on the surface of the chip module 4 facing the intermediate layer 2;

[0138] After that, step S4 is executed, and the first base layer 1, the intermediate layer 2, and the second base layer 3 are stacked in sequence, so that each coil 22 is arranged opposite to the first hole 11. In this process, the pad 421 of the chip module 4 and the part of the coil 22 exposed on the surface of the intermediate layer 2 facing the first base layer 1 are electrically connected through a conductive medium, and step S6 is completed;

[0139] Finally, step S7 is executed to fixedly connect the first base layer 1, the intermediate layer 2, the second base layer 3, and each chip module 4 to form a substrate.

[0140] In summary, the dual-interface card manufacturing process of the embodiment of the present application has the following advantages:

[0141] The first base layer 1 preset with the first holes 11 can adopt a large sheet panel, and the intermediate layer 2 and the second base layer 3 preset with the second holes 21 can also adopt large sheet panels. The chip modules 4 can be batch-set in the first holes 11. Therefore, the production process can adopt large-sheet production, and multiple cards can be produced simultaneously through one production process, which can greatly shorten the production process and improve production efficiency, solving the problems of long production process and short production efficiency in the butt welding process, that is, problem a.

[0142] The first holes 11 are preset in the first base layer 1, and the second holes 21 are preset in the intermediate layer 2. The first holes 11 and the second holes 21 are formed before the first base layer 1 and the intermediate layer 2 are stacked. Therefore, during the process of forming the first holes 11 and the second holes 21, the coil 22 will not be affected, solving the problem that the coil 22 will be damaged during the process of forming the first holes 11, that is, problem b generated in the butt welding process.

[0143] Before or after laminating the first base layer 1, the intermediate layer 2, and the second base layer 3, chip modules 4 are respectively provided corresponding to the first holes 11, so that at least a part of each chip module 4 is located in the corresponding first hole 11. At least a part of the coil 22 can also be exposed and laid on the surface of the intermediate layer 2 facing the first base layer 1 without picking out the coil 22 outside the first hole 11. During the process of disposing the chip module 4 in the corresponding first hole 11, the chip module 4 and the coil 22 can be electrically connected through a conductive medium, thereby solving the card quality problem caused by the coil 22 occupying the space in the first hole 11 and affecting the installation of the chip module 4, that is, problems c and e generated in the butt welding process.

[0144] When the chip module 4 and the coil 22 are electrically connected through solder paste, the solder joint between the coil 22 and the chip module 4 is short. When the card is bent, the bending moment borne by the solder joint is small, so the solder joint is not easily damaged, and the qualified rate of the product in three rounds of tests is relatively high, which can solve the problem of the low qualified rate of the cards produced by the butt welding process in three rounds of tests, that is, problem d. When the chip module 4 and the coil 22 are electrically connected through a conductive sheet 41, the connection between the conductive sheet 41 and the coil 22 is a contact connection or soldered through solder paste, and there is no solder joint or the solder joint is short between the conductive sheet 41 and the coil 22, which can also solve the problem of the low qualified rate of the cards produced by the butt welding process in three rounds of tests, that is, problem d.

[0145] The first base layer 1, the intermediate layer 2, the second base layer 3, and the chip module 4 are laminated simultaneously, without separately setting a hot pressing head to perform separate lamination on the chip module 4. For chip modules 4 of any shape, the same set of lamination equipment can be used to laminate the first base layer 1, the intermediate layer 2, the second base layer 3, and the chip module 4, solving the problem of poor adaptability of the hot pressing head during the lamination process of chip modules 4 of different shapes, that is, problem f generated in the butt welding process.

[0146] Before laminating and fixing the first base layer 1, the intermediate layer 2, the second base layer 3, and the chip module 4, the chip module 4 has been installed with the first base layer 1, the intermediate layer 2, and the second base layer 3. At this time, during lamination, the material forming the first base layer 1 will have a slight flow due to heat and pressure, thereby filling the gap between the chip module 4 and the first base layer 1, solving the problem that it is difficult to fill the gap between the chip module 4 and the first base layer 1, that is, solving problem g generated in the butt welding process.

[0147] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application accordingly. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A dual-interface card manufacturing process, characterized in that, The following steps are involved: Provide a first base layer, wherein the first base layer is preset with a plurality of first holes arranged at intervals; An intermediate layer is provided, wherein a plurality of coils arranged at intervals are pre-buried inside the intermediate layer, wherein the coils have connection ends, and the connection ends of the coils are exposed on the surface of the intermediate layer facing the first base layer, and a conductive sheet is covered at the connection ends, wherein the conductive sheet is in a strip-shaped sheet structure, and one end of the conductive sheet extends to between the area of ​​the first base layer excluding the first hole and the intermediate layer, and is electrically connected to the coils, and the connection ends of the coils are arranged crosswise with the conductive sheet; Set up a second base layer; The first base layer, the middle layer and the second base layer are stacked in sequence, so that each of the coils is arranged corresponding to one of the first holes; Before or after stacking the first base layer, the middle layer and the second base layer, a chip module is respectively arranged corresponding to each of the first holes, so that at least a part of each of the chip modules is located in the corresponding first hole, the chip module is electrically connected to the corresponding coil, and the other end of the conductive sheet is connected to the chip module in the first hole; The first base layer, the middle layer, the second base layer and each chip module are fixedly connected to form a substrate; The substrate is punched into a plurality of cards, each of which includes one chip module.

2. The dual-interface card manufacturing process according to claim 1, wherein The first base layer, the middle layer, the second base layer and each chip module are fixedly connected to form a substrate, including: pre-positioning the first base layer, the intermediate layer, and the second base layer; The first base layer, the middle layer, the second base layer and the chip module are laminated and fixed.

3. The manufacturing process of the dual-interface card according to claim 1, characterized in that Before setting up the first base layer include: The first base layer is manufactured, and the first holes are formed in the first base layer by punching at one time.

4. The manufacturing process of the dual-interface card according to claim 1, characterized in that, The chip module comprises a carrier tape and a chip; before the chip module is arranged in each of the first holes, the method further comprises: Manufacturing the chip module includes: The chip is electrically connected to the first side of the carrier tape, and a pad is arranged on the first side of the carrier tape, and the conductive sheet is electrically connected to the pad.

5. The manufacturing process of the dual-interface card according to claim 4, characterized in that, Before setting up the middle layer, include: Manufacturing the intermediate layer, punching a plurality of second holes in the intermediate layer at one time, wherein each of the second holes is connected to one of the first holes when the first base layer, the intermediate layer and the second base layer are stacked; The carrier tape of each chip module is arranged in the corresponding first hole, and the chip of each chip module is arranged in the corresponding second hole.

6. The dual-interface card manufacturing process according to claim 1, characterized in that, The chip module comprises a carrier tape and a chip, wherein the carrier tape comprises an upper copper foil, an insulating layer and a lower copper foil which are sequentially stacked; Before arranging a chip module in each of the first holes, the method further comprises: Manufacturing the chip module includes: An upper copper foil, an insulating layer and a lower copper foil are provided, wherein the insulating layer is preset with a plurality of reserved holes; The upper copper foil, the insulating layer and the lower copper foil are sequentially stacked and aligned, and laminated to form a carrier tape body; Etching the upper copper foil to form a formed hole on the upper copper foil that completely corresponds to the reserved hole; Etch the lower copper foil, and at least a part of the etched lower copper foil forms a plurality of the conductive sheets; Die-cut the carrier tape body to form a plurality of the carrier tapes.

7. The manufacturing process of the dual-interface card according to claim 6, characterized in that, The insulating layer is a glass woven fabric.

8. A dual-interface card, characterized in that, It is made by using the dual-interface card manufacturing process according to any one of claims 1-7. The dual-interface card includes a first base layer, an intermediate layer, and a chip module, and the first base layer and the intermediate layer are stacked; The first base layer is provided with a first hole, and at least a part of the chip module is installed in the first hole; A coil is embedded in the intermediate layer, and at least a part of the coil is exposed and laid on the surface of the intermediate layer facing the first base layer. The chip module is electrically connected to the part of the coil exposed on the surface of the intermediate layer facing the first base layer through a conductive medium; the conductive medium is a conductive sheet, the conductive sheet is in a strip-like sheet structure, one end of the conductive sheet is connected to the chip module in the first hole, and the other end of the conductive sheet extends to the area between the first base layer except the first hole and the intermediate layer and is electrically connected to the coil, and the connection end of the coil is arranged in a cross manner with the conductive sheet.

9. The dual-interface card according to claim 8, wherein, The coil has a connection end, the connection end is exposed on the surface of the intermediate layer facing the first base layer, and the chip module is electrically connected to the connection end through the conductive medium.

10. The dual-interface card according to claim 9, characterized in that, The conductive medium is a conductive coating, the conductive coating is coated on the coil, and the chip module is in conductive contact with the conductive coating.

11. The dual-interface card according to claim 9, wherein, The intermediate layer is provided with a second hole, the second hole is communicated with the first hole, and at least a part of the chip module is arranged in the second hole.

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