Test structure for measuring alignment deviation

Abstract

The present application discloses a test structure for measuring alignment deviation, including: a silicon cube, a first bonding material layer formed on the top layer of the silicon cube, which is formed on a dielectric film, which is formed on a first wafer; a second bonding material layer, which is formed on the second wafer; wherein, from a top view, the test area includes a central area, the silicon cube is formed in a first area and a second area of ​​the test area, a plurality of silicon cubes are formed in the first area, a plurality of silicon cubes are formed in the second area, the first area is located above the central area, the second area is located to the right of the central area, each silicon cube in the first area is parallel to each other, each silicon cube in the second area is parallel to each other, and the second bonding material layer is rectangular. The present application can measure the alignment deviation of the sensor wafer by detecting the conductive silicon cube, thereby improving the accuracy of monitoring the alignment accuracy.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a test structure for measuring alignment deviation. Background Art

[0002] Complementary metal oxide semiconductor (CMOS)-micro-electro-mechanical system (MEMS) sensor is a device formed by bonding CMOS wafer and MEMS wafer. During its manufacturing process, the microscopic pattern alignment accuracy of CMOS and MEMS is extremely important and directly affects the device performance.

[0003] The related art provides a CMOS-MEMS sensor, which includes a first wafer, a second wafer, and a third wafer bonded in sequence, wherein the first wafer is a capping layer of the sensor, the second wafer is a wafer formed with a MEMS device, and the third wafer is a wafer formed with a CMOS device. The second wafer and the third wafer are bonded by a eutectic bonding process, a first bonding material layer is formed on the second wafer, a second bonding material layer is formed on the third wafer, and the second wafer and the third wafer are eutectic bonded by the first bonding material layer and the second bonding material layer.

[0004] However, since the alignment pattern in the related art only has the search mark of the bonding machine, namely the first search mark of the first bonding material layer and the second search mark of the second bonding material layer, but there is no mark for measuring the overlay error of the first search mark and the second search mark (i.e., the registration mark), it is impossible to accurately judge the alignment deviation and effectively monitor the alignment accuracy of the bonding machine. Summary of the invention

[0005] The present application provides a test structure for measuring alignment deviation, which can solve the problem that the alignment pattern provided in the related art cannot effectively monitor the alignment accuracy of the bonding machine due to the lack of registration marks, thereby reducing the yield to a certain extent.

[0006] The test structure is applied to a CMOS-MEMS sensor, the CMOS-MEMS sensor comprises a first wafer and a second wafer, the first wafer is a wafer formed with a MEMS device, the second wafer is a wafer formed with a CMOS device, the test structure is formed in a test area, and the test structure comprises:

[0007] A silicon cube, a top layer of which is formed with a first bonding material layer, the silicon cube is formed on a dielectric film, and the dielectric film is formed on the first wafer;

[0008] a second bonding material layer, wherein the second bonding material layer is formed on the second wafer;

[0009] Wherein, when viewed from a top view, the test area includes a central area, the silicon cube is formed in a first area and a second area of ​​the test area, a plurality of the silicon cubes are formed in the first area, a plurality of the silicon cubes are formed in the second area, the first area is located above the central area, the second area is located to the right of the central area, each of the silicon cubes in the first area is parallel to each other, each of the silicon cubes in the second area is parallel to each other, and the second bonding material layer is rectangular;

[0010] When the first wafer and the second wafer are bonded and the alignment deviation does not meet the deviation standard, the second bonding material layer is bonded to the first bonding material layer of at least one top layer of the silicon cube; when the first wafer and the second wafer are bonded and the alignment deviation meets the deviation standard, the second bonding material layer is not bonded to the first bonding material layer of the top layer of the silicon cube and is located in the central area.

[0011] In some embodiments, the first bonding material layer includes a germanium layer.

[0012] In some embodiments, the second bonding material layer includes an aluminum layer.

[0013] In some embodiments, the test area also includes a third area and a fourth area. When viewed from the top, the third area is located below the central area, and the fourth area is located to the left of the central area. Each of the silicon cubes in the third area is parallel to each other, and each of the silicon cubes in the fourth area is parallel to each other.

[0014] In some embodiments, when viewed from the top, the silicon cube is rectangular, and in the first region, the second region, the third region, and the fourth region, the spacing between each silicon cube is equal.

[0015] In some embodiments, when viewed from the top, the direction of the length of the silicon cubes in the first region is perpendicular to the direction of the length of the silicon cubes in the second region, the direction of the length of the silicon cubes in the third region is parallel to the direction of the length of the silicon cubes in the first region, and the direction of the length of the silicon cubes in the fourth region is perpendicular to the direction of the length of the silicon cubes in the second region.

[0016] In some embodiments, when viewed from the top, the silicon cube is L-shaped, and in the first region, the second region, the third region, and the fourth region, the spacing between each silicon cube is equal.

[0017] In some embodiments, when viewed from the top, the direction of the length of the silicon cubes in the first region is perpendicular to the direction of the length of the silicon cubes in the second region, the direction of the length of the silicon cubes in the third region is parallel to the direction of the length of the silicon cubes in the first region, and the direction of the length of the silicon cubes in the fourth region is perpendicular to the direction of the length of the silicon cubes in the second region.

[0018] In some embodiments, the CMOS-MEMS sensor further includes a third wafer, the third wafer is a capping layer of the sensor, the third wafer is bonded to a back side of the first wafer, and the back side is a surface of the first wafer where the test structure is not formed;

[0019] The MEMS sensor includes a fixed electrode and a movable electrode, and a groove is formed between the fixed electrode and the movable electrode;

[0020] A cavity corresponding to the fixed electrode and the movable electrode is formed on a surface of the third wafer to be bonded to the back surface of the second wafer.

[0021] In some embodiments, the MEMS sensor includes a pressure sensor and / or an acceleration sensor.

[0022] The technical solution of this application has at least the following advantages:

[0023] A silicon cube grid located in different areas of the central area of ​​the test area is formed on the first wafer of the CMOS-MEMS sensor, and a second bonding material layer corresponding to the central area is formed on the second wafer of the CMOS-MEMS sensor. When the first wafer and the second wafer are bonded, if the alignment deviation does not meet the deviation standard, the second bonding material layer will be bonded to the first bonding material layer on the top layer of at least one silicon cube. Then, the alignment deviation of the sensor wafer can be measured by detecting the conductive silicon cube, thereby improving the accuracy of monitoring the alignment accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 is a top view schematic diagram of a test structure for measuring alignment deviation provided by an exemplary embodiment of the present application;

[0026] Figure 2 is a cross-sectional schematic diagram of a test structure for measuring alignment deviation provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0029] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0030] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0031] refer to Figure 1, which shows a top view schematic diagram of a test structure for measuring alignment deviation provided by an exemplary embodiment of the present application; Figure 2 , which shows a cross-sectional schematic diagram of a test structure for measuring alignment deviation provided by an exemplary embodiment of the present application; Figure 1 and Figure 2 The area shown is the test area 100. Figure 2 yes Figure 1 Section view along the center line AA.

[0032] like Figure 1 and Figure 2 As shown, the test structure is applied to a CMOS-MEMS sensor, which includes a first wafer 110 and a second wafer 210. The first wafer 110 is formed with a MEMS device ( Figure 1 and Figure 2 The second wafer 210 is a wafer having CMOS devices ( Figure 1 and Figure 2 The test structure is formed in the test area 100, and the test structure includes:

[0033] The silicon cube 130 has a first bonding material layer 140 formed on its top layer, which is formed on a dielectric film 120 formed on a first wafer 110. The first bonding material layer 140 may include a germanium (Ge) layer.

[0034] The second bonding material layer 220 is formed on the second wafer 210. The second bonding material layer 220 may include an aluminum (Al) layer.

[0035] Among them, when observed from a top-down angle, the test area 100 includes a central area (a region centered on the center of the test area 100 and smaller in area than the test area 100, which may be rectangular, circular, elliptical, etc.), and silicon cubes 130 are formed in a first area 101 and a second area 102 in the test area 100. A plurality of silicon cubes 130 are formed in the first area 101, and a plurality of silicon cubes 130 are formed in the second area 102. The first area 101 is located above the central area, and the second area 102 is located to the right of the central area. Each silicon cube 130 in the first area 101 is parallel to each other, and each silicon cube 130 in the second area 102 is parallel to each other, and the second bonding material layer 220 is a rectangle.

[0036] When the first wafer 110 and the second wafer 210 are bonded and the alignment deviation does not meet the deviation standard, the second bonding material layer 220 is bonded to the first bonding material layer 140 on the top layer of at least one silicon cube 130. When the first wafer 110 and the second wafer 210 are bonded and the alignment deviation meets the deviation standard, the second bonding material layer 220 is not bonded to the first bonding material layer 140 on the top layer of the silicon cube 130 and is located in the central area.

[0037] In some embodiments, Figure 1 As shown, the test area 100 also includes a third area 103 and a fourth area 104. From a top view, the third area 103 is located below the central area, and the fourth area 104 is located to the left of the central area. Each silicon cube 130 in the third area 103 is parallel to each other, and each silicon cube 130 in the fourth area 104 is parallel to each other.

[0038] In some embodiments, when viewed from a top-down perspective, the silicon cube 130 is rectangular, and the spacing between each silicon cube 130 in the first region 101, the second region 102, the third region 103, and the fourth region 104 is equal; in some embodiments, the direction in which the length of the silicon cube 130 in the first region 101 is perpendicular to the direction in which the length of the silicon cube 130 in the second region 102 is perpendicular, the direction in which the length of the silicon cube 130 in the third region 103 is parallel to the direction in which the length of the silicon cube 130 in the first region 101 is parallel, and the direction in which the length of the silicon cube 130 in the fourth region 104 is perpendicular to the direction in which the length of the silicon cube 130 in the second region 102 is perpendicular.

[0039] In some embodiments, when viewed from a top view, the silicon cube 130 is L-shaped, and the spacing between each silicon cube 130 in the first region 101, the second region 102, the third region 103 and the fourth region 104 is equal; in some embodiments, when viewed from a top view, the direction in which the length of the silicon cube 130 in the first region 101 (the length of the L-shape in this embodiment is the length of any one of the two rectangles constituting the L-shape) is perpendicular to the direction in which the length of the silicon cube 130 in the second region 102 is perpendicular, the direction in which the length of the silicon cube 130 in the third region 103 is parallel to the direction in which the length of the silicon cube 130 in the first region 101 is parallel, and the direction in which the length of the silicon cube 130 in the fourth region 104 is perpendicular to the direction in which the length of the silicon cube 130 in the second region 102 is perpendicular.

[0040] To summarize, in the embodiment of the present application, a silicon cube grid located in different areas of the central area of ​​the test area is formed on the first wafer of the CMOS-MEMS sensor, and a second bonding material layer corresponding to the central area is formed on the second wafer of the CMOS-MEMS sensor. When the first wafer and the second wafer are bonded, if the alignment deviation does not meet the deviation standard, the second bonding material layer will be bonded to the first bonding material layer on the top layer of at least one silicon cube. The alignment deviation of the sensor wafer can be measured by detecting the conductive silicon cube, thereby improving the accuracy of monitoring the alignment accuracy.

[0041] In some embodiments, the CMOS-MEMS sensor further includes a third wafer ( Figure 1 and Figure 2 (not shown in the figure), the third wafer is the capping layer of the sensor, the third wafer is bonded to the back side of the first wafer, and the back side is the surface of the first wafer where no test structure is formed; the MEMS sensor includes a fixed electrode and a movable electrode, and a groove is formed between the fixed electrode and the movable electrode; a cavity corresponding to the fixed electrode and the movable electrode is formed on the surface of the third wafer bonded to the back side of the second wafer.

[0042] In some embodiments, the MEMS sensor includes a pressure sensor and / or an acceleration sensor.

[0043] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A test structure for measuring alignment deviation, characterized in that: The test structure is applied to a CMOS-MEMS sensor, the CMOS-MEMS sensor comprises a first wafer and a second wafer, the first wafer is a wafer formed with a MEMS device, the second wafer is a wafer formed with a CMOS device, the test structure is formed in a test area, and the test structure comprises: A silicon cube, a top layer of which is formed with a first bonding material layer, the silicon cube is formed on a dielectric film, and the dielectric film is formed on the first wafer; a second bonding material layer, wherein the second bonding material layer is formed on the second wafer; Wherein, when viewed from a top view, the test area includes a central area, the silicon cube is formed in a first area and a second area of ​​the test area, a plurality of the silicon cubes are formed in the first area, a plurality of the silicon cubes are formed in the second area, the first area is located above the central area, the second area is located to the right of the central area, each of the silicon cubes in the first area is parallel to each other, each of the silicon cubes in the second area is parallel to each other, and the second bonding material layer is rectangular; When the first wafer and the second wafer are bonded and the alignment deviation does not meet the deviation standard, the second bonding material layer is bonded to the first bonding material layer of at least one top layer of the silicon cube, and when the first wafer and the second wafer are bonded and the alignment deviation meets the deviation standard, the second bonding material layer is not bonded to the first bonding material layer of the top layer of the silicon cube and is located in the central area; The test area further includes a third area and a fourth area. When viewed from the top, the third area is located below the central area, the fourth area is located to the left of the central area, each of the silicon cubes in the third area is parallel to each other, and each of the silicon cubes in the fourth area is parallel to each other; Observed from the top view, the silicon cube is rectangular, and the spacing between each silicon cube in the first area, the second area, the third area and the fourth area is equal, the direction of the length of the silicon cube in the first area is perpendicular to the direction of the length of the silicon cube in the second area, the direction of the length of the silicon cube in the third area is parallel to the direction of the length of the silicon cube in the first area, and the direction of the length of the silicon cube in the fourth area is perpendicular to the direction of the length of the silicon cube in the second area. The silicon cube is L-shaped, and the spacing between each silicon cube in the first area, the second area, the third area and the fourth area is equal.

2. The test structure according to claim 1, characterized in that: The first bonding material layer includes a germanium layer.

3. The test structure according to claim 2, characterized in that: The second bonding material layer includes an aluminum layer.

4. The test structure according to claim 1, characterized in that: When viewed from the top, the direction in which the length of the silicon cubes in the first region is perpendicular to the direction in which the length of the silicon cubes in the second region is perpendicular, the direction in which the length of the silicon cubes in the third region is parallel to the direction in which the length of the silicon cubes in the first region is parallel, and the direction in which the length of the silicon cubes in the fourth region is perpendicular to the direction in which the length of the silicon cubes in the second region is perpendicular.

5. The test structure according to any one of claims 1 to 4, characterized in that: The CMOS-MEMS sensor further includes a third wafer, the third wafer being a capping layer of the sensor, the third wafer being bonded to the back surface of the first wafer, the back surface being a surface of the first wafer on which the test structure is not formed; The MEMS sensor includes a fixed electrode and a movable electrode, and a groove is formed between the fixed electrode and the movable electrode; A cavity corresponding to the fixed electrode and the movable electrode is formed on a surface of the third wafer to be bonded to the back surface of the second wafer.

6. The test structure according to claim 5, characterized in that: The MEMS sensor includes a pressure sensor and / or an acceleration sensor.

Images