A test method for automatically detecting stability of IC clip

Abstract

The application provides a kind of test method for automatically detecting IC clamp stability, which comprises that the chip to be tested is connected with the first contact pin and provides reference voltage for generating measurement voltage, and the chip to be tested is connected with the second contact pin and provides charge voltage for generating measurement voltage; when the chip to be tested is tested and adjusted, the reference voltage and charge voltage of the chip to be tested are measured respectively, a contact resistance is generated when the test system contacts with the chip to be tested, the resistance value of the contact resistance is calculated according to the reference voltage and charge voltage, the contact condition of the chip to be tested and the test system and the oxidation degree of the gold finger surface are determined according to the resistance value of the contact resistance, and the internal reference voltage of the chip to be tested is calibrated based on the target reference voltage. The application can solve the problem of automatic testing of low-cost MCU chips, and can quickly measure the contact resistance to determine the contact condition.

Description

Technical Field

[0001] This invention relates to the field of electronic power technology, and more specifically to a test method for automatically detecting the stability of IC clamping. Background Technology

[0002] Typically, chips undergo FT testing before leaving the factory to filter out defective products and ensure product quality. During testing, issues such as bent chip pins, aging equipment, or inconsistent specifications between different manufacturers frequently arise, significantly impacting test stability. The most prominent problem is the uncontrollable contact resistance between the chip and the test system, resulting in inconsistent electrical performance in each test, a long-standing challenge for engineers and hindering normal mass production shipments. Common methods for testing contact resistance include using a digital multimeter to test the contact between the chip and the test system, or using an ATE platform to test the chip and the test system contact.

[0003] Digital multimeter testing typically involves placing one probe on the gold finger support of the testing equipment and the other on the exposed pads of the test board to measure the resistance between them. This determines the resistance between the chip pins and the test board, thus assessing the contact. This method generally has low accuracy, is susceptible to the position of the testing equipment's clamping bracket, and cannot achieve real-time testing. It requires manual measurement by engineers, hindering automated production and resulting in low efficiency. ATE testing requires a dedicated board that uses its testing functions to detect the gold finger contact. This method requires expensive boards, highly specialized equipment, and is unsuitable for testing low-cost chips. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide a test method for automatically detecting the stability of IC clamping. This method solves the problem of automated testing of low-cost MCU chips and can quickly measure the contact resistance to determine the contact condition.

[0005] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0006] A test method for automatically detecting the stability of IC clamping includes the following steps: the chip under test is connected to a first contact pin and a reference voltage is provided for generating the measurement voltage; the chip under test is connected to a second contact pin and a charge voltage is provided for generating the measurement voltage.

[0007] When the reference voltage of the chip under test is adjusted, the reference voltage and charge voltage of the chip under test are measured respectively. When the test system contacts the chip under test, a contact resistance is generated. The resistance value of the contact resistance is calculated based on the reference voltage and charge voltage, and is expressed as formula (1):

[0008] R0=(V2-K*V1) / (I*(K-1)) (1)

[0009] Where V1 is the reference voltage value, V2 is the charge voltage value, and K is the ratio between the reference voltage and the charge voltage;

[0010] The contact condition between the chip under test and the test system and the degree of oxidation on the gold finger surface are determined based on the contact resistance value, and the internal reference voltage of the chip under test is calibrated based on the target reference voltage.

[0011] A further approach is to either reposition or discard the chip under test if the contact resistance exceeds a preset value; and to perform calibration if the contact resistance does not exceed a preset value.

[0012] A further approach is to add an AD conversion channel to the test system to measure the voltage difference across the contact resistor, and to calibrate the internal reference voltage of the chip under test by eliminating the voltage difference across the contact resistor.

[0013] A further approach is to have a test system with a first AD conversion channel and a second AD conversion channel. The test system measures the reference voltage value of the chip under test and the voltage difference across the contact resistor through the first AD conversion channel and the second AD conversion channel, respectively. The test system calibrates the internal reference voltage value of the chip under test by subtracting the reference voltage value of the chip under test from the voltage difference across the contact resistor.

[0014] A further improvement is that the test system also has a third AD conversion channel. The test system measures the reference voltage and charge voltage of the chip under test through the first AD conversion channel and the third AD conversion channel respectively, and calculates the contact resistance based on the reference voltage and charge voltage.

[0015] A further approach involves subtracting the values ​​to obtain the calibration voltage value of the chip under test corresponding to the current calibration value. The testing system then determines whether an optimal calibration voltage value exists. If it does, the internal reference voltage value of the chip under test is set according to the calibration value corresponding to the optimal calibration voltage value, and the entire calibration process ends. Otherwise, a calibration failure result is output.

[0016] A further approach is to determine whether the difference between the calibrated reference voltage of the chip under test and the target reference voltage is within the error range when setting the internal reference voltage value of the chip under test according to the calibration value corresponding to the optimal calibration voltage value. If so, the calibration result is output.

[0017] A further approach is to recalibrate the reference voltage of the chip under test if the difference between the reference voltage and the target reference voltage is not within the error range, and then re-perform the judgment to determine whether the difference between the reference voltage and the target reference voltage of the calibrated chip under test is within the error range.

[0018] A further approach involves determining whether the difference between the calibrated reference voltage of the chip under test and the target reference voltage is within the error range, specifically including:

[0019] Determine whether the difference between the reference voltage of the calibrated chip under test and the target reference voltage is positive or negative. If it is positive, decrease the reference voltage of the chip under test by a set voltage value and then determine whether the difference between the reference voltage of the chip under test and the target reference voltage is within the error range. If it is negative, increase the reference voltage of the chip under test by a set voltage value and then determine whether the difference between the reference voltage of the chip under test and the target reference voltage is within the error range.

[0020] A further approach is to set K as the amplification ratio of the internal amplification and comparator circuit of the chip, with a typical value of 2.8.

[0021] Therefore, compared with the prior art, the present invention utilizes the ratio between the reference voltage and the charge voltage inside the chip. When the chip is being tested and the reference is being adjusted, the values ​​of the reference voltage and the charge voltage are measured respectively. Based on the ratio between the two, the contact resistance is calculated, and the contact condition between the chip and the test system, as well as the degree of oxidation on the gold finger surface, are determined. This allows for real-time detection of the contact condition, making it very suitable for automated testing. It can improve the efficiency of testing and avoid the adverse effects caused by poor contact.

[0022] Furthermore, the present invention can also eliminate the influence of the voltage difference across the contact resistor to achieve calibration of the internal reference voltage value of the chip, thereby improving the accuracy of the internal reference voltage value of the chip.

[0023] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0024] Figure 1 This is a flowchart of an embodiment of a test method for automatically detecting the stability of IC clamping according to the present invention.

[0025] Figure 2 This is a schematic diagram of an embodiment of a test method for automatically detecting the stability of IC clamping according to the present invention. Detailed Implementation

[0026] An embodiment of a test method for automatically detecting the stability of IC clamping:

[0027] See Figure 1and Figure 2 A test method for automatically detecting the stability of IC clamping includes the following steps:

[0028] Step S1: The chip under test U1 is connected to the first contact pin and a reference voltage is provided for generating the measurement voltage. The chip under test U1 is also connected to the second contact pin and a charge voltage is provided for generating the measurement voltage.

[0029] Step S2: When testing and adjusting the reference of the chip U1 under test, measure the reference voltage and charge voltage of the chip U1 under test respectively.

[0030] Step S3: When the test system contacts the chip U1 under test, a contact resistance R0 is generated. The resistance value of the contact resistance R0 is calculated based on the reference voltage and the charge voltage, and is expressed as formula (1):

[0031] R0=(V2-K*V1) / (I*(K-1)) (1)

[0032] Where V1 is the reference voltage value, V2 is the charge voltage value, and K is the ratio between the reference voltage and the charge voltage.

[0033] Step S4: Determine the contact condition between the chip U1 under test and the test system, as well as the degree of oxidation on the gold finger surface, based on the resistance value of the contact resistance R0.

[0034] Step S5: Calibrate the internal reference voltage of the chip U1 under test based on the target reference voltage.

[0035] Since most low-cost MCU chips have an internal reference voltage, which is crucial for the chip's normal operation and directly affects the accuracy of peripherals (such as ADCs, DACs, and charges) on the chip, a key aspect of pre-shipment testing is reference voltage adjustment. However, the measured reference voltage can be affected by contact conditions, especially when the gold finger surface is severely oxidized. In such cases, the reference voltage will deviate from the target value, and the accuracy of the corresponding peripherals will also be affected. In this embodiment, during chip testing and reference voltage adjustment, the present invention utilizes the ratio between the internal reference voltage and charge voltage of the chip. It measures both the reference voltage and the charge voltage simultaneously to detect the contact condition in real time and determines the chip's contact status based on their ratio.

[0036] During chip testing, the reference voltage and charge voltage can be released through the chip's two pins. By measuring the voltages V1 and V2 on these two pins, the current I flowing into the ground plane, and adding the ratio K between the reference voltage and the charge voltage determined during chip design, the contact resistance R0 can be calculated using the formula R0 = (V2 - K * V1) / (I * (K - 1)). This allows us to determine the contact condition between the chip and the test system, as well as the degree of oxidation on the gold finger surface.

[0037] Furthermore, the ratio K between the charge voltage and the reference voltage is determined by an internal amplification and comparator circuit that links the reference voltage and the charge voltage. If the reference voltage increases, the charge voltage increases, and vice versa. This ratio K is a parameter set to detect the chip's clamping stability. The value of K is the amplification ratio of the internal amplification and comparator circuit, typically 2.8.

[0038] If the contact resistance R0 exceeds a preset value, the chip under test U1 is either repositioned or discarded; if the contact resistance R0 does not exceed a preset value, calibration is performed. For example, if the contact resistance R0 exceeds 1 ohm, the chip under test U1 is either repositioned or discarded; if the contact resistance R0 does not exceed 1 ohm, calibration is performed. It is evident that by detecting the magnitude of the ADC contact resistance R0, chips with excessively high contact resistance R0 are repositioned or discarded to ensure chip calibration accuracy, thereby achieving high-precision measurement. Furthermore, the calibration efficiency is significantly improved compared to previous testing methods, saving testing costs.

[0039] Furthermore, the test system adds an AD conversion channel to measure the voltage difference across the contact resistor R0, and calibrates the internal reference voltage value of the chip U1 under test by eliminating the voltage difference across the contact resistor R0.

[0040] Specifically, the test system has a first AD conversion channel and a second AD conversion channel. The test system measures the reference voltage value of the chip under test U1 and the voltage difference across the contact resistor R0 through the first AD conversion channel and the second AD conversion channel, respectively. The test system calibrates the internal reference voltage value of the chip under test U1 by subtracting the reference voltage value of the chip under test U1 from the voltage difference across the contact resistor R0.

[0041] Furthermore, the test system also has a third AD conversion channel. The test system measures the reference voltage and charge voltage of the chip under test U1 through the first AD conversion channel and the third AD conversion channel respectively, and calculates the contact resistance R0 based on the reference voltage and charge voltage.

[0042] In this embodiment, after subtraction, the calibration voltage value of the chip under test U1 corresponding to the current calibration value is obtained. The test system determines whether there is an optimal calibration voltage value. If there is, the internal reference voltage value of the chip under test U1 is set according to the calibration value corresponding to the optimal calibration voltage value and the entire calibration process ends. Otherwise, the calibration failure result is output.

[0043] When setting the internal reference voltage value of the chip under test U1 according to the calibration value corresponding to the optimal calibration voltage value, it is determined whether the difference between the reference voltage of the calibrated chip under test U1 and the target reference voltage is within the error range. If so, the calibration result is output.

[0044] If the difference between the reference voltage of the chip under test U1 and the target reference voltage is not within the error range, the reference voltage of the chip under test U1 is recalibrated, and the difference between the reference voltage of the chip under test U1 and the target reference voltage after calibration is checked again to see if it is within the error range.

[0045] In this embodiment, determining whether the difference between the reference voltage of the calibrated test chip U1 and the target reference voltage is within the error range specifically includes:

[0046] Determine whether the difference between the reference voltage of the calibrated chip U1 and the target reference voltage is positive or negative. If it is positive, decrease the reference voltage of the chip U1 by a set voltage value and then determine whether the difference between the reference voltage of the chip U1 and the target reference voltage is within the error range. If it is negative, increase the reference voltage of the chip U1 by a set voltage value and then determine whether the difference between the reference voltage of the chip U1 and the target reference voltage is within the error range.

[0047] In this embodiment, a voltage comparator is used to determine whether the difference between the reference voltage of the calibrated chip U1 and the target reference voltage is within the error range. When the voltage comparator outputs a high level (i.e., the chip's reference voltage is greater than the target reference voltage), the calibration bit of the reference voltage is decreased, and the voltage comparison is repeated once until the voltage comparator outputs a low level. If the voltage comparator outputs a low level (i.e., the chip's reference voltage is less than the target reference voltage), the calibration bit of the reference voltage is increased, and the voltage comparison is performed again until the voltage comparator outputs a high level.

[0048] In this embodiment, a target reference voltage is sent, and a comparator compares the reference voltage of the chip under test (U1) with the target reference voltage. If the reference voltage of U1 is greater than the target reference voltage, the reference voltage of U1 is decreased until the difference between the reference voltage and the target reference voltage falls within the error range. If the reference voltage of U1 is less than the target reference voltage, the reference voltage is increased until the difference between the reference voltage and the target reference voltage falls within the error range. By changing the traditional method of directly measuring the reference voltage of U1 to comparing the reference voltage of U1 with a set target reference voltage and calibrating the reference voltage of U1 using the difference, and generating the target reference voltage using a low-order tester, the entire process does not require a high-order tester, greatly reducing the testing cost. Moreover, the entire process only involves comparing the magnitude of voltage values, making the test procedure simple and highly operable.

[0049] Therefore, compared with the prior art, the present invention utilizes the ratio between the reference voltage and the charge voltage inside the chip. When the chip is being tested and the reference is being adjusted, the values ​​of the reference voltage and the charge voltage are measured respectively. Based on the ratio between the two, the contact resistance R0 is calculated, thereby determining the contact condition between the chip and the test system and the degree of oxidation on the gold finger surface. This allows for real-time detection of the contact condition, making it very suitable for automated testing. It can improve the efficiency of testing and avoid the adverse effects caused by poor contact.

[0050] Furthermore, the present invention can also eliminate the influence of the voltage difference across the contact resistor R0, so as to achieve calibration of the internal reference voltage value of the chip, thereby improving the accuracy of the internal reference voltage value of the chip.

[0051] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A test method for automatically detecting stability of IC clip testing, characterized by, The method comprises the following steps: The to-be-tested chip is connected with the first contact pin and provides a reference voltage for generating a measurement voltage, and the to-be-tested chip is connected with the second contact pin and provides a charge voltage for generating a measurement voltage; When the to-be-tested chip is tested and trimmed, the reference voltage and the charge voltage of the to-be-tested chip are measured respectively, a contact resistance is generated when the test system contacts the to-be-tested chip, the resistance value of the contact resistance is calculated according to the reference voltage and the charge voltage, and is expressed as formula (1): R0=(V2-K*V1) / (I*(K-1)) (1) Wherein, V1 is the reference voltage value, V2 is the charge voltage value, and K is the proportional relationship between the reference voltage and the charge voltage; The contact condition of the to-be-tested chip and the test system and the oxidation degree of the gold finger surface are determined according to the resistance value of the contact resistance, and the internal reference voltage of the to-be-tested chip is calibrated based on the target reference voltage; When it is determined that the contact resistance exceeds the preset value, the to-be-tested chip is repositioned or discarded; when it is determined that the contact resistance does not exceed the preset value, calibration is performed; The test system measures the voltage difference between the two ends of the contact resistance by adding an AD conversion channel, and calibrates the internal reference voltage value of the to-be-tested chip by eliminating the voltage difference between the two ends of the contact resistance; The test system has a first AD conversion channel and a second AD conversion channel, the test system measures the reference voltage value of the to-be-tested chip and the voltage difference between the two ends of the contact resistance through the first AD conversion channel and the second AD conversion channel respectively, and the test system calibrates the internal reference voltage value of the to-be-tested chip according to the calibration voltage value obtained by subtracting the voltage difference between the two ends of the contact resistance from the reference voltage value of the to-be-tested chip.

2. The method of claim 1, wherein: The test system further has a third AD conversion channel, the test system measures the reference voltage value and the charge voltage value of the to-be-tested chip through the first AD conversion channel and the third AD conversion channel respectively, and calculates the resistance value of the contact resistance according to the reference voltage value and the charge voltage value.

3. The method of claim 1, wherein: After the subtraction processing, the calibration voltage value of the to-be-tested chip corresponding to the current calibration value is obtained; whether there is an optimal calibration voltage value is determined by the test system, if there is, the internal reference voltage value of the to-be-tested chip is set according to the calibration value corresponding to the optimal calibration voltage value and the whole calibration process is ended, otherwise, a calibration failure result is output.

4. The method of claim 3, wherein: When the internal reference voltage value of the to-be-tested chip is set according to the calibration value corresponding to the optimal calibration voltage value, whether the difference between the reference voltage of the calibrated to-be-tested chip and the target reference voltage is within an error range is determined, if yes, a calibration result is output.

5. The method of claim 4, wherein: If the difference between the reference voltage of the chip to be tested and the target reference voltage is not within the error range, the reference voltage of the chip to be tested is calibrated again, and whether the difference between the calibrated reference voltage of the chip to be tested and the target reference voltage is within the error range is judged again.

6. The method of claim 4, wherein: The judgment of whether the difference between the calibrated reference voltage of the chip to be tested and the target reference voltage is within the error range specifically comprises: If the difference is positive, the reference voltage of the chip to be tested is reduced by a set voltage value, and whether the difference between the reference voltage of the chip to be tested and the target reference voltage is within the error range is judged; if the difference is negative, the reference voltage of the chip to be tested is increased by a set voltage value, and whether the difference between the reference voltage of the chip to be tested and the target reference voltage is within the error range is judged.

7. The method of claim 1, wherein: The K value is the amplification ratio value of the amplification comparison circuit inside the chip, and the typical value is 2.8.

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