Data transmission control method across field programmable logic gate array and related device

Abstract

The present application provides a method for data transmission control across field programmable logic gate arrays and related devices. The method includes: using a first register device to latch a set of data from a first field programmable logic gate array according to a first clock, wherein the set of data is sorted according to data load and pointer signal attributes and divided into multiple sets of local data; using a time division multiplexing interface to sequentially transmit the multiple sets of local data from the first register device to a second register device at multiple time points according to a time division multiplexing clock; and using the second register device to sequentially receive the multiple sets of local data to output the set of data to a second field programmable logic gate array, wherein the second field programmable logic gate array operates according to a second clock different from the first clock.

Description

TECHNICAL FIELD

[0001] The present application relates to high-speed communication across devices, and in particular, to a method for controlling data transmission across field programmable gate arrays (FPGAs) and related devices. BACKGROUND

[0002] FPGAs are often used in system development flow, in which the hardware resources of one FPGA can not be sufficient for use in some systems, and thus multiple FPGAs are needed to play the roles of different partitions in the system, and these FPGAs are connected to each other to perform prototyping design and emulation of the whole system. There are about thousands of input / output (IO) available in one FPGA, and in a more complex system, the signal transmission width between different partitions in the system often reaches tens of thousands of bits, and thus the number of IOs of the FPGA becomes a major limitation in the development flow. In addition, in the related art, these interconnected FPGAs can not operate at their respective optimized operating frequencies in order to match the operating frequencies of each other, and thus the overall performance is limited.

[0003] Therefore, there is a need for a novel method for controlling data transmission and related devices to perform inter-FPGA data transmission under the condition that the number of IOs of the FPGA is limited, and to allow each FPGA to operate at its respective optimized frequency. SUMMARY

[0004] Therefore, an object of the present application is to provide a method for controlling data transmission across FPGAs and related devices to allow different FPGAs to operate at their respective optimized frequencies.

[0005] At least one embodiment of the present application provides a method for data transfer control across field programmable logic arrays. The method can include: latching, by a first register device, a set of data from a first field programmable logic array according to a first clock, wherein the set of data is ordered and divided into a plurality of local data sets according to payload and pointer attributes; transferring, by a Time-Division Multiplexing (TDM) interface, the plurality of local data sets from the first register device to a second register device sequentially at a plurality of time points according to a TDM clock; and receiving, by the second register device, the plurality of local data sets sequentially to output the set of data to a second field programmable logic array, wherein the second field programmable logic array operates according to a second clock different from the first clock.

[0006] At least one embodiment of the present application provides an apparatus for emulation of an electronic system, wherein the apparatus can include a first field programmable logic array, a second field programmable logic array, a first register device, a second register device, and a Time-Division Multiplexing (TDM) interface. The first register device is coupled to the first field programmable logic array, and the second register device is coupled to the second field programmable logic array, wherein the TDM interface is coupled between the first register device and the second register device. The first field programmable logic array can be used for emulation of a first subsystem of the electronic system, wherein the first field programmable logic array operates according to a first clock. The second field programmable logic array can be used for emulation of a second subsystem of the electronic system, wherein the second field programmable logic array operates according to a second clock different from the first clock. In particular, the first register device latches a set of data from the first field programmable logic array according to the first clock, wherein the set of data is ordered and divided into a plurality of local data sets according to payload and pointer attributes to allow the TDM interface to transfer the plurality of local data sets from the first register device to a second register device sequentially at a plurality of time points according to a TDM clock. Further, the second register device can receive the plurality of local data sets sequentially to output the set of data to the second field programmable logic array.

[0007] The method and apparatus provided by embodiments of the present application can completely isolate clock domains of the first field programmable logic array and the second field programmable logic array by means of a non-synchronous transmission interface ordered according to data payload and pointer signal attributes, so that the first field programmable logic array and the second field programmable logic array can both operate at their respective optimized frequencies. In particular, embodiments of the present application do not substantially increase additional costs. Therefore, the present application can solve problems of the related art without or with less side effects. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A schematic diagram of an apparatus for emulation of an electronic system in accordance with an embodiment of the present application.

[0009] Figure 2 An example of an asynchronous first-in-first-out register corresponding to a certain lane.

[0010] Figure 3 An example of an asynchronous first-in-first-out register corresponding to another lane.

[0011] Figure 4 An example of arranging data of the same direction in a plurality of lane types to produce a set of data.

[0012] Figure 5 An example of further arranging data within the set of data in Figure 4 .

[0013] Figure 6 A schematic diagram of an apparatus for emulation of an electronic system in accordance with an embodiment of the present application.

[0014] Figure 7 Certain details of the connection apparatus in accordance with an embodiment of the present application. Figure 6

[0015] Figure 8 A workflow of a method for data transfer control across field programmable gate arrays in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0016] Figure 1 A schematic diagram of an apparatus 10 for emulation of an electronic system in accordance with an embodiment of the present application, wherein the apparatus 10 can comprise a first field programmable gate array FPGA A and a second field programmable gate array FPGA B . In this embodiment, the first field programmable gate array FPGA A may be used for emulation of a first subsystem of the electronic system, while the second field programmable gate array FPGA B may be used for emulation of a second subsystem of the electronic system, wherein the first field programmable gate array FPGA A operates in accordance with a first clock, while the second field programmable gate array FPGA B operates in accordance with a second clock. For example, the first field programmable gate array FPGA A and the second field programmable gate array FPGA B ​All of these can be implemented using field-programmable gate arrays from a vendor such as Xilinx, but the present invention is not limited thereto.

[0017] like Figure 1 As shown, the first field-programmable gate array (FPGA) A The second field-programmable gate array (FPGA) can be connected via the connection device 100. B The connection, wherein the connection device 100 may conform to the Advanced Dextensible Interface (AXI) bus protocol, but the present invention is not limited thereto. In this embodiment, the first field-programmable gate array (FPGA) A It can be used as a master device, therefore the connection device 100 is connected to the first field-programmable gate array (FPGA). A That end can serve as the AXI master, while the second FPGA (Field Programmable Gate Array) B It can be used as a slave device, therefore the connection device 100 is connected to a second field-programmable gate array (FPGA). B That end can serve as an AXI slave, wherein the connection device 100 can connect to the first field-programmable gate array (FPGA) at the AXI master end. A A two-way handshake is performed, and the connection device 100 can connect to the second field-programmable gate array (FPGA) at the AXI slave end. B A two-way handshake is performed, but the invention is not limited thereto.

[0018] like Figure 1 As shown, the first field-programmable gate array (FPGA) A With the second field-programmable gate array (FPGA) B Data transmission between them can include multiple channel types. For example, the channels described by the AXI bus protocol can include address read (AR), address write (AW), write (W), read (R), and response (B) channels. In this embodiment, the connection device 100 can include multiple asynchronous First In First Out (FIFO) registers (hereinafter referred to as "asynchronous FIFO") such as asynchronous FIFOs 110, 120, 130, 140, and 150 to be used for the above-mentioned multiple channel types respectively.

[0019] In this embodiment, each of the above-mentioned multiple channel types can include data transmission in two directions. Figure 2Take the non-synchronous FIFO 110 corresponding to the AR (i.e. Address Read) channel as an example, where the non-synchronous FIFO 110 can receive the relevant data / instruction of the AR channel from the AXI master end and transfer to the AXI slave end in a first-in-first-out manner. As shown in Figure 2 , the non-synchronous FIFO 110 can include a non-synchronous FIFO master end 111 (which can be a register file consisting of multiple registers) and a non-synchronous FIFO slave end 112 (which can be multiple multiplexers), where the relevant data / instruction of the AR channel is received from the AXI master end through the non-synchronous FIFO master end 111 and then transferred to the AXI slave end through the non-synchronous FIFO slave end 112. In this embodiment, the communication between the non-synchronous FIFO master end 111 and the non-synchronous FIFO slave end 112 can include data transmission in two directions, where the data transmission in the first direction can include the AR write pointer and AR load (e.g. data load) transferred from the non-synchronous FIFO master end 111 to the non-synchronous FIFO slave end 112, and the data transmission in the second direction can include the AR read pointer transferred from the non-synchronous FIFO slave end 112 to the non-synchronous FIFO master end 111.

[0020] In addition, Figure 3 Take the non-synchronous FIFO 140 corresponding to the R (i.e. Read) channel as an example, where the non-synchronous FIFO 140 can receive the relevant data / instruction of the R channel from the AXI slave end and transfer to the AXI master end in a first-in-first-out manner. As shown in Figure 3 , the non-synchronous FIFO 140 can include a non-synchronous FIFO master end 141 (which can be a register file consisting of multiple registers) and a non-synchronous FIFO slave end 142 (which can be multiple multiplexers), where the relevant data / instruction of the R channel is received from the AXI slave end through the non-synchronous FIFO master end 141 and then transferred to the AXI master end through the non-synchronous FIFO slave end 142. In this embodiment, the communication between the non-synchronous FIFO master end 141 and the non-synchronous FIFO slave end 142 can include data transmission in two directions, where the data transmission in the first direction can include the R write pointer and R load transferred from the non-synchronous FIFO master end 141 to the non-synchronous FIFO slave end 142, and the data transmission in the second direction can include the R read pointer transferred from the non-synchronous FIFO slave end 142 to the non-synchronous FIFO master end 141.

[0021] Based on the description of Figure 2 and Figure 3 , the relevant details of the relevant data / instruction of other channel types such as the AW channel, W channel and B channel can be similarly deduced, which are not described here for brevity.

[0022] Therefore, data transmission between the AXI master and AXI slave on each channel can include: data transmitted from the AXI master to the AXI slave, which, if distinguished by data attributes, could include AR write pointer, AR payload, AW write pointer, AW payload, W write pointer, W payload, R read pointer, and B read pointer; and data transmitted from the AXI slave to the AXI master, which, if distinguished by data attributes, could include AR read pointer, AW read pointer, W read pointer, R write pointer, R payload, B write pointer, and B payload. Figure 4 As shown, among these multiple channel types, data with the same data transmission direction (e.g., from the AXI master to the AXI slave, or from the AXI slave to the AXI master) can be arranged together to generate a set of data. For example, the AXI master can arrange the AR write pointer, AR payload, AW write pointer, AW payload, W write pointer, W payload, R read pointer, and B read pointer together to generate a set of transmitted data DATA. TX The AXI slave can arrange the AR read pointer, AW read pointer, W read pointer, R write pointer, R payload, B write pointer, and B payload together to generate a set of received data DATA. RX Therefore, this group of data (e.g., the group of transmitted data DATA) TX Or the group receives data DATA RX It may contain at least one read pointer, at least one payload, or at least one write pointer. It should be noted that the at least one payload is preferably transferred from the AXI master to the AXI slave at a time earlier than the at least one write pointer is transferred from the AXI master to the AXI slave, and the at least one read pointer is preferably transferred from the AXI master to the AXI slave at a time earlier than the at least one payload is transferred from the AXI master to the AXI slave. Therefore, in Figure 5 In this embodiment, the group of transmitted data DATA can be... TX The AR write pointer, AR payload, AW write pointer, AW payload, W write pointer, W payload, R read pointer, and B read pointer are further ordered according to payload and pointer attributes (e.g., transmission order) to R read pointer, B read pointer, AR payload, AW payload, W payload, AR write pointer, AW write pointer, and W write pointer, and can then receive this group of data. RX The AR read pointer, AW read pointer, W read pointer, R write pointer, R load, B write pointer, and B load are further sorted according to load and pointer attributes (e.g., transmission order) to AR read pointer, AW read pointer, W read pointer, R load, B load, R write pointer, and B write pointer.

[0023] Figure 6This is a schematic diagram of a device 60 for simulating an electronic system according to an embodiment of the present invention, wherein the device 60 can be used as... Figure 1 An example of device 10 is shown. (As shown in the image) Figure 6 As shown, the first field-programmable gate array (FPGA) A and the second field-programmable gate array (FPGA) B External devices can be interconnected via a connection device 600, wherein the connection device 600 may include components coupled to a first field-programmable gate array (FPGA). A The transmitter 600TX and the FPGA coupled to the second field-programmable gate array B The receiver 600RX and the transmitter 600TX can be connected to each other via a cable.

[0024] Figure 7 According to one embodiment of the present invention Figure 6 Some details of the connecting device 600 shown, in which Figure 7 It is to transmit data DATA TX For example, the received data DATA RX The only difference is the direction of data transmission; all other details can be found in the transmitted data (DATA). TX The examples can be deduced by analogy. For example... Figure 7 As shown, the connection device 600 may include a first register 610, a second register 620, and a time-division multiplexing interface such as a Low Voltage Differential Signaling (LVDS) serializer / deserializer (SerDes) 630. In this embodiment, the transmitter 600TX and the receiver 600RX may be embedded in the LVDS serializer / deserializer 630, but the invention is not limited thereto. In some embodiments, at least a portion (e.g., a portion or all) of the first register 610 may be disposed outside the connection device 600; for example, at least a portion (e.g., a portion or all) of the first register 610 may be a first field-programmable gate array (FPGA). A This is part of the present invention, but it is not limited thereto. In some embodiments, at least a portion (e.g., part or all) of the second register 620 may be disposed outside the connection device 600. For example, at least a portion (e.g., part or all) of the second register 620 may be a second field-programmable gate array (FPGA). B This is part of the invention, but the invention is not limited thereto.

[0025] In this embodiment, the first register device 610 is coupled to the first field-programmable gate array (FPGA). Atransmit data DATA from the first field programmable gate array FPGA A in accordance with the first clock (e.g. master clock MASTERCLK) TX which includes the reordered R read pointer, B read pointer, AR load, AW load, W load, AR write pointer, AW write pointer, and W write pointer described above, wherein the transmit data DATA TX may be divided into a plurality of sets of local data. The LVDS serializer / deserializer 630 is coupled between the first register device 610 and the second register device 620, and the LVDS serializer / deserializer 630 can transmit the plurality of sets of local data from the first register device 610 to the second register device 620 at a plurality of time points respectively in accordance with a time division multiplexing clock such as a pixel clock pxclk, wherein the first field programmable gate array FPGA A may transmit the master clock MASTERCLK to the connection device 600, and the connection device 600 can generate the pixel clock pxclk in accordance with the master clock MASTERCLK. For example, the operating frequency of the first field programmable gate array FPGA A (e.g. the frequency of the master clock MASTERCLK) can be in the order of millions of hertz (megahertz, MHz), while the data transmission rate between the transmitter 600TX and the receiver 600RX (e.g. the frequency of the pixel clock pxclk) can be in the order of gigahertz (GHz) level. In addition, the second register device 620 is also coupled to the second field programmable gate array FPGA B , and can sequentially receive the plurality of sets of local data to output the transmit data DATA TX (which includes the reordered R read pointer, B read pointer, AR load, AW load, W load, AR write pointer, AW write pointer, and W write pointer described above) to the second field programmable gate array FPGA B .

[0026] According to the above operation, the first register device 610 can be regarded as an outbound register file, and the second register device 620 can be regarded as an inbound register file, wherein either (e.g. each) of the first register device 610 and the second register device 620 can include a plurality of registers or a plurality of static random access memory (SRAM) cells, but the present application is not limited thereto.

[0027] In addition, each of the plurality of partial data can be transmitted from the first register 610 to the second register 620 along with the corresponding identification code. After the second register 620 receives all of the plurality of partial data, the second register 620 can restore the transmitted data DATA TX .

[0028] For example, the LVDS serializer / deserializer 630 can be an LVDS source synchronous 7:1 serializer / deserializer. Assuming that the cable data width (e.g., the number of wires) of the transmitter 600TX is 40 bits, the data width of the data pxdata received by the LVDS source synchronous 7:1 serializer / deserializer is 70*7 = 280 bits. In this embodiment, the data pxdata can reserve 5 bits as the identification code tdm_id, wherein when tdm_id[4:0] is 0, the data pxdata is regarded as invalid data. Therefore, the maximum data width of the transmitted data DATA TX is (280-5)*(2^5-1) = 8525 bits. Assuming that DATA TX = {w_write_pointer, aw_write_poniter, ar_write_pointer, w_payload, aw_payload, ar_payload, b_read_pointer, r_read_pointer} and the data width of DATA TX is 5000 bits, according to the calculation result of 5000 / (280-5), the LVDS serializer / deserializer 630 can complete the transmission of DATA TX by 19 times of transmission, wherein DATA TX is transmitted from the lowest bit (e.g., from r_read_pointer), and r_read_pointer, b_read_pointer, ar_payload, aw_payload, w_payload, ar_write_pointer, aw_write_poniter and w_write_pointer can represent the data values of the above-mentioned R read pointer, B read pointer, AR load, AW load, W load, AR write pointer, AW write pointer and W write pointer, respectively. Specifically, the master clock MASTERCLK and the pixel clock pxclk are not synchronous, wherein the first register 610 stores the transmitted data DATA TX in all values at the same time, and when the first register 610 has obtained the transmitted data DATA TXstabilized, the first register 610 can send a signal READY to the LVDS serializer / deserializer 630. When the LVDS serializer / deserializer 630 receives the signal READY, the LVDS serializer / deserializer 630 can start to sequentially send each set of local data DATA TX [m:n] to the receiver 600RX (e.g., {tdm_id[4:0], DATA TX [m:n]} from the transmitter 600TX to the receiver 600RX in a time-multiplexed manner) along with an identification code tdm_id[4:0], where m, n are positive integers and m-n=275-1, indicating that each set of local data DATA TX [m:n] can have a data width of 275. For example, in the first cycle of the pixel clock pxclk, pxdata={5'dl, DATA TX [274:0]}; in the second cycle of the pixel clock pxclk, pxdata={5'd2, DATA TX [549:275]}; and so on, in the nineteenth cycle of the pixel clock pxclk, pxdata={5'dl9, 225d'0, DATA TX [4999:4950]}; and where if there is no more data value to be transmitted (e.g., the transmission of data DATA TX is completed), pxdata=280'd0. Thus, the second register 620 can sequentially latch the data pxdata received at the pixel clock pxclk according to the pixel clock pxclk. The x'dy shown above is to represent the decimal value y in x-bit binary value for simplicity.

[0029] According to the above example, the AXI slave (e.g., the second register 620 or the second field programmable logic array FPGA B ) can know how to restore the transmitted data DATA TX from the data pxdata in each cycle of the pixel clock pxclk (e.g., know the arrangement order of the data pxdata in each cycle) according to the identification code carried in the data pxdata in each cycle of the pixel clock pxclk. TX Once the transmission of data DATA AGet the next piece of data that needs to be transmitted.

[0030] In addition, the entire of any one of the at least one read pointer and the at least one write pointer is contained in the same one of the plurality of sets of partial data. For example, any (e.g., each) of the R read pointer, the B read pointer, the AR write pointer, the AW write pointer, and the W write pointer completes transmission within one cycle of the pixel clock pxdata, so the respective data value of any (e.g., each) of the pointers is not split into multiple cycles of the pxdata for transmission. Since each of the pointers is not truncated at the AXI slave end, data transmission errors due to FIFO state update exceptions can be avoided. Moreover, by virtue of the configuration of the above-described transmission sequence (e.g., the configuration of making the transmission time point of the at least one data payload earlier than the transmission time point of the at least one write pointer), it can be ensured that the second register device (e.g., the asynchronous FIFO therein) correctly performs data transfer on the AXI lane.

[0031] In the present embodiment, the maximum number of the plurality of sets of partial data is determined by the number of bits of the corresponding identification code. For example, when the corresponding identification code is N bits, the data DATA TX At most, the data pxdata can be divided into (2ΛN - 1) sets of partial data and the (2ΛN - 1) sets of partial data are sequentially transmitted in (2ΛN - 1) cycles of the pixel clock pxclk. Therefore, the time division multiplexing ratio (TDM ratio) of the LVDS serializer / deserializer 630 also corresponds to the number of bits of the above-described identification code.

[0032] In some embodiments, in addition to the above-described identification code, the data pxdata can reserve one or more bits for a corresponding check code, so each of the plurality of sets of partial data can be transmitted from the first register device to the second register device together with the corresponding check code (e.g., the pxdata transmitted in each cycle of the pixel clock pxclk can include one or more bits for carrying the corresponding check code), and the corresponding check code can be used for error detection, error correction, or data retry operations for each of the sets of partial data.

[0033] In some embodiments, pipe registers can be inserted at any location on the transmission path of the pixel data pxdata (e.g., the path between the transmitter 600TX and the receiver 600RX) to ensure the timing of the overall system without affecting the overall functionality. In addition, the present application uses the AXI bus protocol as an example for illustration purposes only and is not a limitation of the present application. For example, the above-mentioned data transmission mechanisms across the FPGA are applicable to point-to-point transmission protocols such as the open core protocol (OCP) or the advanced microcontroller bus architecture (AMBA).

[0034] Figure 8 A workflow of a method for data transmission control across field programmable gate arrays according to an embodiment of the present application, wherein the workflow can be applied to Figure 6 the apparatus 60 and the connection device 600 therein as shown. It is noted that one or more steps can be added, modified or deleted in the workflow as shown in Figure 8 as long as the overall result is not affected, and the steps do not have to be executed in the order as shown in Figure 8 .

[0035] In step S810, the apparatus 60 can latch a set of data (e.g., the transmission data DATA A ) from the first field programmable gate array FPGA TX according to a first clock (e.g., the master clock MASTERCLK) using the first register device 610, wherein the set of data is sorted according to the load and pointer attributes and divided into a plurality of sets of local data (e.g., the above-mentioned DATA TX [274:0], DATA TX [549:275], …, and DATA TX [4999:4950]).

[0036] In step S820, the apparatus 60 can transmit the plurality of sets of local data from the first register device 610 to the second register device 620 at a plurality of time points (e.g., at a plurality of cycles of the pixel clock pxdata) according to a time division multiplexing clock (e.g., the pixel clock pxclk) using the time division multiplexing interface (e.g., the LVDS serializer / deserializer 630).

[0037] In step S830, the apparatus 60 can sequentially receive the plurality of sets of local data using the second register device 620 to output the set of data to the second field programmable gate array FPGA B , wherein the second field programmable gate array FPGA Boperates according to a second clock different from the first clock.

[0038] In summary, the method and related apparatus provided by embodiments of the present application can completely isolate field programmable gate arrays (FPGAs) in different clock domains by using bus flow control and master-slave mechanism with a source synchronous serializer / deserializer interface having high-speed transmission characteristics. In this way, the FPGAs can operate at their respective optimized frequencies without being affected by the operating frequency and / or time division multiplexing ratio. In particular, by identifying the number of code bits, the common input and output of the FPGAs can have greater flexibility to adapt to an increase in data width. In addition, as long as the mechanism between the master and slave ends of the source synchronous serializer / deserializer interface can be paired, the above transmission control mechanism across the FPGAs can also be applied to chip-to-chip or chip-to-FPGA data transmission. Compared with related art, embodiments of the present application do not significantly increase additional costs. Therefore, the present application can solve the problems of related art without or with less side effects.

[0039] The above merely provides the preferred embodiments of the present application, and any equivalent variation and improvement made according to the claims of the present application shall fall within the scope of the present application.

[0040] Legend of reference signs:

[0041] 10: device

[0042] 100: connection apparatus

[0043] 110, 120, 130, 140, 150: asynchronous FIFO

[0044] FPGA A FPGA B : field programmable gate array

[0045] 111, 141: master end of asynchronous FIFO

[0046] 112, 142: slave end of asynchronous FIFO

[0047] DATA TX DATA RX : data

[0048] 60: device

[0049] 600: connection apparatus

[0050] 600TX: transmitter

[0051] 600RX: receiver

[0052] 610, 620: register means

[0053] 630: LVDS serializer / deserializer

[0054] MASTERCLK: master clock

[0055] pxclk: pixel clock

[0056] pxdata: data

[0057] READY, CAPTURE: signals

[0058] S810, S820, S830: steps

Claims

1. A method for data transfer control across field programmable logic arrays, comprising: latching a set of data from a first field programmable logic array according to a first clock using a first register device, wherein the set of data is ordered and divided into a plurality of partial data sets according to load and pointer attributes; transferring the plurality of partial data sets from the first register device to a second register device sequentially at a plurality of time points according to a time division multiplexing clock using a time division multiplexing interface; and receiving the plurality of partial data sets sequentially using the second register device to output the set of data to a second field programmable logic array, wherein the second field programmable logic array operates according to a second clock different from the first clock; wherein data transfer between the first field programmable logic array and the second field programmable logic array comprises a plurality of channel types corresponding to at least two of address read, address write, write, read, and response channels, each channel type of the plurality of channel types comprises transmission of data in two directions, and the set of data is generated by arranging data in the same direction in the plurality of channel types.

2. The method of claim 1, wherein the set of data is differentiated by attributes comprising at least one read pointer, at least one load, or at least one write pointer.

3. The method of claim 2, wherein the entirety of either the at least one read pointer or the at least one write pointer is contained in the same partial data set of the plurality of partial data sets.

4. The method of claim 2, wherein the at least one load is transferred from the first register device to the second register device at an earlier time point than the at least one write pointer is transferred from the first register device to the second register device.

5. The method of claim 4, wherein the at least one read pointer is transferred from the first register device to the second register device at an earlier time point than the at least one load is transferred from the first register device to the second register device.

6. The method of claim 1, wherein each partial data set of the plurality of partial data sets is transferred from the first register device to the second register device along with a corresponding identification code, and upon receiving all of the plurality of partial data sets at the second register device, the second register device restores the set of data according to the corresponding identification codes.

7. The method of claim 6, wherein a maximum number of partial data sets of the plurality of partial data sets is determined by a number of bits of the corresponding identification codes.

8. The method of claim 1, wherein each partial data set of the plurality of partial data sets is transferred from the first register device to the second register device along with a corresponding check code, and the corresponding check code is used for error detection, error correction, or data retransmission operations of the each partial data set.

9. An apparatus for emulation of an electronic system, comprising: a first field programmable gate array for simulation of a first subsystem of the electronic system, wherein the first field programmable gate array operates according to a first clock; a second field programmable gate array for simulation of a second subsystem of the electronic system, wherein the second field programmable gate array operates according to a second clock different from the first clock; a first register device coupled to the first field programmable gate array; a second register device coupled to the second field programmable gate array; a time-multiplexed interface coupled between the first register device and the second register device; wherein the first register device latches a set of data from the first field programmable gate array according to the first clock; the set of data is sorted according to load and pointer attributes and divided into a plurality of local data sets to allow the time-multiplexed interface to transfer the plurality of local data sets from the first register device to the second register device sequentially at a plurality of time points according to a time-multiplexed clock; and the second register device sequentially receives the plurality of local data sets to output the set of data to the second field programmable gate array; wherein data transfer between the first field programmable gate array and the second field programmable gate array includes a plurality of channel types, the plurality of channel types respectively corresponding to at least two of address read, address write, write, read, and response channels, each channel type of the plurality of channel types including transfer of data in two directions, and the set of data is generated by arranging data in the same direction in the plurality of channel types.

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