Contact Hole Manufacturing Method and Semiconductor Device Manufacturing Method

Abstract

The present invention provides a method for manufacturing a contact hole and a method for manufacturing a semiconductor device, which cover an insulating dielectric layer with a certain thickness on the top surface of a first conductive structure, and fill a sacrificial layer in the space between the first conductive structures. Thus, after etching an opening in the interlayer dielectric layer to form an upper opening of the contact hole, the sacrificial layer is removed to form a lower opening of the contact hole for alignment, reducing the requirement for the alignment accuracy of the contact hole, and further reducing the process difficulty of manufacturing the contact hole.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and particularly relates to a method for manufacturing a contact hole and a method for manufacturing a semiconductor device. Background Art

[0002] In the fabrication of semiconductor integrated circuits, it is usually necessary to fabricate various electronic devices required by the circuit on a small area of a silicon wafer, and it is also necessary to fabricate appropriate interconnecting lines to electrically connect between the electronic devices to achieve the desired functions. This requires fabricating a large number of contact holes on the silicon wafer, and the performance of these contact holes has an important impact on the overall performance of the circuit.

[0003] With the development of very large scale integrated circuits, the number of electronic devices in the circuit is continuously increasing, and the device size (cell pitch) is continuously decreasing. Among them, the continuous reduction of the device size, on the one hand, puts higher requirements on the lithography critical dimension (CD) and alignment accuracy of the contact hole, and on the other hand, due to the increase in device density, the distance between the contact hole and other conductive structures is reduced. When the lithography alignment deviation is too large, it is very likely to cause device short circuit. In addition, the aspect ratio of the contact hole becomes larger, which is not conducive to the filling of the contact hole. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for manufacturing a contact hole and a method for manufacturing a semiconductor device, which can reduce the process difficulty of manufacturing the contact hole and achieve self-alignment of the contact hole.

[0005] To achieve the above purpose, the present invention provides a method for manufacturing a contact hole, which includes:

[0006] Providing a substrate, on which at least two spaced-apart first conductive structures are formed, an insulating dielectric layer is covered on the top surface of the first conductive structures, and a second conductive structure is formed in the substrate at the interval between adjacent first conductive structures;

[0007] Forming sidewalls on the inner sidewalls of the interval, and the sidewalls cover the sidewalls of the first conductive structures and the insulating dielectric layer;

[0008] Filling a sacrificial layer in the interval, and forming an interlayer dielectric layer covering the sacrificial layer, the insulating dielectric layer, and the sidewalls;

[0009] Etching the interlayer dielectric layer at the interval, and the etching stops at the top surface of the sacrificial layer to form an opening exposing the top surface of the sacrificial layer;

[0010] Removing the sacrificial layer in the bottom region of the opening to form a contact hole exposing the top surface of the second conductive structure at the interval.

[0011] Optionally, the first conductive structure includes a gate; the second conductive structure includes an ion-doped region formed in the substrate at the interval, and the contact hole exposes a partial top surface of the ion-doped region.

[0012] Optionally, the ion-doped region includes a body region formed in the substrate at the interval and a source region formed in the surface layer of the body region, and the contact hole exposes a partial top surface of the source region and the top surface of the body region between adjacent source regions.

[0013] Optionally, the steps of forming the first conductive structure and the second conductive structure include:

[0014] Sequentially covering a gate dielectric layer, a gate layer, and an insulating dielectric layer on the substrate;

[0015] Etching the insulating dielectric layer and the gate layer to form a gate with the insulating dielectric layer covering the top surface;

[0016] Performing body region ion implantation into the substrate at the interval to form a body region;

[0017] Forming a source region in the surface layer of the body region through corresponding photolithography and source region ion implantation.

[0018] Optionally, at least one of the first conductive structure and the second conductive structure is a polysilicon resistor, a plate of a capacitor, a conductive plug, or a metal interconnection line in a multi-layer metal interconnection structure.

[0019] Optionally, the top surface of the sacrificial layer is higher than the top surface of the first conductive structure and lower than the top surface of the insulating dielectric layer; when etching the interlayer dielectric layer at the interval and stopping at the top surface of the sacrificial layer, part of the insulating dielectric layer and the sidewall are also removed, so that the line width of the opening is greater than the line width of the top surface of the sacrificial layer, and the sidewall of the insulating dielectric layer forms a step in the opening that does not expose the top surface of the first conductive structure.

[0020] Optionally, the sacrificial layer in the bottom region of the opening is removed through a wet etching process, and the contact hole has an upper-wide and lower-narrow structure.

[0021] Optionally, after removing the sacrificial layer in the bottom region of the opening to form a contact hole, it further includes: etching a partial thickness of the substrate below the bottom of the contact hole so that the bottom of the contact hole penetrates into the corresponding thickness of the ion-doped region.

[0022] Based on the same inventive concept, the present invention further provides a method for manufacturing a semiconductor device, which includes:

[0023] Adopting the contact hole manufacturing method of the present invention to form a corresponding contact hole;

[0024] Fill the contact hole with a conductive material.

[0025] Optionally, the semiconductor device to be manufactured is an IGBT or a MOS transistor. The first conductive structure includes a gate, and the second conductive structure includes a source region. The step of filling the contact hole with a conductive material includes: depositing a metal layer, where the metal fills the contact hole and is deposited with a corresponding thickness above the insulating dielectric layer; performing photolithography and etching on the metal layer to form a source metal wire for electrically leading out the source region outward.

[0026] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0027] 1. It can be compatible with the existing process, can form contact holes in a self-aligned manner, and has a lower requirement for the alignment accuracy of the contact holes;

[0028] 2. The distance between the contact hole and the first conductive structure can be controlled by the sidewall and the insulating dielectric layer as needed;

[0029] 3. Through the sacrificial layer and the insulating dielectric layer on the top surface of the first conductive structure, the first conductive structure is protected during the opening process, and it is beneficial to form an inverted trapezoidal contact hole morphology with a wider top and a narrower bottom, reducing the aspect ratio of the contact hole, and thus facilitating the filling of the material in the contact hole. Description of the Drawings

[0030] Figure 1 It is a schematic cross-sectional structure diagram of a device under the existing contact hole process.

[0031] Figure 2 A schematic flow diagram of the contact hole manufacturing method according to an embodiment of the present invention.

[0032] Figure 3 It is a schematic cross-sectional structure diagram in the contact hole manufacturing method and the semiconductor device manufacturing method according to a specific embodiment of the present invention.

[0033] Figure 4 It is a schematic cross-sectional structure diagram in the contact hole manufacturing method and the semiconductor device manufacturing method according to another embodiment of the present invention. Detailed Embodiments

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention. It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when a layer is referred to as being "formed on" another layer, it can be directly formed on the other layer or intervening layers may be present. Herein, the terms "upper", "lower", "top", "bottom", "inner", "middle", "longitudinal", "lateral", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and thus should not be construed as a limitation of the present invention. Herein, "longitudinal" can be understood as the direction perpendicular to the surface of the substrate, and "lateral" can be understood as the direction parallel to the surface of the substrate. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items. The terms "same", "equal" and "identical" include the meanings of exactly equal and exactly the same, and may also include the meanings of approximately the same or approximately equal within the allowable process errors. In the specification, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological order. It is to be understood that, where appropriate, these terms may be interchanged such that the embodiments of the present invention described herein can be operated in an order different from that described herein or shown herein. Similarly, if the methods described herein include a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be executed, and some of the described steps may be omitted and / or some other steps not described herein may be added to the method. If a component in a certain drawing is the same as a component in other drawings, although these components can be easily recognized in all the drawings, for the sake of clarity in the description of the drawings, the present specification will not label the reference numerals of all the same components in each drawing.

[0035] As described in the background art, there are defects in the existing contact hole manufacturing process.

[0036] Taking the manufacturing of planar devices such as IGBTs and MOS transistors as an example, in the prior art, please refer to Figure 1 , usually after the etching of the polysilicon gate (i.e., the first conductive structure) 101, the fabrication of the gate sidewall 102, and the ion implantation of the source region (i.e., the second conductive structure) 103, the fabrication of the source contact hole (contact via) 105 is usually completed through the deposition, photolithography, and etching of the interlayer dielectric layer 104. Further, a metal 106 is filled in the contact hole 105 to form a conductive plug or a metal wire (or called an interconnect line) that electrically leads out the source region 103 outward.

[0037] As the device size continues to shrink and the device density continues to increase, on the one hand, higher requirements are imposed on the lithography critical dimension (CD) of the contact hole and the alignment accuracy. On the other hand, due to the increase in device density, the distance between the contact hole and the polysilicon gate is reduced, and the lithography misalignment will have a greater impact on the device threshold voltage, resulting in more prone current concentration and burnout during the use of devices such as IGBTs and MOS transistors, seriously affecting the actual use of these devices. Moreover, when the lithography misalignment is too large, it will even directly cause a short circuit between the gate and the source / drain of the MOS transistor or between the gate and the emitter of the IGBT.

[0038] Of course, similar problems as above also exist in the manufacturing of contact holes in multi-layer metal interconnect structures or other semiconductor devices.

[0039] Based on this, the present invention provides a method for manufacturing a contact hole and a method for manufacturing a semiconductor device. An insulating dielectric layer with a certain thickness is covered on the top surface of the first conductive structure, so that when etching the interlayer dielectric layer to form a contact hole, a step can be formed to increase the opening size of the upper part of the contact hole, and a sacrificial layer is used to form the lower opening of the self-aligned contact hole, which can achieve the self-alignment of the contact hole and reduce the requirements for the CD and alignment accuracy of the contact hole.

[0040] The technical solutions proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0041] Please refer to Figure 2 , an embodiment of the present invention provides a method for manufacturing a contact hole, which includes:

[0042] S1, providing a substrate, on the surface of the substrate, at least two spaced-apart first conductive structures are formed, an insulating dielectric layer is covered on the top surface of the first conductive structure, and a second conductive structure is formed in the substrate at the interval between adjacent first conductive structures;

[0043] S2. Form sidewalls on the inner sidewalls of the interval, and the sidewalls cover the sidewalls of the first conductive structure and the insulating dielectric layer;

[0044] S3. Fill the interval with a sacrificial layer, and form an interlayer dielectric layer covering the sacrificial layer, the insulating dielectric layer, and the sidewalls;

[0045] S4. Etch the interlayer dielectric layer at the interval, and stop the etching at the top surface of the sacrificial layer to form an opening exposing the top surface of the sacrificial layer;

[0046] S5. Remove the sacrificial layer in the bottom region of the opening to form a contact hole exposing the top surface of the second conductive structure at the interval.

[0047] Please refer to Figure 3 , in this embodiment, the substrate 200 provided in step S1 is any suitable semiconductor substrate for manufacturing devices such as IGBTs or MOS transistors. It can be a bare silicon wafer or a silicon wafer after certain process processing, etc. For example, fins or shallow trench isolation structures (STIs) have been formed in the substrate 200.

[0048] As an example, the implementation process of step S1 specifically includes:

[0049] First, please refer to Figure 3 in (A), sequentially cover a gate dielectric layer 201, a gate layer, and an insulating dielectric layer 203 on the substrate 200. Among them, the material of the gate dielectric layer 201 can include silicon oxide or high-k (for example, a dielectric constant k greater than 7) dielectric, etc., which can be formed by thermal oxidation process, chemical vapor deposition process, or atomic layer vapor deposition process, etc. The material of the gate layer can include polysilicon and / or metal, etc., which can be formed by chemical vapor deposition process, etc. The material of the insulating dielectric layer 203 can include silicon nitride and / or silicon oxide, etc. The deposition thickness of the insulating dielectric layer 203 needs to be reasonably selected to increase the height of the subsequent sacrificial layer while ensuring that the required steps are formed on the sidewalls of the insulating dielectric layer after etching the interlayer dielectric layer to form an opening and avoiding the steps from exposing the top surface of the gate.

[0050] Next, please continue to refer to Figure 3 in (A), etch the insulating dielectric layer 203 and the gate layer, and stop the etching at the gate dielectric layer 201 to form a plurality of gates 202 spaced apart from each other and having an insulating dielectric layer 203 covering their top surfaces. The gates 202 serve as at least two spaced-apart first conductive structures formed on the surface of the substrate 200.

[0051] Then, please refer to Figure 3In (B) thereof, a body region ion implantation is performed into the substrate 200 at the interval 204 between adjacent gates 202, and an annealing treatment is carried out to form a body region 200p. Among them, the implanted ions can be at least one p-type ion such as boron, indium, gallium, etc. The body region 200p can laterally extend under a part of the bottom of the gate 202 to overlap with the gate 202.

[0052] After that, through corresponding photolithography, source region ion implantation and annealing treatment, source regions 200s corresponding to the gates 202 one by one are formed in the surface layer of the body region 200p. In this embodiment, two mutually separated source regions 200s corresponding to the gates 202 on both sides are formed in the interval 204, and each source region 200s extends under a part of the bottom of the corresponding gate 202 to overlap with the corresponding gate 202 in the vertical direction. The source region 200s, as the second conductive structure formed in the substrate 200 at the interval 204 between adjacent gates 202, and the body region 200p and the source region 200s together form an ion-doped region formed in the substrate 200 at the interval 204.

[0053] Please refer to Figure 3 In (C) thereof, in step S2, a sidewall material such as silicon oxide is deposited, and the sidewall material is etched to form a sidewall 205 covering the inner sidewall of the interval 204. The sidewall 205 can be a single-layer film structure or a composite structure of a multi-layer film stack. The thickness of the sidewall 205 is adjusted according to the actual requirements of the bottom line width of the contact hole to be formed and the distance between the formed contact hole and the gate 202.

[0054] In step S3, first, please refer to Figure 3 In (D) thereof, a sacrificial layer 206 can be formed to cover the top surface of the insulating dielectric layer 203 and fill the interval 204 through processes such as chemical vapor deposition or spin coating, so as to bury the insulating dielectric layer 203, the interval 204, and the sidewall 205. The material of the sacrificial layer 206 can be selected from any suitable material different from the insulating dielectric layer 203 and the sidewall 205. For example, when the materials of the insulating dielectric layer 203 and the sidewall 205 are both silicon oxide, the sacrificial layer 206 can be silicon nitride. Then, please continue to refer to Figure 3 In (D) thereof, the sacrificial layer 206 is etched back until the top surface of the sacrificial layer 206 is lower than the top surface of the insulating dielectric layer 203 and higher than the top surface of the gate 202, thereby removing the sacrificial layer 206 on the top surface of the insulating dielectric layer 203, so that the remaining sacrificial layer 206 is only located in the interval 204. Then, please refer to Figure 3In (E), an interlayer dielectric layer 207 is deposited. Optionally, the top surface of the deposited interlayer dielectric layer 207 can be further subjected to chemical mechanical polishing until the top surface of the interlayer dielectric layer 207 is flat, and the polished interlayer dielectric layer 207 still buries the tops of the insulating dielectric layer 203, the sidewall 205, and the sacrificial layer 206 therein.

[0055] Please refer to Figure 3 In (F), in step S4, a conventional contact hole process is used to perform photolithography and etching on the interlayer dielectric layer 207 until the top surface of the sacrificial layer 206 is exposed, forming an opening 208a. In this step, a part of the edge of the insulating dielectric layer 203 at the spacer 204 and the top of a part of the thickness of the sidewall 205 can be etched away together, so that the line width of the formed opening 208a can be greater than the line width of the spacer 204 (i.e., greater than the top line width of the sacrificial layer 206), and further the opening 208a can expose a part of the surface of the insulating dielectric layer 203 and the top surface of the sidewall 205. A step 207a where the sidewall of the insulating dielectric layer 203 does not expose the top surface of the gate 202 is formed in the opening 208a.

[0056] Optionally, the opening 208a is an inverted trapezoidal structure with a wider top and a narrower bottom to facilitate subsequent processes.

[0057] Please refer to Figure 3 In (G), in step S5, the sacrificial layer 206 in the bottom region of the opening 208a can be removed by a wet etching process to form a contact hole 208, and the formed contact hole 208 has a structure with a wider top and a narrower bottom.

[0058] Optionally, in step S5, the gate dielectric layer 201 below the bottom of the contact hole 208 is further etched along the contact hole 208, and a part of the thickness of the substrate 200 (i.e., a part of the thickness of the source region 200s and the body region 200p between the source regions 200s) is continuously etched away, so that the bottom of the contact hole 208 penetrates into the corresponding thickness of the body region 200p and the source region 200s. That is to say, the contact hole 208 exposes a part of the top surface of the source region 200s and at the same time exposes the top surface of the body region 200p between the source regions 200s. Moreover, the distance between the contact hole 208 and the gate 202 is controlled by the thickness of the sidewall and the insulating dielectric layer.

[0059] In this embodiment, firstly, with the assistance of pre-filling and subsequent removal of the sacrificial layer 206, on the one hand, the process of etching the interlayer dielectric layer to form a contact hole with a large aspect ratio is divided into the etching of the opening 208a in the interlayer dielectric layer 207 and the removal of the sacrificial layer 206. The aspect ratios of the two processes are reduced, which is beneficial to improving the morphology of the finally formed contact hole. On the other hand, by removing the sacrificial layer 206 and under the confinement of the sidewall 205, the contact hole 208 can be formed self-alignedly, greatly reducing the alignment accuracy requirements for the contact hole 208. In addition, on the basis that the line width of the sacrificial layer 206 meets the bottom line width requirement of the contact hole 208, the line width of the opening 208a in the interlayer dielectric layer 207 can be made larger, so that the contact hole 208 is in an inverted trapezoid shape with a wider top and a narrower bottom, thereby being able to minimize the aspect ratio of the contact hole 208, which is beneficial to the subsequent material filling in the contact hole 208.

[0060] Please refer to Figure 2 and Figure 3 , this embodiment also provides a method for manufacturing a semiconductor device, which includes:

[0061] Firstly, use the contact hole manufacturing method described in the present invention (i.e., steps S1 to S5) to form the corresponding contact hole 208. The specific process can be referred to the above description and will not be elaborated here;

[0062] Then, please refer specifically to Figure 3 in (H), and fill the conductive material 209 into the contact hole 208. For example, first form a metal silicide on the bottom surface of the contact hole 208 to reduce the contact resistance, and then sequentially deposit a thinner metal barrier material, a thinner adhesion layer or seed layer material, and then deposit a thicker metal layer material until it can fill the contact hole 208 and can cover the required thickness on the top surface of the interlayer dielectric layer 207, and further perform chemical mechanical polishing, thereby forming a conductive material 209 with a flat top surface. When the top surface of the conductive material 209 is chemically mechanically polished to be flush with the top surface of the interlayer dielectric layer 207, the conductive material 209 serves as a conductive plug filled in the contact hole 208. When the top surface of the conductive material 209 still has a certain covering thickness on the top surface of the interlayer dielectric layer 207 after chemical mechanical polishing, the conductive material 209 can be further lithographed and etched to form the required metal line, and the metal line is electrically connected to the source region 200s through the part filled in the contact hole 208.

[0063] Optionally, the semiconductor device to be fabricated is an IGBT, MOS transistor, etc. The first conductive structure includes a gate, and the second conductive structure includes a source region. The step of filling the contact hole with a conductive material includes: depositing a metal layer, where the metal fills the contact hole and a corresponding thickness is deposited above the gate; performing photolithography and etching on the metal layer to form a source metal wire for electrically leading out the source region outward.

[0064] Moreover, in the semiconductor device manufacturing method of this embodiment, due to the adoption of the contact hole manufacturing process of the present invention, it can avoid the problem of lithography misalignment caused by the increase in device density, the reduction in device size, and the reduction in the distance between the contact hole and the gate in the prior art. Thus, it can avoid the problem of a larger fluctuation range of the threshold voltage caused by the offset of the contact hole, and further avoid the problem that the device is more likely to have current concentration during use, resulting in burnout or short circuit, enhancing the reliability of the device.

[0065] It should be noted that in the above embodiment, taking the first conductive structure as the gate and the second conductive structure as a combination of the source region and the body region as an example for illustration, however, the technical solution of the present invention is not limited thereto, and it can be used in any suitable process that requires the fabrication of contact holes.

[0066] For example, please refer to Figure 4 , in other embodiments of the present invention, the substrate 200 is a substrate that has entered the back-end interconnect process. The first conductive structure formed on its surface is a certain intermediate layer metal interconnect line in the multi-layer metal interconnect structure, and the second conductive structure 200s is a lower layer metal interconnect line or a conductive plug in the multi-layer metal interconnect structure. At this time, the contact hole 208 filled with the conductive material 209 is used to electrically connect the second conductive structure 200s and the upper layer metal interconnect line and other structures above the first conductive structure.

[0067] For another example, in other embodiments of the present invention, the first conductive structure is a polysilicon resistor or a capacitor plate, etc., and the second conductive structure is a gate, source region, or drain region of a transistor, etc.

[0068] In addition, the technical solution of the present invention is not limited to the application in the fabrication of IGBT or MOS transistor devices. It can also be applied to other any suitable devices that require the fabrication of contact holes. For example, it can be applied to the fabrication of CIS devices to achieve self-alignment of the contact holes of CIS devices, so as to solve the problem that the reduction in the pixel unit size of CIS devices causes damage to the device structure during the self-alignment etching process of the contact holes, and improve the reliability of device performance. For another example, it can be applied to the fabrication of memories to achieve self-alignment of the contact holes of memory cells, so as to solve the problem that the reduction in the size of memory cells causes damage to the device structure during the self-alignment etching process of the contact holes, and improve the reliability of device performance.

[0069] In summary, the method for manufacturing a contact hole and the method for manufacturing a semiconductor device provided by the present invention cover an insulating dielectric layer with a certain thickness on the top surface of the first conductive structure, and fill a sacrificial layer in the gap between the first conductive structures. Thus, after etching the interlayer dielectric layer to form an opening as the upper opening of the contact hole, the sacrificial layer is removed to form the lower opening of the contact hole from alignment, reducing the requirement for the alignment accuracy of the contact hole, and further reducing the process difficulty of manufacturing the contact hole.

[0070] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a contact hole, characterized in that, Comprising: Providing a substrate, on which at least two spaced-apart first conductive structures are formed, an insulating dielectric layer is covered on the top surface of the first conductive structures, and a second conductive structure is formed in the substrate at the interval between adjacent first conductive structures; Forming sidewalls on the inner sidewalls of the interval, the sidewalls covering the sidewalls of the first conductive structures and the insulating dielectric layer; Filling a sacrificial layer in the interval, the top surface of the sacrificial layer being higher than the top surface of the first conductive structures and lower than the top surface of the insulating dielectric layer, and forming an interlayer dielectric layer covering the sacrificial layer, the insulating dielectric layer and the sidewalls; Etching the interlayer dielectric layer at the interval, and stopping the etching at the top surface of the sacrificial layer to form an opening exposing the top surface of the sacrificial layer; Removing the sacrificial layer in the bottom region of the opening by a wet etching process to self-alignedly form a contact hole exposing the top surface of the second conductive structure at the interval; 2. The contact hole manufacturing method according to claim 1, characterized in that, The first conductive structure includes a gate; the second conductive structure includes an ion-doped region formed in the substrate at the interval, and the contact hole exposes a partial top surface of the ion-doped region; 3. The contact hole manufacturing method according to claim 2, characterized in that, The ion-doped region includes a body region formed in the substrate at the interval and a source region formed in the surface layer of the body region, and the contact hole exposes a partial top surface of the source region and the top surface of the body region between adjacent source regions; 4. The contact hole manufacturing method according to claim 3, wherein The steps of forming the first conductive structure and the second conductive structure include: Sequentially covering a gate dielectric layer, a gate layer, and an insulating dielectric layer on the substrate; Etching the insulating dielectric layer and the gate layer to form a gate with the insulating dielectric layer covered on its top surface; Performing body region ion implantation into the substrate at the interval to form a body region; Forming a source region in the surface layer of the body region by corresponding photolithography and source region ion implantation; 5. The contact hole manufacturing method according to claim 1, characterized in that At least one of the first conductive structure and the second conductive structure is a polysilicon resistor, a plate of a capacitor, a conductive plug, or a metal interconnection line in a multi-layer metal interconnection structure; 6. The contact hole manufacturing method according to any one of claims 1-5, characterized in that, When etching the interlayer dielectric layer at the interval and stopping at the top surface of the sacrificial layer, part of the insulating dielectric layer and the sidewalls are also removed, so that the line width of the opening is greater than the line width of the top surface of the sacrificial layer, and the sidewall of the insulating dielectric layer forms a step in the opening that does not expose the top surface of the first conductive structure; 7. The contact hole manufacturing method according to claim 6, characterized in that, The contact hole has a structure that is wider at the top and narrower at the bottom; 8. The contact hole manufacturing method according to claim 2, characterized in that, After removing the sacrificial layer in the bottom region of the opening to form a contact hole, it further includes: etching a partial thickness of the substrate below the bottom of the contact hole so that the bottom of the contact hole penetrates into the corresponding thickness of the ion-doped region; 9. A method for manufacturing a semiconductor device, characterized in that, Comprising: Adopting the contact hole manufacturing method according to any one of claims 1-8 to form a corresponding contact hole; Filling a conductive material into the contact hole.

10. The method for manufacturing a semiconductor device according to claim 9, wherein, The semiconductor device to be fabricated is an IGBT or a MOS transistor. The first conductive structure includes a gate, and the second conductive structure includes a source region. The step of filling the contact hole with a conductive material includes: depositing a metal layer, where the metal fills the contact hole and is deposited with a corresponding thickness above the insulating dielectric layer; performing photolithography and etching on the metal layer to form a source metal wire for electrically leading out the source region outward.

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