A frequency adjustable CFT control circuit

Abstract

A frequency-adjustable CFT control circuit, characterized in that: the CFT control circuit is used in a DCDC converter to control a PWM unit, and the circuit includes an on-time control unit, an off-time control unit, and an RS trigger; wherein the on-time control unit is used to trigger a high-level signal of the PWM unit to turn on the high-end power tube of the DCDC converter; the off-time control unit realizes a fixed frequency or variable frequency mode of the DCDC converter based on the output voltage limit of the DCDC converter, and triggers a low-level signal of the PWM unit to turn off the low-end power tube of the DCDC converter. The circuit structure of the present invention is simple, the conception is ingenious, and it is fully adapted to the DCDC converter in the prior art. The parameters can be adjusted to a high level, so that the output voltage of the DCDC converter is sufficiently stable.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more specifically, to a frequency-adjustable CFT control circuit. Background Art

[0002] DCDC (Direct Current Direct Current) converters are widely used in electronic products such as mobile phones, MP3, digital cameras, portable media players, etc. as an electronic device that can transform input voltage and effectively fix output voltage. Generally speaking, DCDC converters can be divided into three categories: BOOST boost type, BUCK buck type, and buck-boost type. According to the different control methods of high and low power tube voltages of the converter, DCDC converters can also include different control types such as PWM (Pulse Width Modulation) and PFM (Pulse Frequency Modulation). Among them, the PWM control type has been the most widely used due to its high efficiency and high output voltage signal-to-noise ratio.

[0003] For the control of PWM circuits, the prior art often includes voltage mode, peak current mode, constant on-time (COT) mode, constant off-time (CFT) mode, etc. Among them, the constant off-time mode can cooperate with the Turbo mode (with multiple cycles as intervals, using PWM signals to control the high-end power tube in part of the interval time, shielding the PWM signal and always turning off the high-end power tube in the remaining interval time, and realizing Turbo at multiple intervals, so as to keep the inductor current in a low range and the output power is relatively stable), so that the DCDC converter has good transient response and high frequency stability. In addition, by controlling PWM through the minimum off-time, it can also ensure that PWM is reasonably reduced in frequency when the duty cycle is too large, thereby ensuring stable output voltage.

[0004] However, this circuit still has some problems. For example, when the output voltage required by the subsequent load is small, since the frequency stability of CFT is relatively high and the realization of duty cycle is also limited by the PWM unit circuit, when the duty cycle is extremely small, even if the Turbo mode is used, the output voltage will still drift high. This will make it difficult for the output voltage of the DCDC converter to meet the needs of the subsequent load, causing the subsequent load circuit to malfunction.

[0005] In view of the above problems, the present invention provides a frequency-adjustable CFT control circuit. Summary of the invention

[0006] In order to solve the deficiencies in the prior art, the purpose of the present invention is to provide a frequency-adjustable CFT control circuit, which controls the turn-off delay of the power tube through two different AC small signal elements, so that the slope of the turn-off delay voltage can be adjusted, thereby realizing the CFT control circuit to achieve stable voltage output in two different states of fixed frequency and variable frequency.

[0007] The present invention adopts the following technical solution.

[0008] A first aspect of the present invention relates to a frequency-adjustable CFT control circuit, wherein the CFT control circuit is used in a DCDC converter to control a PWM unit, and the circuit includes an on-time control unit, an off-time control unit, and an RS trigger; the on-time control unit is used to trigger a high-level signal of the PWM unit to turn on a high-end power tube of the DCDC converter; the off-time control unit realizes a fixed frequency or variable frequency mode of the DCDC converter based on an output voltage limit of the DCDC converter, and triggers a low-level signal of the PWM unit to turn off a low-end power tube of the DCDC converter.

[0009] Preferably, the on-time control unit controls the RS trigger to generate a low-level signal based on the inductor peak current and the minimum on-time to achieve the conduction of the high-end power tube.

[0010] Preferably, the off-time control unit controls the RS trigger to generate a high-level signal based on the duty delay and the minimum off-time to turn off the high-end power tube.

[0011] Preferably, the duty delay is generated based on a duty delay generating unit; and the duty delay generating unit includes a reference voltage generating unit, a slope voltage generating unit, and a first comparing unit; wherein the reference voltage generating unit is used to generate a reference voltage; the slope voltage generating unit is used to start outputting a gradually increasing slope voltage and start the duty delay timing when the output signal of the RS trigger switches to a low level signal; the first comparing unit is used to compare the reference voltage of the reference voltage generating unit and the slope voltage of the slope voltage generating unit, and output a duty delay end signal when the slope voltage rises to the reference voltage.

[0012] Preferably, the reference voltage generating unit includes a first AC small signal element, a second AC small signal element, and a shunt resistor; the first AC small signal element and the second AC small signal element are connected in series in sequence and connected between the power supply voltage and the ground potential; the shunt resistor is connected in parallel at both ends of the second AC small signal element.

[0013] Preferably, the output current of the first AC small signal element is g m1 ·V in , the output current of the second AC small signal element is gm1 ·V out ; Among them, g m1 is the transconductance of the first AC small signal element and the second AC small signal element, V in and V out They are the input voltage and output voltage of the DCDC converter respectively.

[0014] Preferably, the slope voltage generating unit includes a third AC small signal element, a fourth AC small signal element, a slope capacitor, a switch element and a second comparison unit; wherein, one end of the third AC small signal element and the fourth AC small signal element is connected to the power supply voltage, and the other end is connected to the second comparison unit, and the second comparison unit outputs the smaller output current of the third AC small signal element and the fourth AC small signal element; after the slope capacitor is connected in parallel with the switch element, one end is connected to the output end of the second comparison unit, and the other end is grounded; the conduction and shutdown of the switch element are controlled based on the output signal of the RS trigger.

[0015] Preferably, the output current of the third AC small signal element is g m3 ·V in , the output current of the fourth AC small signal element is g m4 ·V out ; wherein the fourth AC small signal element is a circuit composed of one or more small signal elements; and, g m3 and g m4 are the transconductance of the third AC small signal element and the fourth AC small signal element, V in and V out They are the input voltage and output voltage of the DCDC converter respectively.

[0016] Preferably, the positive phase input terminal of the first comparison unit is connected to the upper plate of the slope capacitor, and the negative phase input terminal is connected to the reference voltage.

[0017] Preferably, when the duty cycle of the DCDC converter is greater than g m3 / g m4 When the DCDC converter is in fixed frequency operation mode, the duty delay is (1-D)·T, and the frequency of the DCDC converter is When the duty cycle of the DCDC converter is less than g m3 / g m4 When the DCDC converter is in variable frequency operation mode, the duty delay is The frequency of the DCDC converter is

[0018] The beneficial effect of the present invention is that, compared with the prior art, the frequency-adjustable CFT control circuit in the present invention can control the turn-off delay of the power tube through two different AC small signal elements, so that the slope of the turn-off delay voltage can be adjusted, thereby realizing the stable voltage output of the CFT control circuit in two different states of fixed frequency and variable frequency. The circuit structure of the present invention is simple, the design is ingenious, and it is fully adapted to the DCDC converter in the prior art. The parameters are highly adjustable, so that the output voltage of the DCDC converter is sufficiently stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A DCDC converter in the prior art;

[0020] Figure 2 A CFT control circuit in the prior art;

[0021] Figure 3 It is a circuit structure diagram of a duty delay generating unit in a CFT control circuit in the prior art;

[0022] Figure 4 The present invention is a schematic diagram of the circuit structure of a station-controlled delay generating unit in a frequency-adjustable CFT control circuit. DETAILED DESCRIPTION

[0023] The present application is further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present application.

[0024] Figure 1 It is a DCDC converter in the prior art. Figure 1 As shown, a commonly used step-down DCDC converter in the prior art includes a high-end power tube S1 and a low-end power tube S2. The two power tubes are turned on or off in an alternating cycle, so that the inductor current fluctuates and the output voltage is stable to provide power for the subsequent load.

[0025] Figure 2 It is a CFT control circuit in the prior art. Figure 2 As shown, the CFT control circuit in the prior art can be applied to Figure 1 The CFT control circuit includes an on-time control unit, an off-time control unit and an RS trigger.

[0026] Among them, the on-time control unit is based on the inductor peak current I output by the error amplifier EA. peak and minimum on-time minT on To control the turn-on time of the high-end power tube, and the off-time control unit is based on the minimum off-time minToff The high-end power tube can be turned off by the duty delay OFFTIME. Through the RS trigger, the signals of the above two units can be input into the PWM unit, so as to control the state of the high-end power tube and the low-end power tube through PWM.

[0027] Figure 3 FIG. 1 is a circuit structure diagram of a duty delay generating unit in a CFT control circuit in the prior art. Figure 3 As shown, the prior art uses this AC small signal element to achieve Figure 2 The OFFTIME module, that is, the output of the delay end time signal of the duty delay generating unit.

[0028] Specifically, the element represented by the current source form in the figure is an AC small signal element, and the most commonly used one may be a bipolar transistor (BJT, Bipolar Junction Transistor) and the like.

[0029] The transconductance of such a component can be expressed as Figure 3 g in m1 and g m3 To represent respectively, the input voltage of other components can be respectively Figure 3 The input voltage of the DCDC converter is V in and output voltage V out Therefore, for this type of small AC signal, the output current can be expressed as g m1 ·V in , g m1 ·V out and g m3 ·V in . Figure 3 The resistor R in the circuit realizes the voltage division function, thus generating a stable reference voltage V ref . The output current is g m3 ·V in The element realizes the slow charging of the capacitor when the switch is turned off, thus realizing the slope voltage V slope When the switch is turned on, the slope voltage can be quickly reduced to 0V, so that the slope voltage starts timing again. After the comparator compares the reference voltage and the slope voltage, the signal output of the delay end time is realized, thereby realizing the timing of the OFFTIME module.

[0030] As mentioned above, this circuit has a fixed period and a constant frequency because the parameters in the circuit are fixed. However, when the duty cycle of the DCDC converter is extremely small, it will inevitably lead to an increase in the output voltage.

[0031] Figure 4FIG. 1 is a schematic diagram of the circuit structure of a station control delay generating unit in a frequency adjustable CFT control circuit in the present invention. Figure 4 As shown, the present invention relates to a frequency-adjustable CFT control circuit, which is used in a DCDC converter to control a PWM unit. The circuit includes an on-time control unit, an off-time control unit, and an RS trigger; wherein the on-time control unit is used to trigger a high-level signal of the PWM unit to turn on the high-end power tube of the DCDC converter; the off-time control unit realizes a fixed frequency or variable frequency mode of the DCDC converter based on the output voltage limit of the DCDC converter, and triggers a low-level signal of the PWM unit to turn off the low-end power tube of the DCDC converter.

[0032] It can be understood that the CFT control circuit can adjust the PWM unit of the DCDC converter, and can also be understood as a part of the PWM unit, thereby participating in the realization of the PWM output signal.

[0033] The influence of the control circuit on the PWM signal mainly includes the influence on the rising edge moment of the PWM signal and the falling edge moment of the PWM signal. Among them, the on-time control unit mainly controls the rising edge moment of the PWM signal to determine the on-time of the high-end power tube in the DCDC converter, while the off-time control unit is used to control the falling edge moment of the PWM signal to determine the off-time of the high-end power tube in the DCDC converter. The RS trigger can realize the aggregation of the above unit signals.

[0034] Specifically, in the present invention, the off-time control unit can control the time period of the DCDC converter based on the AC small signal element, so that the CFT circuit works in two different working modes: variable frequency and fixed frequency.

[0035] When the circuit duty cycle is high, the CFT circuit can operate in a fixed frequency mode. When the circuit duty cycle is extremely small and cannot meet the precise control of the output voltage, the output voltage will drift high. The frequency of the circuit can be changed to stabilize the output voltage at the minimum duty cycle.

[0036] Preferably, the on-time control unit controls the RS trigger to generate a low-level signal based on the inductor peak current and the minimum on-time to achieve the conduction of the high-end power tube.

[0037] It can be understood that the on-time control unit in the present invention is similar to the CFT circuit structure in the prior art. The method of generating the inductor peak current is also similar to the prior art. First, based on the error amplifier, the reference voltage and the feedback voltage FB are compared to generate a reference current Iref, and then Isense is obtained by sampling the inductor current. After comparing the two, the peak value of Isense is obtained, which is the inductor peak current Ipeak described in this article.

[0038] When the inductor peak current comes, if the minimum on-time meets the requirements, the circuit will set the R terminal of the RS trigger high. Since the S terminal voltage is at a low level at this time, the Q terminal output of the RS trigger is low. At this time, the PWM output signal can be controlled to be high, thereby turning on the high-end power tube.

[0039] Preferably, the off-time control unit controls the RS trigger to generate a high-level signal based on the duty delay and the minimum off-time to turn off the high-end power tube.

[0040] It can be understood that the off-time control unit is used to control the high and low level states of the S-terminal signal of the RS trigger. When S is at a high level and the R-terminal is at a low level, the output level of the Q-terminal is high, and the circuit can ensure the low level state of the PWM signal, thereby cutting off the high-end power tube.

[0041] Preferably, the duty delay is generated based on a duty delay generating unit; and the duty delay generating unit includes a reference voltage generating unit, a slope voltage generating unit, and a first comparing unit; wherein the reference voltage generating unit is used to generate a reference voltage; the slope voltage generating unit is used to start outputting a gradually increasing slope voltage and start the duty delay timing when the output signal of the RS trigger switches to a low level signal; the first comparing unit is used to compare the reference voltage of the reference voltage generating unit and the slope voltage of the slope voltage generating unit, and output a duty delay end signal when the slope voltage rises to the reference voltage.

[0042] It can be understood that the duty delay generating unit is Figure 2 The OFFTIME module in the circuit structure is as follows: Figure 4 The principle of this unit will be described in detail below.

[0043] Preferably, the reference voltage generating unit includes a first AC small signal element, a second AC small signal element, and a shunt resistor; the first AC small signal element and the second AC small signal element are connected in series in sequence and connected between the power supply voltage and the ground potential; the shunt resistor is connected in parallel at both ends of the second AC small signal element.

[0044] It can be understood that the reference voltage in the present invention realizes the shunting of the first AC small signal element according to the second AC small signal element and the shunt resistor connected in parallel.

[0045] Preferably, the output current of the first AC small signal element is g m1 ·V in , the output current of the second AC small signal element is g m1 ·V out ; Among them, g m1 is the transconductance of the first AC small signal element and the second AC small signal element, V in and V out They are the input voltage and output voltage of the DCDC converter respectively.

[0046] From this, we can know that the current in the shunt resistor branch is g m1 ·V in -g m1 ·V out In this case, the reference voltage generated by resistor R can be (g m1 ·V in -g m1 ·V out )·R.

[0047] Preferably, the slope voltage generating unit includes a third AC small signal element, a fourth AC small signal element, a slope capacitor, a switch element and a second comparison unit; wherein, one end of the third AC small signal element and the fourth AC small signal element is connected to the power supply voltage, and the other end is connected to the second comparison unit, and the second comparison unit outputs the smaller output current of the third AC small signal element and the fourth AC small signal element; after the slope capacitor is connected in parallel with the switch element, one end is connected to the output end of the second comparison unit, and the other end is grounded; the conduction and shutdown of the switch element are controlled based on the output signal of the RS trigger.

[0048] It can be understood that in another aspect of the circuit, there is also a slope voltage generating unit, which can charge the slope capacitor through the third or fourth AC small signal element, so that the upper plate of the capacitor generates a gradually rising slope voltage during the charging process.

[0049] like Figure 3 and Figure 4 As shown in , when the Toff-end output by the first comparison unit turns high, the switch element will be turned on, thereby discharging quickly and keeping the ramp voltage at 0 V. When the switch pin SW of the chip is at a falling edge, the inductor current is usually at a peak value, the high-end power tube will be turned off, and the switch element will be turned off synchronously to start charging the capacitor C, that is, the OFFTIME module starts timing.

[0050] Preferably, the output current of the third AC small signal element is g m3 ·V in , the output current of the fourth AC small signal element is g m4 ·V out ; wherein the fourth AC small signal element is a circuit composed of one or more small signal elements; and, g m3 and g m4 are the transconductance of the third AC small signal element and the fourth AC small signal element, V in and V out They are the input voltage and output voltage of the DCDC converter respectively.

[0051] It can be understood that in this circuit, the input of the third AC small signal element can be the input voltage V of the DCDC converter. in , and the input of the fourth AC small signal element can be the output voltage V of the DCDC converter out It should be noted that the fourth AC small signal element in the present invention may be composed of multiple elements, and may be obtained by shunting the output current of a shunt resistor or the second AC small signal element, or other elements having the same parameters as the above elements.

[0052] Through the control of the second comparison unit, the circuit can actually select the output current of the third AC small signal element or the fourth AC small signal element to charge the capacitor C when the duty cycle is different.

[0053] Preferably, the positive phase input terminal of the first comparison unit is connected to the upper plate of the slope capacitor, and the negative phase input terminal is connected to the reference voltage.

[0054] In the present invention, the first comparison unit is used to compare the reference voltage with the ramp voltage. In one embodiment of the present invention, the reference voltage with a fixed value can be designed to be equal to the maximum value of the ramp voltage, so that when the ramp voltage rises to be equal to the reference voltage, the output signal of the comparison unit is reversed, so that Figure 2 The output of OFFTIME in the input is flipped.

[0055] Preferably, when the duty cycle of the DCDC converter is greater than g m3 / g m4 When the DCDC converter is in fixed frequency operation mode, the duty delay is (1-D)·T, and the frequency of the DCDC converter is When the duty cycle of the DCDC converter is less than g m3 / g m4 When the DCDC converter is in variable frequency operation mode, the duty delay is The frequency of the DCDC converter is

[0056] It can be understood that, under the action of the second comparison unit, when the duty cycle is large, that is, when the output current of the third AC small signal element is smaller than the output current of the fourth AC small signal element, the DCDC converter works according to the original logic.

[0057] At this time, the transconductance of the first and second AC small signal components in the designed circuit are equal, so the reference voltage is V ref =(g m1 ·V in -g m1 ·V out )·R, due to the duty cycle D=V out / V in , so we can have a reference voltage equal to g m1 ·V in ·(1-D)·R. In addition, the voltage on the upper plate of the ramp voltage satisfies V slope1 =(g m3 ·V in ·t) / C. If the ramp voltage is equal to the reference voltage, the charging time t of the capacitor is the flip time T of the duty delay end signal. off .

[0058] Therefore, calculate g m1 ·V in ·(1-D)·R=(g m3 ·V in ·t) / C, then we have T off1 =g m1 ·(1-D)·RC / g m3 Furthermore, due to the off time, that is, the flip time satisfies T off1 =(1-D)·T1, then the fixed period of the DCDC converter is T1=g m1 RC / g m3 .

[0059] On the other hand, when the output current of the third AC small signal element is greater than the output current of the fourth AC small signal element, the slope capacitor is charged through the fourth AC small signal element. At this time, the reference voltage is still g m1 ·V in ·(1-D)·R. The ramp voltage is V slope2 =(g m4 ·V out ·t) / C. At this time, the simultaneous equations g m1 ·V in ·(1-D)·R=(g m4 ·V out ·t) / C, then we have Further simplifying the above content, we have In this case, the frequency of the DCDC converter will also change slightly with the size of the duty cycle. At this time, the period of the high-end and low-end power tubes in the DCDC converter is

[0060] At this time, whether it is T off2 T2 will automatically adjust with the duty cycle, especially when the duty cycle is extremely small. By extending the cycle, the output voltage will not float high, and the occurrence time of the inductor peak current can be later than the minimum on-time in each cycle, further controlling the stability of the circuit output. When the duty cycle is not extremely small, the original logic can be used to achieve the fixed frequency operation of the circuit, which will not affect the performance of the original circuit.

[0061] The beneficial effect of the present invention is that, compared with the prior art, the frequency-adjustable CFT control circuit in the present invention can control the turn-off delay of the power tube through two different AC small signal elements, so that the slope of the turn-off delay voltage can be adjusted, thereby realizing the stable voltage output of the CFT control circuit in two different states of fixed frequency and variable frequency. The circuit structure of the present invention is simple, the design is ingenious, and it is fully adapted to the DCDC converter in the prior art. The parameters are highly adjustable, so that the output voltage of the DCDC converter is sufficiently stable.

[0062] The applicant of the present invention has made a detailed explanation and description of the implementation examples of the present invention in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, but not to limit the scope of protection of the present invention. On the contrary, any improvements or modifications based on the inventive spirit of the present invention should fall within the scope of protection of the present invention.

Claims

1. A frequency adjustable CFT control circuit, characterized in that: The CFT control circuit is used in a DCDC converter to control a PWM unit, and the circuit includes an on-time control unit, an off-time control unit, and an RS trigger; The on-time control unit is used to trigger the high-level signal of the PWM unit to turn on the high-end power tube of the DCDC converter, and the on-time control unit controls the RS trigger to generate a low-level signal based on the inductor peak current and the minimum on-time to achieve on-time control of the high-end power tube; The off-time control unit realizes a fixed frequency or variable frequency mode of the DCDC converter based on the output voltage limit of the DCDC converter, and triggers a low-level signal of the PWM unit to turn off the low-end power tube of the DCDC converter. The off-time control unit controls the RS trigger to generate a high-level signal based on the duty delay and the minimum off-time to realize the off-time control of the high-end power tube; The duty delay is generated based on a duty delay generating unit; and, The duty delay generating unit includes a reference voltage generating unit, a slope voltage generating unit, and a first comparing unit; wherein, The reference voltage generating unit is used to generate a reference voltage; The slope voltage generating unit is used to start outputting a gradually increasing slope voltage and start the duty delay timing when the output signal of the RS trigger switches to a low level signal; The first comparison unit is used to compare the reference voltage of the reference voltage generation unit with the slope voltage of the slope voltage generation unit, and output a duty delay end signal when the slope voltage rises to the reference voltage; The slope voltage generating unit includes a third AC small signal element, a fourth AC small signal element, a slope capacitor, a switch element and a second comparing unit; Wherein, one end of the third AC small signal element and the fourth AC small signal element is connected to the power supply voltage, and the other end is connected to the second comparison unit, and the second comparison unit outputs the smaller output current of the third AC small signal element and the fourth AC small signal element; After the slope capacitor is connected in parallel with the switch element, one end is connected to the output end of the second comparison unit, and the other end is grounded; The switching element is turned on and off controlled based on the output signal of the RS flip-flop.

2. A frequency-adjustable CFT control circuit according to claim 1, characterized in that: The reference voltage generating unit includes a first AC small signal element, a second AC small signal element, and a shunt resistor; The first AC small signal element and the second AC small signal element are sequentially connected in series and connected between the power supply voltage and the ground potential; The shunt resistor is connected in parallel at both ends of the second AC small signal element.

3. A frequency-adjustable CFT control circuit according to claim 2, characterized in that: The output current of the first AC small signal element is g m1 ·V in , the output current of the second AC small signal element is g m1 ·V out ; Among them, g m1 is the transconductance of the first AC small signal element and the second AC small signal element, V in and V out are respectively the input voltage and the output voltage of the DCDC converter.

4. A frequency-adjustable CFT control circuit according to claim 3, characterized in that: The output current of the third AC small signal element is g m3 ·V in , the output current of the fourth AC small signal element is g m4 ·V out ; Wherein, the fourth AC small signal element is a circuit composed of one or more small signal elements; And, g m3 and g m4 are the transconductances of the third AC small signal element and the fourth AC small signal element, respectively, V in and V out are respectively the input voltage and the output voltage of the DCDC converter.

5. A frequency-adjustable CFT control circuit according to claim 4, characterized in that: The positive phase input terminal of the first comparison unit is connected to the upper plate of the slope capacitor, and the negative phase input terminal is connected to the reference voltage.

6. A frequency adjustable CFT control circuit according to claim 5, characterized in that: When the duty cycle of the DCDC converter is greater than g m3 / g m4 When the DCDC converter is in a fixed frequency working mode, the duty delay is (1-D)·T, and the frequency of the DCDC converter is When the duty cycle of the DCDC converter is less than g m3 / g m4 When the DCDC converter is in variable frequency operation mode, the duty delay is The frequency of the DCDC converter is

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