Capacitive load voltage level shifter

Abstract

The application discloses a capacitor load voltage reduction level shift circuit, which adopts a capacitor load structure and is applied to a GaN half-bridge driving circuit. In order to solve the influence of the driving circuit negative voltage, an anti-negative voltage circuit is provided with a voltage reduction level shift circuit to monitor the high-side voltage floating state in real time and feed back to the bootstrap charging loop, so that the charging time avoids the negative voltage time. The voltage reduction level shift circuit adopts a capacitor load, a narrow pulse controls the input of the high-side shift circuit, and a high-side delay circuit controls the capacitor charging and discharging loop, so that the common mode interference can be effectively reduced, the GaN device can be effectively protected, the gate voltage of the GaN device can be controlled in the normal working range, the damage of the GaN device caused by the negative voltage can be avoided, and the conversion speed is high and the power consumption is low.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a capacitor load step-down level shift circuit. BACKGROUND

[0002] As the third generation semiconductor device, GaN is gradually replacing silicon devices and widely used in traditional and new energy fields, greatly improving the power conversion efficiency. The half-bridge drive of GaN power device is an important part of the current GaN power device application system, and the half-bridge drive level shift circuit is a key research technology of the drive. The research focus is to design a high-performance level shift circuit to realize low-delay transient noise suppression and GaN negative voltage protection to meet the design requirements of high reliability and low power consumption. In the GaN half-bridge gate drive circuit, due to the freewheeling effect of inductive load, the self-lift capacitor will continuously charge, which will make the high-side power supply enter negative voltage, resulting in the gate-source voltage of the high-side GaN device being too high, thereby breaking the GaN device.

[0003] In order to ensure that the high-side voltage is clamped at the effective gate voltage of GaN, a high-side clamping negative voltage protection circuit needs to be designed to protect the GaN device, and a step-down level shift circuit is used to monitor the high-side voltage floating state in real time and feedback to the self-lift charging loop, so that the charging time avoids the negative voltage time. The structure of the level shift circuit generally includes resistance conversion, capacitance conversion, positive feedback interlocking conversion, current mode level conversion circuit, etc.

[0004] In order to effectively overcome the common-mode transient noise and further improve the fast conversion of the shift circuit, the present application provides a capacitor load step-down level shift circuit which can improve the conversion speed and effectively reduce the interference of common-mode noise. SUMMARY

[0005] The purpose of the present application is to overcome the problems existing in the prior art, and to provide a capacitor load step-down level shift circuit which adopts a capacitor load structure and is applied in a GaN half-bridge drive circuit. The negative voltage protection circuit adopts a step-down level shift circuit to monitor the high-side voltage floating state in real time and feedback to the self-lift charging loop, so that the charging time avoids the negative voltage time. The step-down level shift circuit adopts a capacitor load, the input of the high-side shift circuit is controlled by a narrow pulse, and the capacitor charging and discharging loop is controlled by a high-side delay circuit, which can effectively reduce the common-mode interference and has fast conversion speed and low power consumption.

[0006] To achieve the above technical purposes and achieve the above technical effects, the present application realizes the following technical solutions:

[0007] A capacitor load step-down level shift circuit, comprising a left channel input end V IN and a right channel input end V INN , the left channel input end V INThe input end of the inverter INV1 is connected with the output end of the inverter INV1, and the other end of the capacitor C3 is connected with the high side voltage HB. The internal conduction resistance of the inverter INV1 and the capacitor C3 are used to form an RC delay to generate a short pulse.

[0008] The output end of the inverter INV1 is connected with the input end of the buffer BUFF1, and the output end of the buffer BUFF1 is connected with the gate of the high side input PMOS transistor M1. The source of the PMOS transistor M1 is connected with the high side voltage HB, the drain of the PMOS transistor M1 is connected with the source of the PMOS transistor M3, the gate of the PMOS transistor M3 is connected with the left channel input end V IN , the drain of the PMOS transistor M3 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is connected with the ground GND. When the PMOS transistor M1 and the PMOS transistor M3 are turned on at the same time, the high side voltage HB charges the capacitor C1 through the PMOS transistor M1 and the PMOS transistor M3 for short pulse control.

[0009] The drain of the PMOS transistor M3 is connected with the input end of the buffer BUFF5 and the anode end of the diode D1, the output end of the buffer BUFF5 is connected with the output end V OUT1 , the cathode end of the diode D1 is connected with the low side voltage VCC, and the diode D1 is used as a clamping diode to prevent the voltage on the left shift channel from exceeding the low side voltage VCC.

[0010] Further, the left channel input end V IN is connected with the input end of the inverter INV3, and the output end of the inverter INV3 is connected with one end of the capacitor C5. The other end of the capacitor C5 is connected with the high side voltage HS. The internal conduction resistance of the inverter INV3 and the capacitor C5 are used to form an RC delay.

[0011] The output end of the inverter INV3 is connected with the input end of the buffer BUFF3, and the output end of the buffer BUFF3 is connected with the gate of the high side PMOS transistor M5. The output end of the buffer BUFF1 is connected with the input end of the inverter INV5, the output end of the inverter INV5 is connected with the gate of the PMOS transistor M7, the source of the PMOS transistor M5 is connected with the high side voltage HB, the drain of the PMOS transistor M5 is connected with the source of the PMOS transistor M7, and the drain of the PMOS transistor M7 is connected with the ground GND through the resistor R1. When the PMOS transistor M5 and the PMOS transistor M7 are turned on at the same time, the PMOS transistor M7 is in high level for short pulse control.

[0012] The drain of the PMOS transistor M7 is connected to the gate of the NMOS transistor M9, the drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M3, and the source of the NMOS transistor M9 is connected to the ground GND, so that the NMOS transistor M9 is turned on when the gate is high, and the capacitor C1 forms a discharge circuit through the NMOS transistor M9.

[0013] Further, the left channel input end V IN is connected to the input end of the inverter INV0, and the pulse signal at the output end of the inverter INV0 enters the right channel to form the right channel input end V INN .

[0014] Further, the right channel input end V INN is connected to the input end of the inverter INV2, the output end of the inverter INV2 is connected to one end of the capacitor C4, the other end of the capacitor C4 is connected to the high-side voltage HB, and the internal on-resistance of the inverter INV2 and the capacitor C4 form an RC delay to generate a short pulse;

[0015] The output end of the inverter INV2 is connected to the input end of the buffer BUFF2, the output end of the buffer BUFF2 is connected to the gate of the high-side input PMOS transistor M2, the source of the PMOS transistor M2 is connected to the high-side voltage HB, and the right channel input end V INN is connected to the gate of the PMOS transistor M4, the drain of the PMOS transistor M2 is connected to the source of the PMOS transistor M4, the drain of the PMOS transistor M4 is connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the ground GND, so that the PMOS transistor M2 and the PMOS transistor M4 are turned on at the same time to control the short pulse, and the high-side voltage HB charges the capacitor C2 through the PMOS transistor M2 and the PMOS transistor M4;

[0016] The drain of the PMOS transistor M4 is connected to the input end of the buffer BUFF6 and the anode end of the diode D2, the output end of the buffer BUFF6 is connected to the output end V OUT2 , and the cathode end of the diode D2 is connected to the low-side voltage VCC. The diode D2 is used as a clamping diode to prevent the voltage on the right shift channel from exceeding VCC.

[0017] Further, the right channel input end V INN is connected to the input end of the inverter INV4, the output end of the inverter INV4 is connected to one end of the capacitor C6, and the other end of the capacitor C6 is connected to the high-side voltage HS, and the internal on-resistance of the inverter INV4 and the capacitor C6 form an RC delay;

[0018] The output end of the inverter INV4 is connected with the input end of the buffer BUFF4, the output end of the buffer BUFF4 is connected with the gate of the PMOS transistor M6 of the high side, the source of the PMOS transistor M6 is connected with the high side voltage HB, the output end of the buffer BUFF2 is connected with the input end of the inverter INV6, the output end of the inverter INV6 is connected with the gate of the PMOS transistor M8, the drain of the PMOS transistor M6 is connected with the source of the PMOS transistor M8, the drain of the PMOS transistor M8 is connected with the ground GND through the resistance R2, so that the PMOS transistor M6 and the PMOS transistor M8 are turned on at the same time, and the drain of the PMOS transistor M8 is high level for the short pulse control.

[0019] The drain of the transistor M8 is connected with the gate of the NMOS transistor M10, the drain of the NMOS transistor M10 is connected with the drain of the PMOS transistor M4, and the source of the NMOS transistor M10 is connected with the ground GND, so that the NMOS transistor M10 is turned on when the gate is high level, and the capacitor C2 forms a discharge circuit through the NMOS transistor M10.

[0020] The beneficial effects of the present application are:

[0021] The circuit of the present application can be applied in the GaN half-bridge driving circuit, the step-down level shift circuit is adopted to monitor the high side voltage floating state in real time and feedback to the bootstrap charging circuit, so that the charging time avoids the negative voltage time, the step-down level shift circuit adopts the capacitor load, the input of the high side shift circuit is controlled by the narrow pulse, the high side delay circuit controls the capacitor charging and discharging circuit, the common mode interference can be effectively reduced, the conversion speed is fast, the power consumption is low, the GaN device can be effectively protected, the gate voltage is controlled in the normal working range, the damage of the GaN device caused by the negative voltage is avoided, the common mode noise suppression and high speed are good. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is a structure schematic diagram of the step-down level shift circuit of the present application.

[0023] Figure 2 It is a timing waveform diagram of each key node of the circuit of the present application.

[0024] Figure 3 It is a schematic diagram of the step-down level shift circuit of the present application applied in the GaN half-bridge driving integrated circuit. DETAILED DESCRIPTION

[0025] The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0026] As Figure 1As shown, a kind of capacitor load voltage reduction level shift circuit, high side negative voltage detection circuit detects circuit anomaly, output pulse signal enters voltage reduction level shift circuit input end V IN , input signal is divided into two ways and enters the left and right two channels of voltage reduction level shift circuit, including left channel input end V IN And right channel input end V INN , the left channel input end V IN It is connected with the input end of inverter INV1, the output end of inverter INV1 is connected with one end of capacitor C3, the other end of capacitor C3 is connected with high side voltage HB, and RC delay is formed by using the internal on-resistance of inverter INV1 and capacitor C3, so as to generate short pulse;

[0027] The output end of the inverter INV1 is connected with the input end of the buffer BUFF1, and the output end of the buffer BUFF1 is connected with the gate of the PMOS transistor M1 of the high side input.The PMOS transistor M1 is turned on when the gate is low, and the source of the PMOS transistor M1 is connected with the high side voltage HB.The drain of the PMOS transistor M1 is connected with the source of the PMOS transistor M3, and the gate of the PMOS transistor M3 is connected with the left channel input end V IN , the left channel input end V IN Is low, and the PMOS transistor M3 is turned on.The drain of the PMOS transistor M3 is connected with one end of capacitor C1, and the other end of capacitor C1 is connected with ground GND, so that the PMOS transistor M1 and the PMOS transistor M3 are turned on at the same time, which is a short pulse control, and the high side voltage HB charges the capacitor C1 through the PMOS transistor M1 and the PMOS transistor M3.

[0028] The drain of the PMOS transistor M3 is connected with the input end of the buffer BUFF5 and the anode end of the diode D1, and the output end of the buffer BUFF5 is connected with the output end V OUT1 , and the cathode end of the diode D1 is connected with the low side voltage VCC.The diode D1 is used as a clamping diode to prevent the voltage on the left shift channel from exceeding the low side voltage VCC.

[0029] The left channel input end V IN It is connected with the input end of inverter INV3, and the output end of inverter INV3 is connected with one end of capacitor C5, and the other end of capacitor C5 is connected with high side voltage HS, and RC delay is formed by using the internal on-resistance of inverter INV3 and capacitor C5.

[0030] The output end of the inverter INV3 is connected with the input end of the buffer BUFF3, the output end of the buffer BUFF3 is connected with the gate of the PMOS transistor M5, the PMOS transistor M5 is turned on when the gate is low, the output end of the buffer BUFF1 is connected with the input end of the inverter INV5, the output end of the inverter INV5 is connected with the gate of the PMOS transistor M7, the PMOS transistor M7 is turned on when the gate is low, the source of the PMOS transistor M5 is connected with the high side voltage HB, the drain of the PMOS transistor M5 is connected with the source of the PMOS transistor M7, the drain of the PMOS transistor M7 is connected with the ground GND through the resistor R1, so that the PMOS transistor M5 and the PMOS transistor M7 are turned on at the same time, which is short pulse control, and the drain of the PMOS transistor M7 is high;

[0031] The drain of the PMOS transistor M7 is connected with the gate of the NMOS transistor M9, the drain of the NMOS transistor M9 is connected with the drain of the PMOS transistor M3, the source of the NMOS transistor M9 is connected with the ground GND, so that the NMOS transistor M9 is turned on when the gate is high, and the capacitor C1 forms a discharge circuit through the NMOS transistor M9, so as to solve the problem of rapid discharge of the charge on the capacitor C1.

[0032] The left channel input end V IN is connected with the input end of the inverter INV0, and the pulse signal of the output end of the inverter INV0 enters the right channel to form the right channel input end V INN .

[0033] The right channel input end V INN is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with one end of the capacitor C4, the other end of the capacitor C4 is connected with the high side voltage HB, and the internal conduction resistance of the inverter INV2 and the capacitor C4 form an RC delay to generate a short pulse;

[0034] The output end of the inverter INV2 is connected with the input end of the buffer BUFF2, the output end of the buffer BUFF2 is connected with the gate of the PMOS transistor M2 of the high side input, the PMOS transistor M2 is turned on when the gate is low, the source of the PMOS transistor M2 is connected with the high side voltage HB, and the right channel input end V INN is connected with the gate of the PMOS transistor M4, and the right channel input end V INNWhen the low level, PMOS transistor M4 is turned on, the drain of PMOS transistor M2 and the source of PMOS transistor M4 is connected, the drain of PMOS transistor M4 and one end of capacitor C2 is connected, the other end of capacitor C2 is connected to ground GND, so that PMOS transistor M2 and PMOS transistor M4 are turned on at the same time, as short pulse control, high side voltage HB through PMOS transistor M2 and PMOS transistor M4 to charge capacitor C2;

[0035] The drain of PMOS transistor M4 is connected to the input end of buffer BUFF6 and the anode end of diode D2, the output end of buffer BUFF6 is connected to output end V OUT2 The cathode end of diode D2 is connected to low side voltage VCC, diode D2 is used as a clamping diode to prevent the voltage on the right shift channel from exceeding VCC.

[0036] The right channel input end V INN Is connected to the input end of inverter INV4, the output end of inverter INV4 is connected to one end of capacitor C6, the other end of capacitor C6 is connected to high side voltage HS, and the internal on-resistance of inverter INV4 and capacitor C6 are used to form RC delay;

[0037] The output end of inverter INV4 is connected to the input end of buffer BUFF4, the output end of buffer BUFF4 is connected to the gate of PMOS transistor M6 on the high side, and the gate of PMOS transistor M6 is turned on when it is low, the source of PMOS transistor M6 is connected to high side voltage HB, the output end of buffer BUFF2 is connected to the input end of inverter INV6, the output end of inverter INV6 is connected to the gate of PMOS transistor M8, and the gate of PMOS transistor M8 is turned on when it is low, the drain of PMOS transistor M6 is connected to the source of PMOS transistor M8, and the drain of PMOS transistor M8 is connected to ground GND through resistor R2, so that PMOS transistor M6 and PMOS transistor M8 are turned on at the same time, as short pulse control, the drain of PMOS transistor M8 is high;

[0038] The drain of transistor M8 is connected to the gate of NMOS transistor M10, the drain of NMOS transistor M10 is connected to the drain of PMOS transistor M4, and the source of NMOS transistor M10 is connected to ground GND, so that NMOS transistor M10 is turned on when the gate is high, and capacitor C2 forms a discharge circuit through NMOS transistor M10 to solve the problem of rapid discharge of charge on capacitor C2.

[0039] The dVs / dt of common mode noise suppression in the circuit is as follows: Vt is the switching threshold voltage of the output buffer (buffer BUFF5 and buffer BUFF6), which is generally VCC / 2, its important indicator FoM (Figure of Merit), FoM = (dVs / dt) * (Vs); for the left channel FoM = (V CC -V T ) / (R M9 *C M1 ) * Vs, wherein R M9 is the on equivalent resistance of NMOS transistor M9, C M1 is the drain equivalent capacitance of PMOS transistor M1, generally V T = V CC / 2, Vs = V CC , that is: FoM = [(V T / 2)] / (R M9 *C M1 )*(2*V T )=( V T ) 2 / ( R M9 *C M1 ); for high-speed circuit, the drain capacitance of input PMOS transistor M1 is generally not much changed, adjusting the size of NMOS transistor M9 can make its on resistance very small, so that its FoM indicator can be very high, and good common mode rejection effect is achieved under high-speed operation, as shown in Figure 2 , the timing of each key node shows that under the high-speed working frequency of 1MHz, the conduction time of the short pulse control circuit is 100nS, and the timing of each key test point of the voltage level shift circuit works reasonably. Due to the reasonable design of the short pulse, the power consumption is greatly reduced.

[0040] As shown in Figure 3 , it is a GaN power device half-bridge gate drive chip and application system circuit block diagram. The half-bridge drive circuit is divided into high side and low side two channels. The high side drive circuit realizes signal transmission in the form of bootstrap boost. Two inputs HI and LI enter the high side and low side channels respectively. The high side negative voltage detection circuit outputs a pulse signal to directly control the voltage level shift circuit. In order to prevent the voltage level shift circuit from appearing output simultaneously at high level due to noise influence, a logic processing protection circuit is added. After passing through the buffer, a pulse control signal is generated to directly control the switching transistor. The control signal is at high level during negative voltage period, and the switching transistor is not conductive, cutting off the charging circuit of the bootstrap capacitor. When working normally, the control signal is at low level, the switching transistor is conductive, and the bootstrap capacitor starts to charge, achieving the purpose of protecting the high side GaN device.

[0041] In addition, it should be noted that, unless specifically stated or pointed out otherwise, the terms "left", "right", and the like in the description are merely used to distinguish various components, elements, steps, and the like in the description, and are not used to indicate a logical relationship or a sequential relationship between the various components, elements, steps, and the like.

[0042] The preferred embodiments of the present application have been described above with the aid of drawing figures, and are not limited to those embodiments per se, which can be amended and changed by a variety of modifications and changes. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of the present application shall be included in the scope of the present application.

Claims

1. A capacitive load step-down level shifting circuit, characterized in that, Including the left channel input terminal V IN and the right channel input terminal V INN The left channel input terminal V IN The inverter INV1 is connected to the input terminal, and the output terminal of the inverter INV1 is connected to one end of the capacitor C3. The other end of the capacitor C3 is connected to the high-side voltage HB. The internal on-resistance of the inverter INV1 and the capacitor C3 form an RC delay to generate a short pulse. The output of inverter INV1 is connected to the input of buffer BUFF1. The output of buffer BUFF1 is connected to the gate of high-side input PMOS transistor M1. The source of PMOS transistor M1 is connected to the high-side voltage HB. The drain of PMOS transistor M1 is connected to the source of PMOS transistor M3. The gate of PMOS transistor M3 is connected to the left channel input V. IN The drain of PMOS transistor M3 is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to ground GND. When PMOS transistors M1 and M3 are turned on at the same time, it is a short pulse control. The high-side voltage HB charges capacitor C1 through PMOS transistors M1 and M3. The drain of the PMOS transistor M3 is connected to the input terminal of the buffer BUFF5 and the positive terminal of the diode D1, and the output terminal of the buffer BUFF5 is connected to the output terminal V. OUT1 The negative terminal of diode D1 is connected to the low-side voltage VCC. Diode D1 acts as a clamping diode to prevent the voltage on the left shift channel from exceeding the low-side voltage VCC. The left channel input terminal V IN The inverter INV3 is connected to the input terminal, and the output terminal of the inverter INV3 is connected to one end of the capacitor C5. The other end of the capacitor C5 is connected to the high-side voltage HS. The internal on-resistance of the inverter INV3 and the capacitor C5 form an RC delay. The output of inverter INV3 is connected to the input of buffer BUFF3. The output of buffer BUFF3 is connected to the gate of high-side PMOS transistor M5. The output of buffer BUFF1 is connected to the input of inverter INV5. The output of inverter INV5 is connected to the gate of PMOS transistor M7. The source of PMOS transistor M5 is connected to the high-side voltage HB. The drain of PMOS transistor M5 is connected to the source of PMOS transistor M7. The drain of PMOS transistor M7 is connected to ground GND through resistor R1. When PMOS transistors M5 and M7 are turned on simultaneously, it is controlled by a short pulse, and the drain of PMOS transistor M7 is at a high level. The drain of the PMOS transistor M7 is connected to the gate of the NMOS transistor M9, the drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M3, and the source of the NMOS transistor M9 is connected to ground GND, so that the NMOS transistor M9 is turned on when the gate is high, and the capacitor C1 forms a discharge circuit through the NMOS transistor M9. The left channel input terminal V IN Connected to the input of inverter INV0, the pulse signal at the output of inverter INV0 enters the right channel to form the input V of the right channel. INN ; The right channel input terminal V INN The inverter INV2 is connected to the input terminal, and the output terminal of the inverter INV2 is connected to one end of the capacitor C4. The other end of the capacitor C4 is connected to the high-side voltage HB. The internal on-resistance of the inverter INV2 and the capacitor C4 form an RC delay to generate a short pulse. The output of inverter INV2 is connected to the input of buffer BUFF2, and the output of buffer BUFF2 is connected to the gate of the high-side input PMOS transistor M2. The source of PMOS transistor M2 is connected to the high-side voltage HB, and the right channel input is V. INN The gate of PMOS transistor M4 is connected to the gate of PMOS transistor M2, the drain of PMOS transistor M2 is connected to the source of PMOS transistor M4, the drain of PMOS transistor M4 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to ground GND. When PMOS transistors M2 and M4 are turned on at the same time, it is a short pulse control, and the high-side voltage HB charges capacitor C2 through PMOS transistors M2 and M4. The drain of PMOS transistor M4 is connected to the input terminal of buffer BUFF6 and the positive terminal of diode D2. The output terminal of buffer BUFF6 is connected to the output terminal V. OUT2 The negative terminal of diode D2 is connected to the low-side voltage VCC. Diode D2 acts as a clamping diode to prevent the voltage on the right-side shift channel from exceeding VCC. The right channel input terminal V INN The inverter INV4 is connected to the input terminal, and the output terminal of the inverter INV4 is connected to one end of the capacitor C6. The other end of the capacitor C6 is connected to the high-side voltage HS. The internal on-resistance of the inverter INV4 and the capacitor C6 form an RC delay. The output of inverter INV4 is connected to the input of buffer BUFF4. The output of buffer BUFF4 is connected to the gate of high-side PMOS transistor M6. The source of PMOS transistor M6 is connected to the high-side voltage HB. The output of buffer BUFF2 is connected to the input of inverter INV6. The output of inverter INV6 is connected to the gate of PMOS transistor M8. The drain of PMOS transistor M6 is connected to the source of PMOS transistor M8. The drain of PMOS transistor M8 is connected to ground GND through resistor R2. When PMOS transistors M6 and M8 are turned on simultaneously, it is controlled by a short pulse, and the drain of PMOS transistor M8 is at a high level. The drain of transistor M8 is connected to the gate of NMOS transistor M10, the drain of NMOS transistor M10 is connected to the drain of PMOS transistor M4, and the source of NMOS transistor M10 is connected to ground GND, so that NMOS transistor M10 is turned on when the gate is high level, and capacitor C2 forms a discharge circuit through NMOS transistor M10.

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