Power control system for a system on a chip, system on a chip, and computing device

Abstract

Provided are a power consumption control system for a system on chip, the system on chip and a computing device. The power consumption control system comprises: a plurality of process sensors; a power consumption controller comprising: a chain controller configured to collect at least one count value from each of the plurality of process sensors, and to perform a weighted calculation on the count values of the plurality of process sensors to determine a process deviation of the system on chip under a first working condition; a voltage and frequency calculation unit configured to determine a target frequency and / or a target voltage to which the system on chip is to be adjusted according to the process deviation; a voltage adjustment signal generation unit configured to generate a voltage adjustment signal for adjusting a supply voltage of the system on chip according to the target voltage; and a frequency control unit configured to generate a frequency adjustment signal for adjusting a clock frequency of the system on chip according to the target frequency. The process deviation thus determined is more accurate, and the target frequency and the target voltage calculated based on the process deviation are also more suitable for the current working condition.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of chips, and in particular, to a power consumption control system for a system on chip, a system on chip and a computing device. BACKGROUND

[0002] With the continuous shrinking of integrated circuit processes, controlling chip cost and power consumption has become an important goal for major chip manufacturers. AVFS (Adaptive Voltage Frequency Scaling) is a common configuration for high-end CPUs, GPUs, mobile processors and other chips in the industry. AVFS is a power consumption reduction technology that acquires detection data in real time through sensors, and then determines the clock frequency and supply voltage of the chip system according to the detection data. Process deviation is a detection data obtained by using a process sensor to represent the performance deviation of the chip under the current process, current temperature and current voltage.

[0003] In order to represent the performance deviation of the chip, a plurality of process sensors are usually arranged at different positions inside the system on chip, and then a plurality of process deviation data are collected, and the final result is obtained by synthesizing the plurality of process deviation data. However, the inventors have found that the process deviation data thus obtained is affected by various factors such as the arrangement position and collection sequence of the sensors, and therefore cannot accurately reflect the current situation of the system. SUMMARY

[0004] Therefore, the purpose of the present disclosure is to provide a power consumption control system for a system on chip, a system on chip and a computing device to solve the technical problems existing in the prior art.

[0005] In a first aspect, the embodiments of the present disclosure provide a power consumption control system for a system on chip, comprising:

[0006] a plurality of process sensors;

[0007] a power consumption controller, comprising:

[0008] a chain controller configured to collect at least one count value from each of the plurality of process sensors, and to perform a weighted calculation on the count values of the plurality of process sensors to determine a process deviation of the system on chip under a first working condition;

[0009] a voltage and frequency calculation unit configured to determine a target frequency and / or a target voltage to which the system on chip is to be adjusted according to the process deviation;

[0010] a voltage adjustment signal generation unit configured to generate a voltage adjustment signal for adjusting the supply voltage of the system on chip according to the target voltage,

[0011] A frequency control unit is configured to generate a frequency modulation signal for adjusting a clock frequency of the system-on-chip according to the target frequency.

[0012] Optionally, the plurality of process sensors are connected in a loop and form a unidirectional data transmission path with the chain controller.

[0013] Optionally, the chain controller configures a corresponding weight for each process sensor according to the arrangement position and collection sequence of the process sensor to perform the weighted calculation.

[0014] Optionally, the process sensor comprises:

[0015] at least one oscillation ring, each oscillation ring being formed by connecting a plurality of inverters of the same type in a loop and coupled with a counting unit, the counting unit being configured to count the number of inversions of the plurality of inverters within a fixed time and output a count value of the number of inversions of the corresponding oscillation ring within a unit time,

[0016] the chain controller configures a weight for each oscillation ring, and performs a weighted calculation on at least one count value output by the at least one oscillation ring included in each process sensor to obtain a count value of the process sensor.

[0017] Optionally, the process sensor further comprises a mesh ring comprising a unique inverter and a wire with a length greater than a set threshold, and is configured to output a count value, and the chain controller performs a weighted calculation on the count value output by the at least one oscillation ring included in each process sensor and the mesh ring to obtain a count value of the process sensor.

[0018] Optionally, the chain controller configures different weights for different types of oscillation rings, and the type of the oscillation ring is determined by the type of the inverter comprising the oscillation ring.

[0019] In a second aspect, the disclosure provides a method for adjusting voltage and frequency, comprising:

[0020] collecting at least one count value from each process sensor;

[0021] performing a weighted calculation on the count values of the plurality of process sensors to obtain a process deviation of the system under a first working condition;

[0022] determining a target frequency and / or a target voltage to which the system is to be adjusted based on the process deviation; and

[0023] adjusting the clock frequency and / or the supply voltage of the system to the target frequency and / or the target voltage, respectively.

[0024] Optionally, the process deviation of the system under the current condition is determined based on the count values of the plurality of process sensors.

[0025] configuring a weight for each process sensor; and

[0026] performing a weighted calculation on the count values of the plurality of process sensors to obtain a process deviation of the system under current conditions.

[0027] In a third aspect, an embodiment of the present disclosure provides an on-chip system, comprising:

[0028] a processing unit;

[0029] a frequency and voltage adjustment controller comprising the power consumption control system according to any one of the preceding embodiments;

[0030] an on-chip bus for coupling the processing unit, the dual-rail memory and the power consumption control system.

[0031] In a fourth aspect, an embodiment of the present disclosure provides a computing device, comprising:

[0032] the on-chip system according to the preceding embodiments;

[0033] an off-chip bus;

[0034] a storage device coupled to the on-chip system through the off-chip bus;

[0035] a power management circuit coupled to the power consumption controller.

[0036] According to an embodiment of the present disclosure, at least one count value is collected from each process sensor by a chain controller, and a weighted calculation is performed on the count values of the plurality of process sensors to determine a process deviation of the system under current working conditions. The process deviation thus determined is more accurate, and the target frequency and target voltage calculated based on the process deviation are also more suitable for the current working conditions. BRIEF DESCRIPTION OF DRAWINGS

[0037] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0038] Figure 1 is a structural schematic diagram of an on-chip system to which an embodiment of the present disclosure is applied;

[0039] Figure 2 is a structural schematic diagram of an on-chip system to which another embodiment of the present disclosure is applied;

[0040] Figure 3 is a structural diagram of a process sensor constructed by an embodiment of the present disclosure;

[0041] Figure 4 is a structural diagram of a process sensor provided by another embodiment of the present disclosure;

[0042] Figure 5 is a flow chart of a method for adjusting voltage and frequency according to an embodiment of the present disclosure;

[0043] Figure 6 is a structural diagram of a general-purpose computer system to which an embodiment of the present disclosure is applied;

[0044] Figure 7 is a structural diagram of an embedded system to which an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0045] The present disclosure is described below based on embodiments, but the present disclosure is not limited to only these embodiments. In the following detailed description of the present disclosure, some specific details are described in detail. The present disclosure can also be fully understood without the description of these specific details by those skilled in the art. In order to avoid confusion of the essence of the present disclosure, well-known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0046] System on chip

[0047] Figure 1 is a structural diagram of a system on chip 100 to which an embodiment of the present disclosure is applied.

[0048] Referring to the drawings, a processing unit 101 and a high-speed memory 103, a cache 104 are coupled to a bus on chip 102. The bus on chip 102 is, for example, an AXI bus. The AXI bus is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 and above protocols proposed by ARM Company, and it is a bus on chip oriented to high performance, high bandwidth, and low latency. The AIX bus separates the address / control and data phases, supports unaligned data transmission, and supports burst transmission and out-of-order transmission, thus meeting the needs of ultra-high performance and complex system on chip design. The processing unit 101 can be any processing unit with different circuit structures, such as a microprocessor, a microcontroller, a digital processing unit (DSP), a processor core, a graphics processing unit (GPU), a neural network processing unit, etc. Unlike the high-speed memory 103 provided in the system on chip, the memory located off-chip can have a larger capacity but slower speed and lower cost. In some implementations, the high-speed memories 103 and 104 can be static random access memories (SRAM), and the memory off-chip can be a DRAM (dynamic random access memory) and a flash memory.

[0049] As shown in the figure, the AVFS controller 105 is coupled to the on-chip bus 102. The AVFS controller 105 is also coupled to the clock management unit 106 and the power management circuit 211 located off-chip, respectively.

[0050] The on-chip bus 102 further includes interface circuits (not shown) through which the on-chip bus 102 is coupled to external devices located off-chip. The external devices can be, for example, input / output devices for text, audio and video, and various memories. The processing unit 101 can access the external devices located off-chip through the interface circuits.

[0051] The on-chip system 100 can also embed basic software (not shown), such as an operating system of the on-chip system, and application programs for specific purposes. Other application programs can be stored in a memory located off-chip from the on-chip system 100, and these application programs can be copied into the high-speed memory 104 in the on-chip system 100 through the interface circuits or access the resources in the on-chip system 100 through the interface circuits.

[0052] The processing unit 101 is responsible for reading various instructions and decoding and executing the instructions. In the present embodiment, the processing unit 101 sends frequency-voltage adjustment instructions to the AVFS controller 105 via the on-chip bus 102.

[0053] The AVFS controller 105 performs frequency-voltage adjustment operations. In performing the frequency-voltage adjustment operations, the AVFS controller 105 generates a frequency adjustment signal REGF and a voltage adjustment signal REGV, sends the frequency adjustment signal REGF to the clock management unit 106, and sends the voltage adjustment signal REGV to the power management circuit 211, so as to adjust the clock frequency FCPU by the clock management unit 106 and adjust the supply voltage VCPU provided to the on-chip system 100 by the power management circuit 211.

[0054] As shown in the figure, the AVFS controller 105 includes a register set for storing a frequency point table 1051, a chain controller 1052, a voltage and frequency calculation unit 1053, a frequency control unit 1054, and a voltage adjustment signal generation unit 1055.

[0055] The frequency point table 1051 includes a plurality of frequencies, which are usually verified to be able to make the system work normally. The frequency point table 1051 is usually loaded into the register set after the system is powered on. When the system is powered on, the processing unit 101 or other components sends a frequency configuration instruction, and the AVFS controller 105 loads the frequency point table 1051 into the register set according to the frequency configuration instruction.

[0056] The chain controller 1052 is coupled to a plurality of process sensors ps, and is configured to collect a plurality of count values from the plurality of process sensors ps in real time and perform weighted calculation according to the plurality of count values to determine a process deviation.

[0057] The voltage and frequency calculation unit 1053 calculates the target frequency and the target voltage to which the system is to be adjusted, based on the process variation data received from the chain controller 1052, and provides the target frequency and the target voltage to the frequency control unit 1054 and the voltage control signal generation unit 1055, respectively. The voltage control signal generation unit 1055 generates the voltage control signal REGV based on the target voltage, and the frequency control unit 1054 generates the frequency control signal REGF based on the target frequency. Optionally, the AVFS controller 105 can further include an alarm unit (not shown) for alarming abnormal conditions.

[0058] Optionally, the voltage and frequency calculation unit 1053 further adjusts the target frequency using the frequency point table 1051, for example, when the target frequency exceeds the maximum frequency or the minimum frequency in the frequency point table, the target frequency is considered inappropriate, or when the target frequency does not match any of the frequencies in the frequency point table, the target frequency is considered inappropriate, in the case where the target frequency is considered inappropriate, the frequency closest to the target frequency can be obtained from the frequency point table, and the target frequency is assigned to the target frequency.

[0059] As shown in the figure, the six process sensors ps are connected in series with the chain controller 1052, forming a unidirectional data transmission path. The chain controller 1052 is both the starting point and the ending point of the data transmission path. The physical link of the process sensors is represented by arrows in the figure. Such a serial physical link is advantageous in saving wiring space on the system 100. It should be noted that a chip that generally complies with the boundary scan protocol (for example, IEEE 1149.1) contains scan chains, which are mainly used to help testers control and observe the signal changes inside the integrated circuit from the outside of the integrated circuit. In this embodiment, the scan chains inside the process sensors ps are used to connect multiple process sensors ps in series.

[0060] The chain controller 1052 sends data requests to the multiple process sensors ps along the data transmission path and receives count values from the multiple process sensors ps, and obtains the count values of the individual process sensors ps based on the multiple process sensors ps.

[0061] Figure 2 is a structural schematic diagram of another embodiment of a system on a chip. In this embodiment, the power management circuit 212 is disposed inside the system on a chip 200.

[0062] Figure 3is a structural diagram of an exemplary process sensor ps. As shown in the diagram, the process sensor ps includes an LVT ring oscillator 301, an RVT ring oscillator 302, an HVT ring oscillator 303, a calculation unit 305 coupled to the LVT ring oscillator 301, a counting unit 306 coupled to the RVT ring oscillator 302, and a counting unit 307 coupled to the HVT ring oscillator 303.

[0063] The LVT ring oscillator 301 is a loop of an odd number of LVT inverters. The RVT ring oscillator 302 is a loop of an odd number of RVT inverters. The HVT ring oscillator 303 is a loop of an odd number of HVT inverters. A plurality of inverters of the same type can be connected into a loop by a switch control signal. An odd number of inverters can ensure that a signal passing through the ring oscillator can return with an opposite signal, for example, the LVT ring oscillator 301 starts with a value of 0, and then passes through 5 LVT inverters to return with a value of 1. The time for the signal to return is the sum of the delay times of the odd number of inverters, thereby generating a periodic signal oscillation.

[0064] The counting units 305-307 each calculate a count value of the ring oscillator to which it is coupled in a unit of time under current conditions. Specifically, the LVT inverters, the RVT inverters, and the HVT inverters are each composed of an inverter unit in the LVT, RVT, and HVT standard cell libraries. According to the design of the standard cell library, different types of inverters each have a timing parameter including inverter delay times under different temperatures, different process variations, and different voltages. According to the parameter, the delay times of the three types of inverters under current conditions are determined, and then the product of the inverter delay times and the number of inverters is the oscillation period time of the ring oscillator. The count value in a fixed time is then divided by the oscillation period of the ring oscillator, thereby obtaining the count value of each ring oscillator in a unit of time under current conditions.

[0065] Figure 4 is a structural diagram of an exemplary process sensor ps. As shown in the diagram, the process sensor ps includes an LVT ring oscillator 311, an RVT ring oscillator 312, an HVT ring oscillator 313, a mesh ring 314, a calculation unit 315 coupled to the LVT ring oscillator 311, a counting unit 316 coupled to the RVT ring oscillator 312, and a counting unit 317 coupled to the HVT ring oscillator 313.

[0066] with Figure 3The difference lies in the addition of a network ring 314 and a counting unit 318 coupled to the network ring 314 to the process sensor ps. As shown in the diagram, the network ring 314 contains only one inverter, which is one of the following: LVT, RVT, or HVT inverters. The network ring's wiring is very long, and since the network delay of the wiring is much greater than the network delay of the inverters, the network delay reflected by the network ring is essentially the network delay of the wiring. The network ring 314 also includes three inverters, which is sufficient to meet the requirements.

[0067] Will Figures 3-4 and Figure 2 As can be understood, since multiple process sensors ps form a unidirectional data transmission path, the chain controller 1052 can serially and periodically send data read requests to each process sensor ps. After receiving the request, each process sensor ps obtains the count value generated on each oscillating ring inside it and transmits the count value on each oscillating ring to the chain controller 1052 via the data transmission path.

[0068] After obtaining the count values, the chain controller 1052, in one implementation, without including the network ring, calculates the system's process deviation under the current conditions through the following steps: First, the count values ​​of each oscillating ring of each process sensor ps are weighted, summed, and then averaged to obtain the weighted average count value of each process sensor ps. Then, the weighted average count values ​​of multiple sensors are weighted, summed, and averaged again to obtain the system's process deviation under the current conditions. Alternatively, the chain controller 1052 can also obtain the system's process deviation under the current conditions through the following steps: First, the count values ​​of each oscillating ring of each process sensor ps are summed and then averaged to obtain the average count value of each process sensor ps. Then, the average count values ​​of multiple sensors are weighted, summed, and averaged again to obtain the system's process deviation under the current conditions.

[0069] It should be understood that when performing a weighted calculation on the count values ​​of each oscillating ring in a process sensor, a weight must first be assigned to each oscillating ring. Optionally, the weight of each oscillating ring is determined by the type of inverter that makes up that oscillating ring. Similarly, when performing a weighted calculation on the count values ​​of multiple process sensors, a weight must first be assigned to each process sensor. Optionally, the weight of each process sensor can be determined based on its position (or sequence number) in the unidirectional data transmission path.

[0070] The formula of the weighted calculation is as follows: assuming that the weight of the process sensor 1 is w0, the count value is count0, the weight of the process sensor 2 is w1, the count value is count1, and the weight of the process sensor 3 is w2, the count value is count2. Then the process deviation obtained by integrating the count values of the three process sensors is:

[0071] counter = (counter0*w0+counter1*w1+counter2*w2) / 3 Formula (1)

[0072] Similarly, when the count values output by multiple oscillation rings are weighted and calculated, the formula is similar to formula (1).

[0073] In the case of including a mesh ring, the chain controller 1052 can process each oscillation ring based on the count value obtained by the mesh ring, for example, the count unit 315, the count unit 316, the count unit 317 and the count unit 318 are added with the count value of the count unit 318 respectively as the recalculated count value of each oscillation ring, and then the following steps are used to obtain the process deviation of the system under the current condition: first, the recalculated count value of each process sensor ps of each oscillation ring is weighted and summed and then averaged to obtain the weighted average count value of each process sensor ps, and then the weighted average count values of multiple sensors are weighted and summed again and then averaged to obtain the process deviation of the system under the current condition. Another embodiment of the above (another embodiment used in process sensors without mesh rings) can also be used here, which is not repeated here.

[0074] It should be understood that the disclosure can adjust the oscillation rings inside the process sensor according to the specific situation, for example, only LVT oscillation ring 301 and RVT oscillation ring 302 are arranged in each process sensor, or only LVT oscillation ring 301 and mesh ring 304 are arranged. In addition, there are not only LVT inverters, RVT inverters, HVT inverters, but also other types of inverters, such as uLVT.

[0075] Due to comparison, the speed of the HVT inverter is the highest, the delay is the smallest, but the power consumption is the largest. The speed of the LVT inverter is the smallest, the delay is the largest, but the power consumption is the smallest. The speed, delay and power consumption of RVT are between the two. Therefore, the process sensor can also be constructed according to the speed, delay and power consumption.

[0076] According to the above embodiment, at least one count value is collected from each process sensor by the chain controller, and the count values of multiple process sensors are weighted and calculated to determine the process deviation of the system under the current condition, so that the process deviation represented is more reasonable, and the target frequency and target voltage determined based on the process deviation are also more suitable for the current situation.

[0077] In addition, the weight configuration is flexible, for example, the weight can be determined based on the current working condition of each system on chip (e.g., different voltage, different temperature, different arrangement and acquisition sequence of process sensors).

[0078] As an embodiment, when the plurality of process sensors and the chain controller form a unidirectional data transmission path, the weight of each process sensor can be configured according to the position (or sequence number) of each process sensor in the unidirectional data transmission path, because the position information affects the output count value. In addition, the weight of each process sensor or each oscillator can also be obtained through multiple experiments.

[0079] Power control system for system on chip of embodiments of the disclosure

[0080] Based on the above embodiments, the present disclosure provides a power consumption control system for a system on chip. Referring to Figure 1 or 2, the power consumption control system includes: a plurality of process sensors ps, a power consumption controller, the power consumption controller includes: a chain controller 1052, a voltage and frequency calculation unit 1053, a voltage adjustment signal generation unit 1055 and a frequency control unit 1054.

[0081] The chain controller 1052 is coupled with the plurality of process sensors ps, configured to collect at least one count value from the plurality of process sensors ps respectively, and perform weighted calculation on the count values of the plurality of process sensors to determine the process deviation of the system on chip under the current working condition.

[0082] The voltage and frequency calculation unit 1053 is configured to determine the target frequency and / or target voltage to which the system on chip is to be adjusted according to the process deviation.

[0083] The voltage adjustment signal generation unit 1055 is configured to generate a voltage adjustment signal for adjusting the power supply voltage of the system on chip 1 according to the target voltage.

[0084] The frequency control unit 1054 is configured to generate a frequency adjustment signal for adjusting the clock frequency of the system on chip according to the target frequency.

[0085] The power consumption controller provided in the embodiment can be used in a system on chip, and can also be used in other computer environments. The power consumption controller calculates the process deviation more accurately through weighted calculation, so that the target frequency and target voltage calculated based on the process deviation are also more suitable for the current working condition. For more detailed description of the components of the power consumption controller, refer to the embodiments in the above, which will not be described here.

[0086] Method of adjusting frequency and voltage of embodiments of the disclosure

[0087] Figure 5 A flowchart of a method for adjusting frequency and voltage is shown, which includes the following steps.

[0088] In step S01, at least one count value is collected from each process sensor.

[0089] In step S02, the count values of the plurality of process sensors are weighted to determine a process deviation of the system under current conditions. Each process sensor outputs at least one count value for characterizing a performance deviation of the current processor. The plurality of count values are integrated to determine a process deviation of the system under current conditions. For example, the count values of each oscillation ring in each process sensor are first weighted and averaged to obtain a weighted average count value of each process sensor, and then the weighted average count values of the plurality of sensors are weighted and averaged again to obtain a process deviation of the system under current conditions.

[0090] In step S03, a target frequency and a target voltage to which the system is to be adjusted are determined based on the process deviation. Although the process deviation is only one factor affecting the target frequency and the target voltage to which the system is to be adjusted, the target frequency and the target voltage can be calculated by combining the process deviation with other factors (e.g., temperature). In addition, after the preliminary target frequency and the preliminary target voltage are calculated, the final target frequency to which the system is to be adjusted can be determined based on the preliminary target frequency and the preliminary target voltage, and the final target voltage to which the system is to be adjusted can be determined based on the final target frequency to which the system is to be adjusted. Figure 1 or Figure 2 In step S03, a target frequency and a target voltage to which the system is to be adjusted are determined based on the process deviation. Although the process deviation is only one factor affecting the target frequency and the target voltage to which the system is to be adjusted, the target frequency and the target voltage can be calculated by combining the process deviation with other factors (e.g., temperature). In addition, after the preliminary target frequency and the preliminary target voltage are calculated, the final target frequency to which the system is to be adjusted can be determined based on the preliminary target frequency and the preliminary target voltage, and the final target voltage to which the system is to be adjusted can be determined based on the final target frequency to which the system is to be adjusted.

[0091] In step S04, the processing frequency and the supply voltage of the system are adjusted to the target frequency and the target voltage, respectively.

[0092] In some embodiments, determining a process deviation of the system under current conditions according to the count values of the plurality of process sensors comprises the following steps: first, configuring a weight for each process sensor, and then weighting the count values of the plurality of process sensors to obtain the process deviation of the system under current conditions.

[0093] In some embodiments, the count value of each process sensor is obtained by the following steps: first, configuring a weight for each oscillation ring in each process sensor, and then weighting the count values of at least one oscillation ring in each process sensor to obtain the count value of each process sensor under current conditions.

[0094] In some embodiments, the weight of each process sensor is configured according to the position of the process sensor in the unidirectional data transmission path.

[0095] In some embodiments, different weights are configured according to different types of oscillation rings, and the type of the oscillation ring is determined by the type of the inverter that constitutes the oscillation ring.

[0096] Specific applications of system on chip

[0097] Figure 6 is a structural schematic diagram of a general-purpose computer system to which embodiments of the present disclosure are applied. As shown in the figure, the computer system 600 can include one or more processors 12 and a memory 14. The system on a chip provided by the above embodiments can be used as the processor 12.

[0098] The memory 14 in the computer system 600 can be a main memory (referred to as main memory or memory for short). It is used to store instruction information and / or data information represented by data signals, for example, to store data provided by the processor 12 (for example, as an operation result), and can also be used to realize data exchange between the processor 12 and an external storage device 16 (also referred to as auxiliary storage or external memory).

[0099] In some cases, the processor 12 can need to access the memory 14 to obtain data in the memory 14 or modify data in the memory 14. Since the access speed of the memory 14 is relatively slow, in order to alleviate the speed gap between the processor 12 and the memory 14, the computer system 600 further includes a cache memory 18 coupled to the bus 11, which is used to cache some program data or message data in the memory 14 that can be repeatedly called. The cache memory 18 is implemented by a storage device such as static random access memory (SRAM) and the like. The cache memory 18 can be a multi-level structure, for example, a three-level cache structure with a first-level cache (L1 Cache), a second-level cache (L2 Cache) and a third-level cache (L3 Cache), or a cache structure of more than three levels or other types of cache structures. In some embodiments, a part of the cache memory 18 (for example, the first-level cache, or the first-level cache and the second-level cache) can be integrated inside the processor 12 or integrated in the same system on a chip as the processor 12.

[0100] Based on this, the processor 12 can include an instruction execution unit 121, a memory management unit 122, and the like. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory, and the write access request specifies the write data to be written into the memory and the corresponding physical address; the memory management unit 122 is used to translate the virtual address specified by these instructions into the physical address mapped by the virtual address, and the physical address specified by the write access request can be consistent with the physical address specified by the corresponding instruction.

[0101] The information exchange between the memory 14 and the cache memory 18 is usually organized in blocks. In some embodiments, the cache memory 18 and the memory 14 can be divided into data blocks in the same spatial size, which can be the minimum unit of data exchange between the cache memory 18 and the memory 14 (including one or more data of a preset length). For the sake of simplicity and clarity of expression, each data block in the cache memory 18 will be referred to as a cache block (which can be referred to as a cacheline or cache line) below, and different cache blocks have different cache block addresses; each data block in the memory 14 will be referred to as a memory block, and different memory blocks have different memory block addresses. The cache block address, for example, includes a physical address tag for locating a data block.

[0102] Due to the limitation of space and resources, the cache memory 18 cannot cache all the contents in the memory 14, i.e., the storage capacity of the cache memory 18 is usually smaller than that of the memory 14, and each cache block address provided by the cache memory 18 cannot correspond to all the memory block addresses provided by the memory 14. When the processor 12 needs to access the memory, it first accesses the cache memory 18 via the bus 11 to determine whether the content to be accessed has been stored in the cache memory 18. If so, the cache memory 18 hits, and the processor 12 directly calls the content to be accessed from the cache memory 18. If the content to be accessed by the processor 12 is not in the cache memory 18, the cache memory 18, the processor 12 needs to access the memory 14 via the bus 11 to find the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, the efficiency of the processor 12 can be significantly improved when the cache memory 18 hits, thereby improving the performance and efficiency of the entire computer system 600.

[0103] In addition, the computer system 600 can also include a storage device 16, a display device 13, an audio device 19, a mouse / keyboard 15, and other input / output devices. The storage device 16 is, for example, a hard disk, an optical disk, a flash memory, and other devices for information access coupled with the bus 11 through a corresponding interface. The display device 13 is, for example, coupled with the bus 11 through a corresponding display card, and is used for display according to the display signal provided by the bus 11.

[0104] The computer system 600 also typically includes a communication device 17, and thus can communicate with a network or other devices via a variety of means. The communication device 17 can include, for example, one or more communication modules, and by way of example, the communication device 17 can include a wireless communication module adapted for a particular wireless communication protocol. For example, the communication device 17 can include a WLAN module for implementing Wi-Fi™ communications in compliance with the Institute of Electrical and Electronics Engineers (IEEE) 602.11 standards; the communication device 17 can also include a WWAN module for implementing wireless wide area communications in compliance with cellular or other wireless wide area protocols; the communication device 17 can also include a Bluetooth module or other communication module employing other protocols, or other custom types of communication modules; and the communication device 17 can also be a port for serial transmission of data.

[0105] Of course, different computer systems can vary in structure depending on the motherboard, operating system, and instruction set architecture. For example, many computer systems are now provided with an input / output control center connected between the bus 11 and various input / output devices, and the input / output control center can be integrated within the processor 12 or independent of the processor 12.

[0106] Figure 7 is a structural diagram of an embedded system to which the embodiments of the present disclosure are applied. The system on chip provided by the above embodiments can be used as the processor 701.

[0107] Although the embedded system has high similarity with the computer system in the hardware structure, the characteristics of the embedded system application cause the embedded system to have great difference with the general computer system in the composition and implementation form of the hardware.

[0108] First, to meet the requirements of the embedded system 700 in speed, volume, and power consumption, the operating system, application software, and special data, and other data that need to be stored for a long time, usually do not use a disk or other storage medium with large capacity and slow speed, but mostly use the random access memory 702 or the flash memory 703.

[0109] In addition, in the embedded system 700, an A / D (analog / digital conversion) interface 705 and a serial interface 706 are required for the need of measurement and control, which are rarely used in general computers. The A / D interface 705 mainly completes the conversion of analog signals to digital signals and the conversion of digital signals to analog signals required in testing. The embedded system 700 is often required to be tested when applied to industrial production. Since the single-chip microcomputer generates digital signals, the digital signals need to be converted into analog signals for testing when testing, and therefore, unlike general computers, the A / D (analog / digital conversion) interface 705 is required to complete the related conversion. In addition, multiple embedded systems are often required to be connected in series in the industry to complete related functions, and therefore, the serial interface 706 for connecting multiple embedded systems in series is required, which is mostly not required in general computers.

[0110] In addition, the embedded system 700 as a basic processing unit often needs to be connected into a network in industrial design, and therefore, the network interface 707 for connecting the embedded system 700 into a network is required. This is also mostly not required in general computers. In addition, according to the actual application and scale, some embedded systems 700 need to use external buses 704. With the rapid expansion of the application field of the embedded system 700, the embedded system 700 is increasingly personalized, and the types of buses used according to the characteristics of the embedded system 700 are also increasingly diversified. In addition, in order to test the internal circuit of the embedded processor 701, the boundary scan test technology is generally used for the processor chip. In order to adapt to the test, the debug interface 708 is used.

[0111] With the rapid development of very large scale integration (VLSI) and semiconductor technology, part or all of the above-mentioned embedded system can be implemented on a silicon chip, that is, an embedded system on a chip (SoC).

[0112] Commercial value of embodiments of the disclosure

[0113] The system on a chip provided by the embodiments of the present disclosure obtains the process deviation through weighted calculation, and determines the target frequency and the target voltage to which the system needs to be adjusted based on the process deviation, so that the target frequency and the target voltage can better reflect the current situation. Such a system on a chip can be used to form a computing device used in various scenarios, for example, a cloud server with a large number of data centers; for another example, an electronic device used in daily life, including terminal devices such as a notebook computer and a mobile phone and some consumer electronic products. As can be seen, the system on a chip and the computing device constructed by the system on a chip of the embodiments of the present disclosure have commercial value and economic value on the basis of practical value.

[0114] Those skilled in the art can understand that the present disclosure can be implemented as a system, a method and a computer program product. Therefore, the present disclosure can be embodied in a form of a complete hardware, a complete software (including firmware, resident software, microcode), and also can be embodied in a form of a software and hardware combination. In addition, in some embodiments, the present disclosure can also be embodied in a form of a computer program product in one or more computer readable media including computer readable program codes.

[0115] Any combination of one or more computer readable medium can be employed. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any suitable combination of the above. More specific examples of a computer readable storage medium include a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this context, a computer readable storage medium can be any tangible medium that can contain or store a program for use by or in connection with a processing unit, apparatus or device.

[0116] A computer readable signal medium can include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal can take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium can be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

[0117] Program code embodied on a computer readable medium can be transmitted using any appropriate medium, including but not limited to wireless, wire line, optical fiber cable, RF, etc., and any suitable combination of the above.

[0118] Computer program code for carrying out operations of embodiments of the present disclosure can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++, or a conventional procedural programming language, such as the C programming language. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0119] The specific embodiments of the present disclosure described above are illustrative, and not intended to limit the scope of the present disclosure. Various modifications and changes can be made therein and alternatives can be substituted without departing from the spirit and scope of the present disclosure as recited in the claims.

Claims

1. A power control system for a system on chip, comprising: a plurality of process sensors; a power controller, comprising: a chain controller configured to collect at least one count value from each of the plurality of process sensors, and to perform a weighted calculation on the count values of the plurality of process sensors to determine a process deviation of the system on chip under a first working condition; wherein the plurality of process sensors are connected in a loop and form a unidirectional data transmission path with the chain controller, the chain controller is the start point and the end point of the data transmission path, and the chain controller configures a corresponding weight for each process sensor according to a layout position and a collection sequence of the process sensor to perform the weighted calculation; a voltage and frequency calculation unit configured to determine a target frequency and / or a target voltage to which the system on chip is to be adjusted according to the process deviation; a voltage adjustment signal generation unit configured to generate a voltage adjustment signal for adjusting a supply voltage of the system on chip according to the target voltage; a frequency adjustment control unit configured to generate a frequency adjustment signal for adjusting a clock frequency of the system on chip according to the target frequency.

2. The power consumption control system of claim 1, wherein, The process sensor comprises: at least one oscillation ring, each oscillation ring being formed by a plurality of inverters of the same type connected in a loop and coupled with a counting unit, the counting unit being configured to count a number of inversions of the plurality of inverters within a fixed time, and to output a number of inversions of the corresponding oscillation ring within a unit time as a count value; the chain controller configures a weight for each of the at least one oscillation ring, and performs a weighted calculation on the at least one count value output by the at least one oscillation ring included in each process sensor to obtain a count value of the process sensor.

3. The power consumption control system of claim 2, wherein, The process sensor further comprises a mesh ring including a unique inverter and a wire with a length greater than a set threshold, and is configured to output a count value, and the chain controller performs a weighted calculation on the count values output by the at least one oscillation ring and the mesh ring included in each process sensor to obtain a count value of the process sensor.

4. The power consumption control system of claim 3, wherein, The chain controller configures different weights for different types of oscillation rings, and the type of the oscillation ring is determined by the type of the inverters included in the oscillation ring. 5.A method for adjusting voltage and frequency, comprising: collecting at least one count value from each process sensor; performing a weighted calculation on count values of a plurality of process sensors to obtain a process deviation of a system under a first working condition, wherein the plurality of process sensors are connected in a loop and form a unidirectional data transmission path with a chain controller, the chain controller is the start point and the end point of the data transmission path, and the chain controller configures a corresponding weight for each process sensor according to a layout position and a collection sequence of the process sensor to perform the weighted calculation; determining a target frequency and / or a target voltage to which the system is to be adjusted based on the process deviation; and adjusting a clock frequency and / or a supply voltage of the system to the target frequency and / or the target voltage, respectively. 6.A system on chip, comprising: a processing unit; a frequency and voltage adjustment controller comprising a power control system according to any one of claims 1 to 4; a bus on chip configured to couple the processing unit and the frequency and voltage adjustment controller.

7. A computing device comprising: the system on chip of claim 6; an off-chip bus; a storage device coupled with the system on chip through the off-chip bus; a power management circuit coupled with the power consumption controller.

8. The computing device of claim 7, wherein the power management circuit is configured to: determine a power consumption of the system on chip; determine a power consumption of the storage device; determine a power consumption of the off-chip bus; determine a power consumption of the power consumption controller; determine a power consumption of the power management circuit; determine a power consumption

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