Prefetching method and system based on thread branch information in graphics processor

Abstract

The present application provides a prefetching method and system based on thread branch information in a graphics processor (GPU), which is applied to the field of GPU instruction prefetching technology. The method comprises determining context information and a first index of a first instruction pointer (PC) of a branch stack at a first moment and a first top instruction pointer; establishing a miss table corresponding to the branch stack based on the context information and the second index, where the second index is the previous index of the first index; and prefetching missing instruction pointers within a time period corresponding to the first instruction pointer based on the miss table each time the GPU executes the second top instruction pointer of the branch stack. The missing instruction pointers are obtained based on the context information, effectively reducing instruction cache misses caused by locality issues between branch instructions in the GPU and improving the GPU's execution speed. The method relies on the program's global context information, making it more clear and reliable, and effectively reducing design complexity.

Description

Technical Field

[0001] The present application relates to the technical field of graphics processor instruction prefetching, and in particular to a prefetching method and system based on thread branch information in a graphics processor. Background Art

[0002] Currently, graphics processors usually use predicates to execute branches serially, and use masks to achieve selective execution of threads in a warp. For example, Figure 1 As shown, taking a 4-thread graphics processor unit as an example, branches start at A and are divided into B and C. Among them, two threads should execute branch B, and the other two threads should execute branch C. The graphics processor will execute branch B first and then branch C serially, and use their respective masks to mask the threads not executing under the current branch, and then converge to D. Among them, the mask at A is 1111, the mask at B is 1010, the mask at C is 0101, and the mask at D is 1111. The above information is usually stored in a stack called the branch stack (IPDOM), whose structure is as follows Figure 2 As shown in Figure 1. It includes: the next instruction pointer (Next program counter, Next pc), the current mask and the reconvergence instruction pointer (program counter, pc).

[0003] The branch stack grows downward, so the bottom of the stack contains the most recently pushed data. When a branch instruction is encountered, the starting instruction pointer (pc), current mask, and reconvergence instruction pointer (pc) corresponding to the currently executed branch are pushed in. After the branch is completed, the data is popped out or updated based on whether the reconvergence point is reached.

[0004] Current prefetching technology overlaps computation and memory access, issuing prefetch requests before cache misses are likely to occur. This allows data blocks to be cached before they are actually needed, thus avoiding processor stalls caused by cache misses. Graphics processors use a warp scheduler to switch warps when encountering cache misses to mask pipeline stalls caused by cache misses. However, instruction cache misses remain poorly optimized for individual tasks. Because all branch directions must be executed, instructions in certain directions may not be in the instruction cache due to poor spatial locality, potentially resulting in cache misses. When there are many branch instructions, switching warps may not fully mask latency, thus impacting processor performance.

[0005] Therefore, a new technical solution for instruction caching in a graphics processor is needed. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a prefetching method and system based on thread branch information in a graphics processor, which solves the technical problem of instruction cache misses caused by poor spatial locality of instructions in the prior art.

[0007] The embodiments of this specification provide the following technical solutions:

[0008] An embodiment of this specification provides a prefetching method based on thread branch information in a graphics processor, including:

[0009] Step 1: Determine context information of the first instruction pointer based on the first top instruction pointer of the branch stack and the first top instruction pointer at the first moment;

[0010] Step 2: Perform an XOR operation on the first stack top instruction pointer and the first stack top instruction pointer, and then perform hash coding to obtain the first index corresponding to the first instruction pointer;

[0011] Step 3: Establish a missing table corresponding to the branch stack based on the context information and the second index, where the second index is the previous index of the first index, and the second index is obtained by performing a hash code after performing an XOR operation on the second top instruction pointer of the branch stack at the second moment and the second top instruction pointer, and the second moment is the moment before the first moment;

[0012] Step 4: Each time the graphics processor executes the second top instruction pointer of the branch stack, the missing instruction pointers in the time period corresponding to the first instruction pointer are pre-fetched according to the missing table. The missing instruction pointers are obtained according to the context information.

[0013] Preferably, step 3 includes:

[0014] Step 301: Determine whether a first instruction pointer has an instruction cache miss based on context information;

[0015] Step 302: If yes, store the missing instruction pointer corresponding to the instruction cache miss in the storage unit corresponding to the second index;

[0016] Step 303: If not, continue executing the next instruction pointer.

[0017] Preferably, step 4 includes:

[0018] Step 401: Each time the graphics processor executes the second top stack instruction pointer, it is determined based on the miss table and the second index whether there is an instruction cache miss within the time period corresponding to the first instruction pointer;

[0019] Step 402: If yes, prefetch the missing data according to the missing instruction pointer corresponding to the instruction cache miss, and record the prefetch hit status;

[0020] Step 403: If not, instruction prefetching is not required.

[0021] Preferably, one storage unit includes multiple missing instruction pointers.

[0022] Preferably, after step 402, the method further includes:

[0023] Step 404: Update the pointer of the missing instruction in the storage unit according to the prefetch hit condition.

[0024] Preferably, the storage unit adopts a ring-shaped first-in-first-out stack structure.

[0025] Preferably, the prefetch hit conditions include: prefetch hit and prefetch miss. Step 404 includes:

[0026] Step 4041: When the number of prefetch misses is greater than a preset threshold, the corresponding missing instruction pointer is invalidated;

[0027] Step 4042: When the number of prefetch misses is less than or equal to the preset threshold, no invalidation processing is performed on the missing instruction pointer.

[0028] An embodiment of this specification further provides a prefetching system based on thread branch information in a graphics processor, comprising:

[0029] Module M1: determining context information of the first instruction pointer according to the first top instruction pointer of the branch stack and the first top instruction pointer at the first moment;

[0030] Module M2: performing an XOR operation on the first stack top instruction pointer and the first stack top instruction pointer, and then performing hash coding to obtain a first index corresponding to the first instruction pointer;

[0031] Module M3: Establish a missing table corresponding to the branch stack based on the context information and a second index, where the second index is the previous index of the first index, and the second index is obtained by performing a hash code after performing an XOR operation on the second top instruction pointer of the branch stack and the second top instruction pointer at the second moment, and the second moment is the moment before the first moment;

[0032] Module M4: Each time the graphics processor executes the second top instruction pointer of the branch stack at the second moment, prefetch the missing instruction pointers in the time period corresponding to the first instruction pointer according to the missing table, where the missing instruction pointers are obtained according to the context information.

[0033] Preferably, module M3 includes:

[0034] Submodule M301: determining, based on context information, whether the first instruction pointer has an instruction cache miss;

[0035] Submodule M302: If yes, store the missing instruction pointer corresponding to the instruction cache miss in the storage unit corresponding to the second index;

[0036] Submodule M303: If not, continue executing the next instruction pointer.

[0037] Preferably, module M4 includes:

[0038] Submodule M401: Each time the graphics processor executes the second top stack instruction pointer, it is determined based on the miss table and the second index whether there is an instruction cache miss in the time period corresponding to the first instruction pointer;

[0039] Submodule M402: If yes, prefetch the missing data according to the missing instruction pointer corresponding to the instruction cache miss, and record the prefetch hit status;

[0040] Submodule M403: If not, instruction prefetching is not required.

[0041] Compared with the prior art, the beneficial effects achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least the following: determining the context information of the first instruction pointer based on the first top instruction pointer and the first top instruction pointer of the branch stack, the first instruction pointer being the branch instruction currently being executed, and determining which branch code blocks the current instruction pointer is between, thereby obtaining the current context position information, which is more accurate than other prefetching technologies, and the information it relies on is the global context information of the program, which is clearer and more reliable, and effectively reduces the design complexity; establishing a miss table based on the context information, and performing instruction prefetching at the moment before the current moment through the miss table, which can effectively reduce the instruction cache miss caused by locality problems between branch instructions in the graphics processor, and improve the running speed of the graphics processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0043] Figure 1 This is a flow chart of execution branching in a 4-thread graphics processor in this application;

[0044] Figure 2 This is a schematic diagram of the structure of a branch stack in this application;

[0045] Figure 3This is a schematic diagram of a prefetching method based on thread branch information in a graphics processor in this application. DETAILED DESCRIPTION

[0046] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0047] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0048] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0049] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0050] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples, however, one skilled in the art will appreciate that the examples can be practiced without these specific details.

[0051] Currently, GPUs typically use predicates to execute branches serially, using masks to selectively execute threads within a warp. The GPU stores information such as the Next PC, current mask, and reconvergence instruction pointer (PC) in a branch stack (IPDOM). The branch stack grows downward, with the most recently pushed data at the bottom. When a branch instruction is encountered, the starting instruction pointer (PC), current mask, and reconvergence instruction pointer (PC) corresponding to the currently executing branch are pushed in. After the branch is completed, the data is popped out or updated based on whether the reconvergence point has been reached.

[0052] Current prefetching techniques overlap computation and memory access, issuing prefetch requests before cache misses occur. This allows data blocks to be cached before they are actually needed, thus avoiding processor stalls caused by cache misses. GPUs, when encountering cache misses, mask pipeline stalls caused by cache misses by switching warps using the warp scheduler.

[0053] In light of this, the inventors conducted in-depth research and improved exploration of various websites, web page structures, and page information, as well as various extraction schemes. They discovered that the problem of instruction cache misses remains poorly optimized for individual tasks. Because all branch directions must be executed, instructions for certain directions may not be in the instruction cache due to poor spatial locality, resulting in cache misses. When there are many branch instructions, switching thread warps may not fully mitigate latency, thus affecting processor performance.

[0054] Based on this, an embodiment of this specification proposes a processing solution: a corresponding miss table is established based on the information in the branch stack. When the graphics processor executes a branch instruction, the miss table can predict the address where the instruction cache miss will occur and prefetch the instruction. When the corresponding instruction with an instruction cache miss is executed, the prefetched data can be directly used, avoiding the occurrence of instruction cache misses and improving the processing speed and performance of the graphics processor.

[0055] The following describes the technical solutions provided by various embodiments of the present application in conjunction with the accompanying drawings.

[0056] like Figure 3 As shown, an embodiment of this specification provides a prefetching method based on thread branch information in a graphics processor, including:

[0057] Step 1: Determine context information of the first instruction pointer based on the first top instruction pointer of the branch stack at the first moment and the first top instruction pointer.

[0058] The first moment refers to the current moment, that is, the moment when the current graphics processor is executing.

[0059] Specifically, the branch stack grows downward, so the bottom of the stack is the most recently pushed data, that is, the first top instruction pointer refers to the instruction pointer referred to by Next pc at the bottom of the branch stack at the current moment, and the first top instruction pointer refers to the instruction pointer adjacent to the first top instruction pointer and located above the first top instruction pointer in the branch stack.

[0060] Since the branch stack is in a downward growth form, the data in the branch stack is different at each moment. The position information of the currently executing instruction pointer can be determined based on the top pointer and the next top pointer in the branch stack at the corresponding moment.

[0061] For example, Figure 3 As shown, the first top-of-stack instruction pointer and the second top-of-stack instruction pointer correspond to B and C in the figure respectively. The context information of the first instruction pointer can be determined based on B and C. The context information relied on by this application is the global context information of the program, which is clearer and more reliable, effectively reduces the design complexity, and has higher accuracy than other prefetching technologies.

[0062] Step 2: Perform an XOR operation on the first stack top instruction pointer and the first stack top instruction pointer, and then perform hash coding to obtain a first index corresponding to the first instruction pointer.

[0063] Specifically, for each moment, the top instruction pointer and the second top instruction pointer in the branch stack are XORed and hashed to obtain the corresponding index. For example, for the branch stack at the first moment, the first top instruction pointer and the first top instruction pointer are XORed and hashed to obtain the first index corresponding to the first instruction pointer.

[0064] Furthermore, for each moment, the current index corresponding to the instruction pointer being executed at the current moment can be obtained.

[0065] It can be seen that the present application does not impose any specific restrictions on the method of obtaining the first index. The XOR operation and hash coding mentioned are only exemplary methods. In actual applications, the first index corresponding to the first top of stack instruction pointer and the first top of stack instruction pointer, or the first index corresponding to the first instruction pointer, can be obtained by other methods, all of which are within the scope of protection of the present application.

[0066] Step 3: Create a missing table corresponding to the branch stack based on the context information and the second index.

[0067] Among them, the second index is the previous index of the first index, the second index is obtained by performing a hash encoding after performing an XOR operation on the second top instruction pointer of the branch stack at the second moment and the second top instruction pointer, and the second moment is the moment before the first moment.

[0068] Specifically, based on the context information obtained above, it can be determined whether there is an instruction cache miss within the time period of the first instruction pointer. If so, the missing instruction pointer is stored in the storage unit corresponding to the second index in the miss table, so that when the first instruction pointer is executed, the missing instruction pointer corresponding to the instruction cache miss can be pre-fetched in advance, thereby overcoming the problem of poor spatial locality of instructions and improving the performance of the graphics processor.

[0069] Step 4: Each time the graphics processor executes the second top instruction pointer of the branch stack, the missing instruction pointer in the event segment corresponding to the first instruction pointer is pre-fetched according to the missing table. The missing instruction pointer is obtained according to the context information.

[0070] Specifically, steps 1 to 3 involve establishing a corresponding miss table based on the branch stack when the program or thread is first executed. Once established, when a newly switched thread warp or the same thread warp reaches the instruction pointer at the top of the first stack, the present application can prefetch the corresponding address of the next segment where an instruction cache miss will occur. That is, the corresponding address of the first segment where an instruction cache miss will occur can be prefetched at the second moment. Then, by prefetching the missing data based on the address where the instruction cache miss will occur, this can effectively reduce instruction cache misses caused by locality issues between branch instructions in the graphics processor, thereby improving the operating speed of the graphics processor.

[0071] It is known that the index used in this application is the index of the previous stack top pointer and the previous stack top pointer. There are two parallel links in this application. One is that whenever the stack top pointer changes, the stack top instruction pointer before the change and the second stack top instruction pointer are hashed after the XOR operation to have a position as the index. Then, according to the missing situation of the instruction cache after the change, it is decided whether to store the missing table and the missing content, that is, the missing instruction corresponding instruction pointer (pc); the other is to find whether the missing instruction pointer (pc) has been stored in the missing table before according to the index obtained by hashing the current stack top instruction pointer and the second stack top instruction pointer after the XOR operation. If so, pre-fetch. One is a write operation to the missing table and the other is a read operation. When the stack top instruction pointer changes, they will be executed in parallel.

[0072] In an optional embodiment, step 3 includes: step 301: determining whether there is an instruction cache miss for the first instruction pointer based on context information; step 302: if so, storing the missing instruction pointer corresponding to the instruction cache miss in the storage unit corresponding to the second index; step 303: if not, continuing to execute the next instruction pointer.

[0073] Specifically, when determining based on context information whether there is an instruction cache miss within the time period corresponding to the first instruction pointer corresponding to the first index, in order to pre-fetch the corresponding missing instruction pointer in advance when the first instruction pointer is executed again, the missing instruction pointer is stored in the storage unit of the second index obtained at the previous moment in the missing table in this application, so that when the second top stack instruction pointer is executed later, the missing instruction pointer corresponding to the first instruction pointer can be pre-fetched, and the missing data corresponding to the missing instruction pointer can be pre-fetched.

[0074] It is known that in this application, instruction prefetching can be performed at multiple times in advance without any limitation.

[0075] Furthermore, step 4 includes: step 401: each time the graphics processor executes the second top-of-stack instruction pointer, determining whether there is an instruction cache miss within the time period corresponding to the first instruction pointer based on the miss table and the second index; step 402: if yes, prefetching the missing data based on the missing instruction pointer corresponding to the instruction cache miss, and recording a prefetch hit; step 403: if no, no instruction prefetching is required.

[0076] Specifically, after the miss table is established, when the second stack top instruction pointer is executed again, it is determined whether there is an instruction cache miss in the time period corresponding to the first instruction pointer based on the miss table and the second index. If so, the missing data is prefetched according to the missing instruction pointer and the prefetch hit is recorded; if not, there is no need to prefetch the instruction. In practical applications, such as Figure 3 As shown, during the first execution, the latest Next pc (B in the figure) and the second latest Next pc (C in the figure) are derived from the current moment of the IPDOM stack, and after XOR operation, they are hashed to form the current index of the current missing table. At the same time, the previous index before the last change is stored. When an instruction cache miss occurs, the missing instruction pointer is stored in the missing table according to the previous index; when the previous index is executed again, the previous index confirms in the missing table whether there is an instruction cache miss at the current index, that is, whether there is data in the storage unit corresponding to the previous index in the missing table. If so, the missing instruction pointer is taken out, and the data corresponding to the missing instruction pointer is prefetched from the memory through a prefetch request to implement instruction prefetch, and the prefetch hit situation is recorded.

[0077] After step 402, the present application further includes: step 404: updating the missing instruction pointer in the storage unit according to the prefetch hit situation.

[0078] In the present application, the prefetch hit situations include: prefetch misses and prefetch hits. When prefetching instructions based on the missing instruction pointer, the prefetch hit situation is judged. If the prefetch hits, there is no need to update the missing instruction pointer in the storage unit. If the prefetch misses, the number of prefetch misses is recorded. Step 404 includes: Step 4041: When the number of prefetch misses is greater than a preset threshold, the corresponding missing instruction pointer is invalidated; Step 4042: When the number of prefetch misses is less than or equal to the preset threshold, the missing instruction pointer is not invalidated.

[0079] Specifically, when the number of prefetch misses reaches a preset threshold, the missing instruction pointer of the corresponding index is invalidated, and the remaining missing addresses are rearranged in order.

[0080] In an optional embodiment, a storage unit includes multiple missing instruction pointers, and the storage unit adopts a circular first-in-first-out stack structure. Figure 3 As shown, in the storage unit corresponding to index 4, there are multiple missing instruction pointers, address 1, address 2 and address 3. A storage unit can also have a missing instruction pointer. For example, there is an instruction missing address in index 3, address 4. A storage unit may also have no missing instruction pointer, indicating that there is no instruction cache missing in the instruction pointer of the index corresponding to the storage unit at the next moment, and there is no need to prefetch instructions.

[0081] In order to record multiple instruction cache misses for a branch area, the present application uses a circular first-in, first-out (FIFO) structure in the storage unit of the miss table to prefetch the missing addresses in sequence and record the prefetch hit status of these missing addresses.

[0082] The missing table is searched for data in the previous index. If data exists, it is pre-fetched in the order of the data and the pre-fetch hits are recorded. When the number of pre-fetch misses reaches a threshold, the missing address of the corresponding index is invalidated and the remaining missing addresses are rearranged in order. If the missing table is full for an index, no new missing instruction pointers are added until the corresponding entry contains an invalid entry.

[0083] An embodiment of this specification further provides a prefetching system based on thread branch information in a graphics processor, comprising:

[0084] Module M1: Determine context information of the first instruction pointer according to the first top instruction pointer of the branch stack and the first top instruction pointer at the first moment.

[0085] Module M2: Perform an XOR operation on the first stack top instruction pointer and the first stack top instruction pointer, and then perform hash coding to obtain a first index corresponding to the first instruction pointer.

[0086] Module M3: Establish a missing table corresponding to the branch stack based on the context information and the second index, where the second index is the previous index of the first index, and the second index is obtained by performing a hash encoding after performing an XOR operation on the second top instruction pointer of the branch stack at the second moment and the second top instruction pointer, and the second moment is the moment before the first moment.

[0087] In an optional embodiment, module M3 includes: sub-module M301: determining whether there is an instruction cache miss for the first instruction pointer based on context information; sub-module M302: if so, storing the missing instruction pointer corresponding to the instruction cache miss in the storage unit corresponding to the second index; sub-module M303: if not, continuing to execute the next instruction pointer.

[0088] Module M4: Each time the graphics processor executes the second top instruction pointer of the branch stack at the second moment, prefetch the missing instruction pointers in the time period corresponding to the first instruction pointer according to the missing table, where the missing instruction pointers are obtained according to the context information.

[0089] In an optional embodiment, module M4 includes: sub-module M401: each time the graphics processor executes the second top-of-stack instruction pointer, determining whether there is an instruction cache miss within the time period corresponding to the first instruction pointer based on the miss table and the second index; sub-module M402: if so, prefetching the missing data based on the missing instruction pointer corresponding to the instruction cache miss and recording a prefetch hit; sub-module M403: if not, not performing instruction prefetching.

[0090] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the product embodiments described later are relatively simple to describe because they correspond to the methods. For relevant parts, refer to the description of the system embodiments.

[0091] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A prefetching method based on thread branch information in a graphics processor, characterized in that: include: Step 1: Determine context information of the first instruction pointer based on the first top instruction pointer of the branch stack and the first top instruction pointer at the first moment; Step 2: Perform an XOR operation on the first stack top instruction pointer and the first stack top instruction pointer, and then perform hash coding to obtain a first index corresponding to the first instruction pointer; Step 3: Establish a missing table corresponding to the branch stack according to the context information and a second index, where the second index is the previous index of the first index, and the second index is obtained by performing a hash code after performing an XOR operation on the second top instruction pointer and the second top instruction pointer of the branch stack at the second moment, and the second moment is the moment before the first moment; Step 4: Each time the graphics processor executes the second top instruction pointer of the branch stack, prefetch missing instruction pointers within the time period corresponding to the first instruction pointer according to the missing table, wherein the missing instruction pointers are obtained according to the context information.

2. The prefetching method based on thread branch information in a graphics processor according to claim 1, characterized in that: The step 3 comprises: Step 301: Determine whether the first instruction pointer has an instruction cache miss based on the context information; Step 302: If yes, store the missing instruction pointer corresponding to the instruction cache miss in the storage unit corresponding to the second index; Step 303: If not, continue executing the next instruction pointer.

3. The prefetching method based on thread branch information in a graphics processor according to claim 2, characterized in that: The step 4 comprises: Step 401: Each time the graphics processor executes the second top-of-stack instruction pointer, determine, based on the miss table and the second index, whether there is an instruction cache miss within the time period corresponding to the first instruction pointer; Step 402: If yes, prefetch the missing data according to the missing instruction pointer corresponding to the instruction cache miss, and record the prefetch hit status; Step 403: If not, instruction prefetching is not required.

4. The prefetching method based on thread branch information in a graphics processor according to claim 2, characterized in that: One of the storage units includes a plurality of missing instruction pointers.

5. The prefetching method based on thread branch information in a graphics processor according to claim 3, characterized in that: After step 402, the method further includes: Step 404: Update the pointer of the missing instruction in the storage unit according to the prefetch hit condition.

6. The prefetching method based on thread branch information in a graphics processor according to claim 4, characterized in that: The storage unit adopts a ring-shaped first-in-first-out stack structure.

7. The prefetching method based on thread branch information in a graphics processor according to claim 5, characterized in that: The prefetch hit condition includes: prefetch hit and prefetch miss. Step 404 includes: Step 4041: When the number of prefetch misses is greater than a preset threshold, the corresponding missing instruction pointer is invalidated; Step 4042: When the number of prefetch misses is less than or equal to the preset threshold, the missing instruction pointer is not invalidated.

8. A prefetch system based on thread branch information in a graphics processor, characterized in that: include: Module M1: determining context information of the first instruction pointer according to the first top instruction pointer of the branch stack and the first top instruction pointer at the first moment; Module M2: performing an XOR operation on the first stack top instruction pointer and the first stack top instruction pointer, and then performing hash coding to obtain a first index corresponding to the first instruction pointer; Module M3: establishing a missing table corresponding to the branch stack according to the context information and a second index, where the second index is the previous index of the first index, and the second index is obtained by performing a hash code after performing an XOR operation on the second top instruction pointer and the second top instruction pointer of the branch stack at the second moment, and the second moment is the moment before the first moment; Module M4: Each time the graphics processor executes the second top instruction pointer of the branch stack at the second moment, prefetch the missing instruction pointer within the time period corresponding to the first instruction pointer according to the missing table, wherein the missing instruction pointer is obtained according to the context information.

9. The prefetching system based on thread branch information in a graphics processor according to claim 8, characterized in that: The module M3 includes: Submodule M301: determining, based on the context information, whether the first instruction pointer has an instruction cache miss; Submodule M302: If yes, store the missing instruction pointer corresponding to the instruction cache miss in the storage unit corresponding to the second index; Submodule M303: If not, continue executing the next instruction pointer.

10. The prefetching system based on thread branch information in a graphics processor according to claim 9, characterized in that: The module M4 includes: Submodule M401: each time the graphics processor executes the second stack top instruction pointer, determining whether there is an instruction cache miss within a time period corresponding to the first instruction pointer based on the miss table and the second index; Submodule M402: If yes, prefetch the missing data according to the missing instruction pointer corresponding to the instruction cache miss, and record the prefetch hit situation; Submodule M403: If not, instruction prefetching is not required.

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