Method and system for mitigating stall in iterative decoder

Abstract

Methods, systems, and apparatus for mitigating stalls in an iterative decoder are described. A codeword is received from a memory device. The codeword is repeatedly error corrected based on a first bit flip criterion. A stall condition is detected in a plurality of error correction iterations. In response to the detection, the codeword is error corrected based on a second bit flip criterion different from the first bit flip criterion.

Description

Technical Field

[0001] The present disclosure relates generally to error correction in memory subsystems, and more particularly to methods and systems for mitigating stalls in iterative decoders. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may use the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] According to one aspect of the present disclosure, a method is provided. The method includes: receiving a codeword from a memory device; repeatedly error-correcting the codeword in multiple iterations based on a first bit flip criterion; detecting a stall condition in the multiple iterations; and in response to the detection, error-correcting the codeword based on a second bit flip criterion different from the first bit flip criterion.

[0004] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions that, when executed by a processing device, cause the processing device to: receive a codeword from a memory device; repeatedly error-correct the codeword in multiple iterations based on a first bit flip criterion; detect a stall condition in the multiple iterations; and in response to the detection, error-correct the codeword based on a second bit flip criterion different from the first bit flip criterion.

[0005] According to another aspect of the present disclosure, a system is provided. The system includes: a memory device; and a processing device operatively coupled to the memory device to: receive a codeword from the memory device; repeatedly error-correct the codeword in multiple iterations based on a first bit flip threshold, wherein error correction of the codeword in iterations from the multiple iterations includes flipping one or more bits of the codeword that satisfy the first bit flip threshold; detect a stall condition in the multiple iterations; and in response to the detection, error-correct the codeword based on a second bit flip threshold different from the first bit flip threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2ABlock diagram illustrating an exemplary codeword subject to error correction based on operation of an error corrector in accordance with some embodiments of the present disclosure.

[0009] Figure 2B Block diagram illustrating exemplary values ​​of bits of a codeword structure that may take over multiple iterations of an error corrector in accordance with some embodiments.

[0010] Figure 3 A block diagram illustrating an exemplary table containing stall patterns detected during error correction of a codeword in accordance with some embodiments.

[0011] Figure 4 Flowchart of an example method for enabling mitigation of stall in an iterative decoder according to some embodiments of the present disclosure.

[0012] Figure 5 Flowchart of another example method of enabling mitigation of stall in an iterative decoder according to some embodiments of the present disclosure.

[0013] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to methods and systems for mitigating stalls in an iterative decoder of a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0015] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. A die in a package may be assigned to one or more channels for communicating with a memory subsystem controller. Each die may consist of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane consists of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0016] Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits being stored. The logical states can be represented by binary values ​​such as "0" and "1" or a combination of these values. There are various types of cells such as single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC). For example, an SLC can store one bit of information and have two logical states.

[0017] Low density parity check (LDPC) codes are commonly used to implement error correction in memory subsystems. LDPC codes are a class of efficient linear block codes that include single parity check (SPC) codes. LDPC codes have high error correction performance and can provide performance close to the channel capacity. The MinSum algorithm (MSA), which is a simplified version of the belief propagation algorithm, can be used to decode LDPC codes. However, decoders based on MSA use relatively high amounts of energy per bit (picojoules per bit) to decode codewords, and are therefore less suitable for energy-conscious applications (such as mobile applications). Bit flip (BF) decoders have been introduced to solve this problem. When compared to the error correction performance of decoders based on MSA, BF decoders use less energy per bit at the expense of providing lower error correction performance. Lower error correction performance is an obstacle to deploying BF decoders to replace decoders based on MSA. In addition, BF decoders may fall into a stall / oscillation state, in which additional iterations of the decoder cannot cause the BF decoder to exit this stall state.

[0018] The BF decoder defines an energy function for one bit of a codeword. The energy function assigns an energy level to each codeword bit. The energy function of a codeword bit can be considered as an indication of the reliability information of the codeword bit. The energy function of a codeword bit can be determined based on the number of parity violations per codeword bit (e.g., a higher number of parity violations is a sign of a bit with lower reliability) and channel information. Channel information is determined based on the current state of the bit (after one or more iterations of the BF decoder) relative to the bit read from the memory device. When the current state of the bit is consistent with the bit read from the memory device, the bit is considered more reliable. The BF decoder flips the least reliable bit first. When a higher energy function corresponds to a more reliable bit, the BF decoder can operate to maximize the energy function of each bit and reach a global maximum. However, the BF decoder may get stuck in a local maximum and fail to reach a global maximum. In this case, the BF decoder begins to oscillate between multiple states, that is, for several consecutive iterations, the decoder moves from one state to another in an iteration cycle. The BF decoder oscillates between multiple states by repeating the stall mode, thereby generating a high error floor.

[0019] Error flooring is a phenomenon encountered in some iterative error correction codes (e.g., LDPC codes). When plotting the codeword error rate (CWER) or bit error rate (BER) of an LDPC code, the CWER / BER decreases steadily in a curve as the signal-to-noise ratio condition improves. The CWER corresponds to the rate (probability) at which the LDPC decoder fails to correct errors in the codeword. For LDPC codes, there is a point after which the curve does not drop as quickly as before, in other words, there is an area where the performance flattens out. This area is called the error floor area. The error floor of the decoder is an indicator of the performance of the subsystem using the decoder. For example, a BF decoder of a memory subsystem with a high error floor affects the quality of service (QoS) and latency of the memory subsystem. In fact, even when the original bit error rate (RBER) is low, a BF decoder with a high error floor triggers error handling operations, which causes worse QoS and higher latency.

[0020] Aspects of the present disclosure address the above and other deficiencies by improving the BF decoder. The embodiments presented herein detect stall conditions in multiple iterations of the BF decoder and modify the bit flip criteria for correcting the erroneous bits of the codeword. The embodiments described herein enable the decoder to exit the stall state. In addition, the embodiments herein reduce the error floor of the BF decoder and significantly improve the performance of the memory subsystem.

[0021] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0022] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0023] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0024] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0025] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0026] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0027] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Although nonvolatile memory devices such as NAND type memory (e.g., 2D NAND, 3D NAND) and 3D cross-point nonvolatile memory cell arrays are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (or, for simplicity, the controller 115) may communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130 (e.g., in response to commands dispatched by the controller 115 on a command bus). The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0031] The memory subsystem controller 115 may include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0032] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem 110).

[0033] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0036] The memory subsystem 110 includes an error corrector 113 that implements the method of stall mitigation. In some embodiments, the controller 115 includes at least a portion of the error corrector 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the error corrector 113 is part of a host system 120, an application, or an operating system.

[0037] In some embodiments, the error corrector 113 is operable to encode and decode data stored in a memory device (e.g., an encoder and / or decoder). When data is retrieved from the memory device, encoding the data using an error correction code (ECC) allows correction of erroneous data bits. For example, the error corrector 113 may encode data received from the host system 120 and store the data and parity bits as a codeword in the memory device 130. The error corrector 113 may further be operable to decode the data stored in the memory device 130 before transmitting the corrected data to the host system 120 to identify and correct the erroneous bits of the data. Although illustrated as a single component that can perform encoding and decoding of data, the error corrector 113 may be provided as a separate component. In some embodiments, the error corrector 113 is operable to encode the data according to a low density parity check (LDPC) code. The error corrector 113 is operable to decode the codeword stored in the memory device 130 based on a BF decoder. As described below, error corrector 113 implements an enhanced BF decoder that can mitigate stalling of the decoding scheme.

[0038] Error corrector 113 receives a codeword from a memory device (e.g., memory device 130 or memory device 140) and attempts to correct the codeword in multiple iterations based on a first bit flip criterion. In response to error corrector 113 detecting a stall condition in multiple iterations, error corrector 113 attempts to correct the codeword based on a second bit flip criterion different from the first bit flip criterion. Additional details about the operation of error corrector 113 are described below.

[0039] Figure 2A Block diagram illustrating an exemplary code structure 200 for error correction based on operation of the error corrector 113 according to some embodiments of the present disclosure. Figure 2A Multiple states of the same structure are shown, such as states 200A, 200B, 200C, 200D, and 200E. The states of the structure include an initial state or are generated by iterations of the error corrector 113. Structure 200 is an exemplary structure that fails under a conventional BF decoder (i.e., causes the conventional BF decoder to oscillate indefinitely). Structure 200 includes data bits and parity checks. Circles (e.g., circles 1, 2, 3, 4, 5, and 6) represent data bits, and squares (e.g., square 204A and square 206A) represent parity checks. Shaded circles represent erroneous bits, such as circles 4, 5, and 6 in state 200A, and black squares represent failed (not satisfied) parity checks, while unshaded circles represent correct bits, such as circles 1, 2, 3 in state 200A, and unshaded squares represent satisfied parity checks, such as square 204A.

[0040] Figure 2AWill be through from Figure 2B Example bit value descriptions of Tables 230A to C. Figure 2B Block diagram illustrating exemplary values ​​of bits of structure 200 over multiple iterations of error corrector 113 according to some embodiments. Tables 230A, 230B, and 230C include columns 231, 232, and 233 containing values ​​that remain constant over multiple iterations of error corrector 113. Column 231 contains identifiers for bits 1, 2, 3, 4, 5, and 6. Column 232 contains the correct values ​​for the bits. Column 233 contains the values ​​of the bits as read from a memory device. Each of tables 230A, 230B, and 230C includes columns containing current values ​​of the bits after the most recent iteration of error correction, columns 234A, 234B, and 234C, respectively. Each of tables 230A, 230B, and 230C includes: columns containing channel information for the bits, columns 235A, 235B, and 235C, respectively; and columns containing energy function values ​​for the bits, columns 236A, 236B, and 236C, respectively.

[0041] To correct the error, the error corrector 113 should flip the erroneous bits 4, 5, and 6. The error corrector 113 determines the energy function (column 236A) of each of the bits and flips the bits according to the energy function and the bit flipping criterion. To determine the energy function of the bit, the error corrector 113 may determine the channel information (column 235A) of the bit, the number of parity checks that are satisfied for the bit, and the number of parity checks that fail for the bit.

[0042] In some embodiments, the error corrector 113 determines the channel information of the bits according to the non-limiting example of equation (1):

[0043] Channel information (bit) = 1-2*(CurrentState (bit) XOR StateReadFromMemory (bit))(1)

[0044] Where CurrentState(bit) is the state of the bit produced by the most recent iteration of the error corrector 113 (column 234A), and StateReadFromMemory(bit) is the state of the bit as read from memory (column 233A). According to equation (1), when the current state of the bit is equal to the state of the bit as read from memory, the channel information is 1, and when the current state of the bit is different from the state of the bit as read from memory, the channel information is -1.

[0045] The error corrector 113 determines an energy function based at least in part on the determined channel information. In a non-limiting example, the energy function may be determined according to equation (2):

[0046] e (bits) = NumberSatisfiedParities (bits) - NumberFailedParities (bits) + ChannelInformation (bits) (2)

[0047] exist Figure 2A , the initial bit flip criterion (e.g., e(bit) is less than or equal to 0) causes bits 1, 2, 3 to be flipped, and the state of the code structure moves from 200A to 200B, even though bits 1, 2, and 3 are correct and bits 4, 5, and 6 are erroneous. These are erroneous flips. When the decoder (e.g., error corrector 113) iterates to the code structure in state 200B based on the energy function and the initial flip criterion, the decoder flips bits 1, 2, and 3 without flipping erroneous bits 4, 5, and 6. From this iteration, a structure in state 200C is obtained, wherein the structure in state 200C is identical to the structure in state 200A and can cause the error corrector 113 to oscillate, repeatedly generating a decoding pattern (stall condition) of the structure from state 200B to 200C. This is described in further detail below. Figure 2A Each of the error correction iterations described in , includes a fix for this stall condition.

[0048] In the structure of state 200A, bits 4, 5, and 6 are erroneous, and bits 1, 2, and 3 are correct. Furthermore, in the structure of state 200A, each of bits 4, 5, and 6 is identical to its corresponding bit in the codeword, as read from memory. For bits 4, 5, and 6, there is a channel match between the current state of the bit and the bit read from memory. Bits 1, 2, and 3 are not erroneous, but the bit read from memory is inconsistent with the current state of the bit, i.e., bits 1, 2, and 3 are erroneously read from the memory device. For bits 1, 2, and 3, there is a channel mismatch between the current state of the bit and the bit read from memory.

[0049] In a non-limiting example, the error corrector 113 is based on equation (2) and Figure 2BThe values ​​described in determine the energy function of bits 1, 2, 3, 4, 5, and 6. In state 200A, each of bits 1, 2, and 3 has the same number of failed parity checks (1) and the same number of satisfied parity checks (2). In addition, the channel information of each of bits 1, 2, and 3 is -1 because the current state of the bit is inconsistent with the state of the bit read from the memory. The energy function of each of the bits of circles 1, 2, and 3 is e(1:3)=2-1-1=0 (column 236A). In the structure of state 200A, bits 4, 5, and 6 have the same number of satisfied parity checks (2) and the same number of failed parity checks (1 failed parity check). The channel information of bits 4, 5, and 6 is 1 because the current state of the bit is consistent with the state of the bit read from the memory. The energy function of bits 4, 5, and 6 is e(4:6)=2-1+1=2. Therefore, although bits 4, 5, and 6 are erroneous in the structure of state 200A, the energy function of bits 1, 2, and 3 is lower than the energy function of bits 4, 5, and 6, indicating that bits 1, 2, and 3 are less reliable than bits 4, 5, and 6.

[0050] The error corrector 113 flips codeword bits 1, 2, and 3 that are not erroneous based on the initial bit flip criterion. The bit flip criterion may be a bit flip threshold. For example, a bit flip threshold of 0 may be selected, and the error corrector flips the bit when the energy function of the bit is less than or equal to the bit flip threshold. According to the initial bit flip criterion, bits 4, 5, and 6 are considered more reliable than bits 1, 2, and 3, even though bits 4, 5, and 6 are erroneous and bits 1, 2, and 3 are correct, because the states of bits 4, 5, and 6 are the same as the states read from the memory, making their corresponding energy functions greater than the bit flip threshold. The result of the iteration of the error corrector is a structure of state 200B.

[0051] During a subsequent iteration, the error corrector 113 determines the energy functions of bits 1, 2, 3, 4, 5, and 6 (e.g., column 236B, where e(1:3)=1-2+1=0; e(4:6)=3+1=4). Based on these energy functions and the same first bit flip criterion (e.g., bit flip threshold 0), the error corrector 113 again flips bits 1, 2, and 3, but not bits 4, 5, and 6, because the energy functions of bits 1, 2, and 3 continue to indicate that their reliability is lower than that of bits 4, 5, and 6 (e(1:3) is less than or equal to the bit flip threshold, while e(4:6) is greater than the bit flip threshold). From this iteration, the structure of state 200C is obtained, where the structure of state 200C is the same as the structure of state 200A and can cause the error corrector 113 to oscillate, repeatedly generating a decoding pattern (stall condition) of the structure of states 200B to 200C.

[0052] The error corrector 113 detects this stall condition (as described herein) and modifies the bit flip criteria. For example, the error corrector 113 modifies the bit flip criteria by increasing the bit flip threshold to 2 so that bits with an energy function less than or equal to 2 are flipped. The bit flip criteria are relaxed to flip more bits than the number of bits flipped based on the initial bit flip criteria. The updated bit flip criteria causes bits 1, 2, 3, 4, 5, and 6 to flip and obtain an updated structure of state 200D. Therefore, in this iteration (when the error corrector operates on the structure of state 200C), when the energy function of the bits has not changed, column 236A, where e(1:3)=0 and e(4:6)=2, the modification of the bit flip criteria (e.g., the bit flip threshold is increased to 2) causes bits 1, 2, 3, 4, 5, and 6 to flip because they all meet the bit flip criteria (e(1:3) is less than 2, e(4:6) is equal to 2). The iteration of the error corrector 113 produces the structure of state 200D.

[0053] During the following iteration, the error corrector 113 determines the energy function of bits 1, 2, 3, 4, 5, and 6 for the structure of state 200D. Each of bits 1, 2, and 3 has 3 failed parity checks, no satisfied parity checks, and its current state is consistent with the state read from the memory, resulting in the channel information being -1. The energy function of bits 1, 2, and 3 is e(1:3)=0-3+1=-2 (column 236C). Each of bits 4, 5, and 6 has 2 satisfied parity checks, 1 failed parity check, and its current state is inconsistent with the bit read from the memory, resulting in the channel information being -1. The energy function of each of bits 4, 5, and 6 is e(4:6)=2-1-1=0. The error corrector 113 flips bits 1, 2, and 3, but does not flip bits 4, 5, and 6 because the energy function of bits 1, 2, 3 satisfies the bit flip criterion, and the energy function of bits 4, 5, 6 does not satisfy the bit flip criterion. In some embodiments, the bit flip criterion used in this iteration from the structure of state 200D to the structure of state 200E is a further updated bit flip criterion (e.g., threshold = -2). The structure of state 200E is produced by this iteration, in which all parity checks are satisfied, indicating that bits 1, 2, 3, 4, 5, and 6 are corrected and the error corrector stops iterating. In some embodiments, the error corrector 113 uses the updated bit flip criterion for a limited number of iterations, and the following iterations (e.g., from the structure of state 200D to the structure of state 200E) may be performed based on the initial bit flip criterion rather than the updated bit flip criterion or based on the further updated bit flip criterion. In other words, relaxing the bit flip criterion for one or more iterations when the decoder is in a stall condition helps the decoder get out of the stall condition.

[0054] Figure 3Block diagram illustrating an exemplary table containing stall modes detected during error correction of a codeword in accordance with some embodiments. Error corrector 113 decodes the codeword, attempting to correct errors for a number of iterations. As an example, table 300 shows syndromes at the beginning and end of an iteration of error corrector 113. The syndrome indicates the number of erroneous parity checks in the codeword. At an initial iteration 0, the syndrome at the beginning of the iteration is 504, and the syndrome at the end of the iteration is 200. Error corrector 113 performs a subsequent error correction iteration, iteration 1. At iteration 1, the syndrome iteration start is 200 and the syndrome iteration end is 76. At Figure 3 In the example of , the decoder starts oscillating at iteration 12, and the period of the oscillation is 4. The stall pattern 302 may be repeated a second time (from iteration 16 to iteration 19). When the stall pattern 302 is detected, the error corrector 113 updates the bit flip criterion, causing the stall mode to be interrupted at the end of iteration 20.

[0055] Figure 4 4 is a flow chart of an example method 400 for mitigating stalls in a decoder of a memory subsystem according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The error corrector 113 of FIG. 114 is executed. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible. Reference will be made to FIG. 114 . Figure 3 The operation of method 400 is described in the stall mode of as an exemplary stall mode that may occur during error correction of a codeword. The illustrated embodiment should be understood as being by way of example only, and other stall modes may occur.

[0056] At operation 405, the processing device receives a codeword from a memory device (e.g., memory device 130 or memory device 140). In some embodiments, the codeword is received as a result of a read operation from host system 120. The codeword may include a combination of data bits and parity bits. The parity bits are stored in the memory device along with the data bits.

[0057] At operation 410, the processing device repeatedly decodes the codeword by performing error correction of bits within the codeword for a plurality of iterations based on an initial bit flipping criterion. The processing device may perform initial error correction iterations on the codeword to obtain an initially corrected codeword. For example, the processing device error corrects the codeword during iteration 0 of table 300. During the iterations, the processing device determines the locations of potential erroneous bits in the codeword and flips one or more of these bits to obtain an updated codeword (e.g., using an energy function and a bit flipping criterion, as described above). The processing device calculates syndromes to determine the number of failed parity checks for each codeword bit.

[0058] During an initial iteration, the processing device corrects errors of the codeword according to an initial bit flip criterion. In some embodiments, the initial bit flip criterion may include an initial bit flip threshold. At an iteration performed based on the initial bit flip criterion, the processing device flips one or more bits of the codeword that satisfy the initial bit flip criterion. When the energy function of the bit satisfies the bit flip criterion, the processing device flips the bit. The energy function of the bit may be determined as described above. For example, at an initial iteration, when the bit satisfies the bit flip threshold, the processing device flips one or more bits of the codeword received from the memory device. In some embodiments, when the energy function of the bit is less than the initial bit flip threshold, the bit of the codeword satisfies the initial bit flip threshold. The processing device may perform several iterations based on the initial bit flip criterion. Subsequent iterations may correct errors based on updated codewords from the previous iteration. Figure 3 In an example of , the processing device may perform iterations 0 to 15 based on the initial bit flipping criteria. In some embodiments, the processing device may perform iterations 0 to 19 based on the initial bit flipping criteria.

[0059] At operation 415, the processing device determines whether a stopping criterion is met. The stopping criterion may include an indication that no errors are detected for the codeword. In some embodiments, the stopping criterion may include a null syndrome indicating that the codeword no longer includes an erroneous bit. In some embodiments, the stopping criterion may include a maximum number of iterations or a maximum amount of time. For example, the processing device may be operable to perform a maximum number of iterations (e.g., 30 iterations, 40 iterations, 100 iterations, etc.), and when this number of iterations is performed, the resulting corrected codeword is output, regardless of whether the corrected codeword still includes an erroneous bit. When the stopping criterion is met, the operational flow moves to operation 420. At operation 420, the processing device outputs the corrected codeword (or outputs an indication of failure if the processing device is unable to decode the codeword). For example, the processing device may transmit the corrected codeword to the host 120. Alternatively, when the stopping criterion is not met, the operational flow moves to operation 425.

[0060] At operation 425, the processing device determines whether a stall condition exists in the plurality of iterations. In some embodiments, the processing device detects the stall condition by monitoring syndromes generated by error correction of the codeword in the plurality of iterations and detecting a stall pattern (e.g., stall pattern 302) in syndromes generated by error correction of the codeword in consecutive iterations from the plurality of iterations. For example, the processing device may store a plurality of consecutive syndromes generated during iterations of error correction of the codeword and compare consecutive sets of these syndromes to identify a stall pattern that repeats within a plurality of sets of iterations. The processing device may identify the stall pattern 302 as a repeating pattern between iterations 12 to 15 and iterations 16 to 19. In some embodiments, the processing device may detect the stall condition in the plurality of iterations by hashing a plurality of syndromes generated by error correction of the codeword in the plurality of iterations and comparing the hash values ​​with hash values ​​generated by hashing other syndromes generated by error correction of the codeword in other iterations. For example, the processing device may generate one hash value from the syndromes of iterations 12 to 15 and another hash value from the syndromes of iterations 16 to 19. The processing device compares the two hash values ​​to determine that iterations 12 to 15 and iterations 16 to 19 have repeating similar patterns.

[0061] In response to determining that a stall condition is not detected, the operational flow moves to operation 410, where error correction of the codeword continues according to an iterative mechanism without updating the bit flip criteria. The processing device corrects the erroneous bits of the codeword based on the initial bit flip criteria. Alternatively, in response to determining that a stall condition is detected, the operational flow moves to operation 430.

[0062] At operation 430, the processing device updates the bit flip criteria to an updated bit flip criteria. In some embodiments, the updated bit flip criteria may include an updated bit flip threshold as described above. In some embodiments, the updated bit flip threshold is greater than the initial bit flip threshold, which relaxes the flip condition, thereby causing more bit flips and enabling the processing device to exit the stall condition. Operational flow moves to operation 410, where the processing device repeats the error correction of the codeword based on the updated bit flip criteria.

[0063] At operation 410, after operation 430, the processing device error corrects the codeword based on an updated bit flip criterion that is different from the initial bit flip criterion. During the iterations performed based on the updated bit flip criterion, the processing device flips one or more bits of the codeword that meet the updated bit flip criterion. For example, when the energy function of the bit meets the updated bit flip threshold, the processing device flips one or more bits of the codeword. In some embodiments, the updated bit flip threshold causes one or more reliable bits to flip, where the reliable bits are not flipped when the initial bit flip criterion / threshold is used. In some embodiments, the updated bit flip threshold causes more bits to flip than when the initial bit flip threshold is used. In some embodiments, when the energy function of the bit is less than or equal to the updated bit flip threshold, the bits of the codeword meet the updated bit flip threshold. The processing device may perform one or more iterations based on the updated bit flip criterion. Subsequent iterations may correct errors based on the updated codeword from the previous iteration and further based on the updated bit flip criterion.

[0064] exist Figure 3 In the example of , the processing device may perform iteration 20 based on the updated bit flipping criteria. Figure 3 , but additional iterations may be performed until the stop criteria are met and the corrected codeword is output. Although the embodiments herein describe initial and updated bit flip criteria, in some embodiments, the bit flip criteria may be updated multiple times (e.g., multiple increases of the bit flip threshold, an increase after a decrease of the threshold, etc.). In one embodiment, the processing device may use the updated bit flip criteria for one or more iterations before reverting to the initial bit flip criteria or further updating the bit flip criteria (e.g., a threshold less than the initial bit flip threshold and / or less than the updated bit flip threshold, a threshold greater than the initial bit flip threshold and / or greater than the updated bit flip threshold). In another embodiment, the processing device may use the updated bit flip criteria for one or more iterations before detecting another stall condition and further updating the bit flip criteria.

[0065] Figure 5 5 is a flowchart of another example method for enabling stall mitigation in an iterative decoder according to some embodiments of the present disclosure. Method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by Figure 1The error corrector 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0066] At operation 505, the processing device receives a codeword from a memory device. At operation 510, the processing device repeatedly error-corrects the codeword in multiple iterations based on a first bit flip criterion. In some embodiments, error correction of the codeword in an iteration includes flipping one or more bits of the codeword that satisfy a bit flip threshold, as described above.

[0067] At operation 515, the processing device detects a stall condition in an iteration. Detecting the stall condition may include detecting a stall pattern in syndromes resulting from error correction of a codeword in consecutive iterations from the plurality of iterations. Detection of the stall condition may be performed as described above.

[0068] In response to the detection, the flow moves to operation 520. At operation 520, the processing device corrects the error of the codeword based on an updated bit flipping criterion that is different from the bit flipping criterion. In some embodiments, the updated bit flipping criterion causes one or more bits to flip, where the bit is not flipped when the first bit flipping criterion is used.

[0069] Figure 6 An example machine of computer system 600 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110) or can be used to perform operations of the controller (for example, to execute an operating system to execute a corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0070] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0071] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618 that communicate with each other via a bus 630.

[0072] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 for communicating via a network 620.

[0073] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0074] In one embodiment, instructions 626 include instructions for implementing instructions corresponding to an error corrector (e.g., Figure 1Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0075] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that result in a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. At times, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0076] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0077] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for a given purpose, or it may include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. For example, a computer system or other data processing system (e.g., controller 115) may perform computer-implemented methods 400 and 500 in response to its processor executing a computer program (e.g., a sequence of instructions) contained in a memory or other non-transitory machine-readable storage medium. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0078] The algorithms and displays presented herein are essentially independent of any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0079] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0080] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: receiving a codeword from a memory device, the codeword comprising a plurality of bits; iteratively error correcting the codeword in a plurality of iterations based on a comparison between a first bit flip criterion and an energy function of each of the plurality of bits of the codeword, wherein the first bit flip criterion comprises a first bit flip threshold, and wherein error correcting the codeword within an iteration of the plurality of iterations comprises flipping one or more bits of the plurality of bits of the codeword that satisfy the first bit flip threshold; detecting a stall condition in the plurality of iterations; as well as In response to the detecting, error correcting the codeword based on a comparison between a second bit flip criterion and the energy function of each of the plurality of bits of the codeword, wherein the second bit flip criterion includes a second bit flip threshold and wherein the second bit flip threshold is different from the first bit flip threshold, wherein error correcting the codeword based on the second bit flip threshold includes flipping one or more bits of the plurality of bits of the codeword that satisfy the second bit flip threshold, wherein the second bit flip threshold causes a bit to be flipped as a result of the comparison between the second bit flip threshold and the energy function of the bit, wherein the bit is not flipped as a result of the comparison between the first bit flip threshold and the energy function of the bit.

2. The method of claim 1 , wherein the flipping of the bit of the codeword that satisfies the second bit flip threshold comprises: An energy function of the bit is determined to be less than the second bit flip threshold.

3. The method of claim 1 , wherein said detecting said stall condition comprises: monitoring syndromes resulting from the error correction of the codeword in the plurality of iterations; and A stall pattern is detected in syndromes resulting from the error correction of the codeword in consecutive iterations from the plurality of iterations.

4. The method of claim 1 , wherein said detecting said stall condition comprises: Syndromes resulting from the error correction of the codeword in the plurality of iterations are hashed.

5. The method according to claim 1, further comprising: In response to miscorrecting the codeword in a number of iterations using the second bit flip threshold, miscorrecting the codeword using the first bit flip threshold.

6. The method according to claim 1, further comprising: detecting a subsequent stall condition in the plurality of iterations; as well as In response to detecting the subsequent stall condition, error correcting the codeword based on a comparison between a third bit flip criterion and the energy function of each of the plurality of bits of the codeword, wherein the third bit flip criterion includes a third bit flip threshold that is different from the first bit flip threshold and the second bit flip threshold.

7. The method of claim 6, wherein error correcting the codeword based on the third bit flip threshold comprises: One or more bits of the plurality of bits of the codeword that satisfy the third bit flip threshold are flipped, wherein satisfying the third bit flip threshold includes determining that an energy function of the bit is less than the third bit flip threshold.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receiving a codeword from a memory device, the codeword comprising a plurality of bits; iteratively error correcting the codeword in a plurality of iterations based on a comparison between a first bit flip criterion and an energy function of each of the plurality of bits of the codeword, wherein the first bit flip criterion comprises a first bit flip threshold, and wherein error correcting the codeword within an iteration of the plurality of iterations comprises flipping one or more bits of the plurality of bits of the codeword that satisfy the first bit flip threshold; detecting a stall condition in the plurality of iterations; and In response to the detecting, error correcting the codeword based on a comparison between a second bit flip criterion and the energy function of each of the plurality of bits of the codeword, wherein the second bit flip criterion includes a second bit flip threshold and wherein the second bit flip threshold is different from the first bit flip threshold, wherein error correcting the codeword based on the second bit flip threshold includes flipping one or more bits of the plurality of bits of the codeword that satisfy the second bit flip threshold, wherein the second bit flip threshold causes a bit to be flipped as a result of the comparison between the second bit flip threshold and the energy function of the bit, wherein the bit is not flipped as a result of the comparison between the first bit flip threshold and the energy function of the bit.

9. The non-transitory computer-readable storage medium of claim 8, wherein the flipping of the bit of the codeword that satisfies the second bit flip threshold comprises: An energy function of the bit is determined to be less than the second bit flip threshold.

10. The non-transitory computer-readable storage medium of claim 8, wherein detecting the stall condition comprises: monitoring syndromes resulting from the error correction of the codeword in the plurality of iterations; and A stall pattern is detected in syndromes resulting from the error correction of the codeword in consecutive iterations from the plurality of iterations.

11. The non-transitory computer-readable storage medium of claim 8, wherein detecting the stall condition comprises: Syndromes resulting from the error correction of the codeword in the plurality of iterations are hashed.

12. The non-transitory computer-readable storage medium of claim 8, wherein the processing device further: In response to miscorrecting the codeword in a number of iterations using the second bit flip threshold, miscorrecting the codeword using the first bit flip threshold.

13. The non-transitory computer-readable storage medium of claim 8, wherein the processing device further: detecting a subsequent stall condition in the plurality of iterations; and In response to detecting the subsequent stall condition, error correcting the codeword based on a comparison between a third bit flip criterion and the energy function of each of the plurality of bits of the codeword, wherein the third bit flip criterion includes a third bit flip threshold that is different from the first bit flip threshold and the second bit flip threshold.

14. The non-transitory computer-readable storage medium of claim 13, wherein error correcting the codeword based on the third bit flip threshold comprises: One or more bits of the plurality of bits of the codeword that satisfy the third bit flip threshold are flipped, wherein satisfying the third bit flip threshold includes determining that an energy function of the bit is less than the third bit flip threshold.

15. A system comprising: Memory device; as well as a processing device operatively coupled to the memory device to: receiving a codeword from the memory device, the codeword comprising a plurality of bits; iteratively error correcting the codeword in a plurality of iterations based on a comparison between a first bit flip threshold and an energy function of each of the plurality of bits of the codeword, wherein the error correction of the codeword in an iteration from the plurality of iterations comprises flipping one or more bits of the plurality of bits of the codeword that satisfy the first bit flip threshold; detecting a stall condition in the plurality of iterations; as well as In response to the detecting, error correcting the codeword based on a comparison between a second bit flip threshold and the energy function of each of the plurality of bits of the codeword, wherein the second bit flip threshold is different from the first bit flip threshold, wherein error correcting the codeword based on the second bit flip threshold includes flipping one or more bits of the plurality of bits of the codeword that satisfy the second bit flip threshold, wherein the second bit flip threshold causes a bit to be flipped as a result of the comparison between the second bit flip threshold and the energy function of the bit, wherein the bit is not flipped as a result of the comparison between the first bit flip threshold and the energy function of the bit.

16. The system of claim 15, wherein the flipping of the bit of the codeword that satisfies the second bit flip threshold comprises: An energy function of the bit is determined to be less than the second bit flip threshold.

17. The system of claim 15, wherein detecting the stall condition comprises: monitoring syndromes resulting from the error correction of the codeword in the plurality of iterations; and A stall pattern is detected in syndromes resulting from the error correction of the codeword in consecutive iterations from the plurality of iterations.

18. The system of claim 15, wherein detecting the stall condition comprises: Syndromes resulting from the error correction of the codeword in the plurality of iterations are hashed.

19. The system of claim 15, wherein the processing device further: In response to miscorrecting the codeword in a number of iterations using the second bit flip threshold, miscorrecting the codeword using the first bit flip threshold.

20. The system of claim 15, wherein the processing device further: detecting a subsequent stall condition in the plurality of iterations; and In response to detecting the subsequent stall condition, error correcting the codeword based on a comparison between a third bit flip criterion and the energy function of each of the plurality of bits of the codeword, wherein the third bit flip criterion includes a third bit flip threshold that is different from the first bit flip threshold and the second bit flip threshold.

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