Busbar system

Abstract

The present invention provides a bus system. A plurality of slave components are electrically connected to a master component via a bus. Each slave component has a warning handshake pin. The warning handshake pins of the slave components are electrically connected together via a warning handshake control line. In a first stage of a first slave component corresponding to the slave component in a plurality of stages of each distribution cycle of a distribution stage, the first slave component controls the warning handshake control line to a second voltage level via the warning handshake pin. In each stage except the first stage in the distribution cycle, the first slave component controls the warning handshake control line to communicate with other slave components via the warning handshake pin. The present invention can increase the efficiency and flexibility of the bus system in scheduling.

Description

Technical Field

[0001] The present invention relates to a bus system, and more particularly to a bus system having a plurality of slave components. Background Art

[0002] In the past, in computer systems, chipsets such as south bridge chips were electrically connected to other circuit modules, such as system-on-a-chip (SoC) with different functions, through low pin count (LPC) interfaces. These external circuit modules connected through low pin count interfaces can be assigned different independent addresses, so the south bridge chip can communicate with the external circuit modules in a one-to-many manner. However, in recent years, some newly proposed bus architectures, such as the Enhanced Serial Peripheral Interface (eSPI) bus, only allow one-to-one communication between the chipset and the external circuit modules.

[0003] Therefore, a mechanism is needed to schedule the buses of multiple circuit modules. Summary of the invention

[0004] The present invention provides a bus system. The bus system includes a master control element, an enhanced sequence peripheral device interface bus and a plurality of slave elements. The slave elements are electrically connected to the master control element through the enhanced sequence peripheral device interface bus. Each of the slave elements has a warning handshake pin, and the warning handshake pins of the slave elements are electrically connected together through a warning handshake control line. When the warning handshake control line is at a first voltage level and a first slave element of the slave elements wants to communicate with other slave elements, the first slave element controls the warning handshake control line to a second voltage level through the warning handshake pin, so that the slave elements enter a synchronization stage. After the synchronization stage, in a first stage corresponding to the first slave element in multiple stages of each distribution cycle of a distribution stage, the first slave element controls the warning handshake control line to the second voltage level through the warning handshake pin, and in each stage except the first stage in the distribution cycle, the first slave element controls the warning handshake control line to communicate with other slave elements through the warning handshake pin.

[0005] Furthermore, the present invention provides a bus system. The bus system includes a master control component, an enhanced sequence peripheral device interface bus and a plurality of slave components. The slave components are electrically connected to the master control component through the enhanced sequence peripheral device interface bus. Each of the slave components has a warning handshake pin, and the warning handshake pins of the slave components are electrically connected together through a warning handshake control line. When the warning handshake control line is at a first voltage level and a first slave component of the slave components wants to communicate with the master control component through the enhanced sequence peripheral device interface bus, the first slave component controls the warning handshake control line to a second voltage level through the warning handshake pin, so that the slave component enters a synchronization stage. After the synchronization stage, the other slave components except the first slave component detect the warning handshake control line in the other phases except a first phase corresponding to the first slave component in multiple phases of each distribution cycle of a distribution phase to determine whether to communicate with the first slave component through the warning handshake control line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Shown are busbar systems according to some embodiments of the present invention.

[0007] Figure 2 Display according to some embodiments of the present invention Figure 1 Connection configuration diagram of the busbar system.

[0008] Figure 3 A flow chart showing a method for scheduling control of single wire data access (SWDA) communication in a bus system according to some embodiments of the present invention is shown.

[0009] FIG. 4A to FIG. 4B A sample waveform diagram showing the ALERT_HAND control line is used to illustrate the slave device according to Figure 3 The SWDA communication scheduling control method is used to drive the operation of the alert handshake control line ALERT_HAND.

[0010] FIG. 5A to FIG. 5B A sample waveform diagram showing the ALERT_HAND control line is used to illustrate the slave device according to Figure 3 The scheduling control method is used to drive the operation of the alert handshake control line ALERT_HAND.

[0011] Figure 6 A diagram showing a connection configuration of a busbar system according to some embodiments of the present invention.

[0012] Figure 7 A diagram showing a connection configuration of a busbar system according to some embodiments of the present invention.

[0013]

Explanation of symbols

[0014] 1,1A,1B: Busbar system

[0015] 10: Main control components

[0016] 12: Bus

[0017] 14A-14N: Slave components

[0018] 143A-143D: Demand Controller

[0019] 145A-145D: Scheduler Controller

[0020] 15A-15N: Peripheral components

[0021] 16A-16D: Address entry selection pins

[0022] 18A-18D: Address segment selection pins

[0023] 20: Processing module

[0024] 22: Memory

[0025] Alert_1-Alert_4: Alert handshake pins

[0026] ALERT_HAND: Alert handshake control line

[0027] AP1-AP4: Distribution cycle

[0028] clk1-clk4: clock pulse signal

[0029] eSPI_CLK: clock pulse signal

[0030] CY1-CY8: Clock pulse period

[0031] COM:Instructions

[0032] eSPI_CS: chip select signal line

[0033] eSPI_IO, eSPI_IO2: input and output signal lines

[0034] eSPI_RST: reset signal line

[0035] GND: Ground terminal

[0036] PH1-PH4: Stage

[0037] R: Pull-up resistor

[0038] REQ1,REQ2: Interrupt requirements

[0039] S302-S320: Steps

[0040] ST_Ass: Distribution Phase

[0041] ST_IdleWait: waiting stage

[0042] ST_Sync: Synchronization phase

[0043] ST_SyncEnd: synchronization end phase

[0044] SWDA_DATA: data

[0045] Target_ID: Target identification

[0046] TP1-TP4: Time period

[0047] t1-t11, t21-t24: time points

[0048] VDD: Power supply DETAILED DESCRIPTION

[0049] In order to make the above and other purposes, features, and advantages of the present invention more clearly understood, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings as follows:

[0050] Figure 1 A bus system 1 according to some embodiments of the present invention is shown. The bus system 1 includes a master component 10, a bus 12, and a plurality of slave components 14A-14D. In some embodiments, the master component 10 is a south bridge chip. In some embodiments, the master component 10 can be electrically connected to a processing module 20 of a computer system (not shown) so as to access data with the slave components 14A-14D through the bus 12 in response to instructions from the processing module 20. In some embodiments, the processing module 20 can be electrically connected to a memory 22 of the computer system so as to access the memory 22 according to the requirements of different application programs. In some embodiments, the bus 12 is an Enhanced Serial Peripheral Interface (eSPI) bus. The master component 10 is electrically connected to the slave components 14A-14D through the bus 12. In addition, the master device 10 communicates with the slave devices 14A-14D in eSPI in a one-to-one mechanism, and the slave devices 14A-14D communicate with the master device 10 in accordance with an arbitration mechanism. It should be noted that the number of slave devices 14A-14D is only an example and is not intended to limit the present invention.

[0051] Figure 2 Display according to some embodiments of the present invention Figure 1 FIG. 1 is a connection configuration diagram of the bus system 1. In this embodiment, the bus 12 includes a reset signal line eSPI_RST, a chip select signal line eSPI_CS, a clock pulse signal eSPI_CLK, and an input / output signal line eSPI_IO. The master control component 10 performs eSPI communication with the slave components 14A-14D in a one-to-one mechanism through the chip select signal line eSPI_CS. In addition, through the arbitration mechanism, the slave components 14A-14D can perform eSPI communication (e.g., transmit data and instructions) with the master control component 10 through the input / output signal line eSPI_IO. When the master control component 10 performs eSPI communication with the slave components 14A-14D through the bus 12, the clock pulse signal eSPI_CLK can be used as a reference clock pulse.

[0052] Generally speaking, according to the operation mechanism of the chip select signal line eSPI_CS, the master control component 10 can only select a single component for eSPI communication. However, by using an arbitration mechanism, only one of the slave components 14A-14D responds to the master control component 10 at a time in the bus system 1. Therefore, when the master control component 10 still operates in a one-to-one communication mechanism, the bus 12 can correspond to one chip select signal line eSPI_CS and connect the slave components 14A-14D for eSPI communication, thereby improving the expandability of the bus system 1.

[0053] exist Figure 2, the slave components 14A-14D include address segment selection pins 18A-18D, address entry selection pins 16A-16D, and alert handshake pins Alert_1-Alert_4. The addresses corresponding to the slave components 14A-14D can be configured by a combination of voltage levels received by the address segment selection pins 18A-18D and the address entry selection pins 16A-16D, so that the slave components 14A-14D have different address segments. For example, the address segment selection pins 18A and 18C of the slave components 14A and 14C are coupled to the ground terminal GND to correspond to the first address segment. The address entry selection pins 16A and 16C of the slave components 14A and 14C are respectively coupled to the ground terminal GND and the power supply VDD to respectively correspond to different address entry codes, for example, respectively corresponding to the first address and the second address of the first address segment. In addition, the address segment selection pins 18B and 18D of the slave components 14B and 14D are coupled to the power supply VDD to correspond to the second address segment. The address entry selection pins 16B and 16D of the slave components 14B and 14D are respectively coupled to the ground terminal GND and the power supply VDD to correspond to different address entry codes, such as the first address and the second address of the second address segment. It is worth noting that the configuration of the address segment selection pins 18A-18D and the address entry selection pins 16A-16D is only an example and is not intended to limit the present invention. In other embodiments, any suitable setting can be used to set the address segment corresponding to the slave components 14A-14D.

[0054] The alert handshake pins Alert_1-Alert_4 of the slave components 14A-14D are electrically connected to the alert handshake control line ALERT_HAND. In this embodiment, the alert handshake control line ALERT_HAND is electrically connected to the power supply VDD through a pull-up resistor R, so that the alert handshake control line ALERT_HAND is a high voltage level (e.g., a high logic signal "H"). In addition, the schedule controller 145A-145D in the slave components 14A-14D can drive the alert handshake control line ALERT_HAND by controlling the corresponding alert handshake pins Alert_1-Alert_4 to a low voltage level (e.g., a low logic signal "L"), so that the alert handshake control line ALERT_HAND is a low voltage level. Therefore, each slave component 14A-14D can obtain the right to actively communicate with the master component 10 by controlling the voltage level of the alert handshake control line ALERT_HAND. The alert handshake pins Alert_1-Alert_4 are bidirectional input / output pins and are open drain in output mode. In some embodiments, the alert handshake control line ALERT_HAND is electrically connected to the ground terminal GND through a pull-down resistor so that the alert handshake control line ALERT_HAND is at a low voltage level (e.g., a low logic signal "L").

[0055] exist Figure 2, each slave component 14A-14D includes a respective demand controller 143A-143D. Taking the slave component 14A as an example, the demand controller 143A of the slave component 14A can perform eSPI communication with the master component 10 through the bus 12. For example, when the slave component 14A communicates with the master component 10, the demand controller 143A can receive instructions and data from the master component 10 through the bus 12, and provide corresponding data to the master component 10. In addition, the demand controller 143A of the slave component 14A can also perform single-wire data access (SWDA) communication with other slave components (such as slave components 14B, 14C and / or 14D) and / or peripheral components (not shown) through the alert handshake control line ALERT_HAND. For example, when the slave component 14A communicates with the slave components 14B, 14C and / or 14D, the demand controller 143A can transmit instructions and data to a single slave component (i.e., one-to-one communication) or multiple slave components (i.e., one-to-many broadcast) through the alert handshake control line ALERT_HAND. In addition, the demand controller 143A can also receive instructions and data from the slave components 14B, 14C or 14D through the alert handshake control line ALERT_HAND. Furthermore, each slave component 14A-14D also includes its own scheduling controller 145A-145D. Each scheduling controller 145A-145D is used to control the alert handshake control line ALERT_HAND to perform the sequencing of eSPI communication and / or SWDA communication. In addition, the priority order of the slave components 14A-14D to control the alert handshake control line ALERT_HAND is determined by Figure 2 In other embodiments, other hardware or software settings can be used to determine the priority of the slave components 14A-14D controlling the alert handshake control line ALERT_HAND.

[0056] In some embodiments, when the slave component 14A performs eSPI communication with the master component 10, if the slave component 14A finds that the command transmitted by the master component 10 through the bus 12 is abnormal, for example, the master component 10 is attacking the slave component 14A to steal the data inside the slave component 14A, the slave component 14A can immediately perform SWDA communication through the alert handshake control line ALERT_HAND, so as to broadcast to the slave components 14B-14D to notify other slave components that the operation of the current master component 10 is abnormal. Therefore, the slave components 14B-14D can avoid performing eSPI communication with the master component 10 with abnormal operation.

[0057] Figure 3A flow chart showing a method for scheduling and controlling SWDA communication of a bus system 1 according to some embodiments of the present invention is shown. Figure 3 The scheduling control method of SWDA communication can be executed by each scheduling controller 145A-145D of the slave components 14A-14D in the bus system 1. FIG. 4A to FIG. 4B The exemplary waveform diagram of the warning handshake control line ALERT_HAND is shown to illustrate the slave components 14A-14D according to Figure 3 The SWDA communication scheduling control method is used to drive the operation of the alert handshake control line ALERT_HAND. In addition, FIG. 4A to FIG. 4B The waveforms of the clock pulse signals clk1 - clk4 and the alert handshake control line ALERT_HAND shown are only examples and are not intended to limit the present invention.

[0058] Also refer to Figure 3 and FIG. 4A to FIG. 4B , the slave components 14A-14D use the clock pulse signals clk1-clk4 of the same frequency as the counting basis of the scheduling controllers 145A-145D. In some embodiments, the clock pulse signals clk1-clk4 have the same phase. In some embodiments, the clock pulse signals clk1-clk4 have different phases. In some embodiments, the clock pulse signals clk1-clk4 have the same frequency, so the clock pulse signals clk1-clk4 have the same time period, that is, TP1=TP2=TP3=TP4. In some embodiments, the scheduling controllers 145A-145D count according to the rising edge of the clock pulse signals clk1-clk4. In some embodiments, the scheduling controllers 145A-145D count according to the falling edge of the clock pulse signals clk1-clk4.

[0059] When the alert handshake control line ALERT_HAND is not detected to be driven, the schedule controller 145-145D controls the slave components 14A-14D to enter the idle wait stage ST_IdleWait (step S302). In the idle wait stage ST_IdleWait, the schedule controller 145A-145D of each slave component 14A-14D controls the corresponding alert handshake pin Alert_1-Alert_4 to be in input mode, so as to monitor whether the alert handshake control line ALERT_HAND is driven by any slave component 14A-14D (step S304), for example, the alert handshake control line ALERT_HAND changes from a high voltage level to a low voltage level.

[0060] In step S304, when it is detected that the alert handshake control line ALERT_HAND is not driven by any slave device 14A-14D, each schedule controller 145A-145D controls the slave device 14A-14D to continue to operate in the standby waiting stage (step S302) until it is detected that the alert handshake control line ALERT_HAND is driven (step S304). When it is detected that the alert handshake control line ALERT_HAND is driven (for example, the alert handshake control line ALERT_HAND is at a low voltage level), each schedule controller 145A-145D controls the slave device 14A-14D to enter the synchronization stage ST_Sync (step S306). Therefore, the slave devices 14A-14D of the bus system 1 will enter the synchronization stage ST_Sync at the same time.

[0061] When the bus system 1 enters the synchronization stage ST_Sync (step S306), the slave components with interruption requirements will control their alert handshake pins to output mode and output a low voltage level to drive the alert handshake control line ALERT_HAND for more than a specific number of clock pulse cycles (for example, driving more than 3 clock pulse cycles), so that other slave components of the bus system 1 can distinguish that the bus system 1 enters the synchronization stage ST_Sync instead of other stages (for example, the distribution stage ST_Ass). After the alert handshake control line ALERT_HAND is driven for more than 3 clock pulse cycles, the slave components with interruption requirements will stop driving the alert handshake control line ALERT_HAND and control their alert handshake pins to input mode to monitor the alert handshake control line ALERT_HAND. At the same time, other slave components of the bus system 1 will also detect that the alert handshake control line ALERT_HAND has returned to a high voltage level, so all slave components simultaneously enter the synchronization end stage ST_SyncEnd (step S308).

[0062] In the synchronization end stage ST_SyncEnd, each scheduling controller 145A-145D will wait for at least one clock pulse cycle to ensure that each slave component 14A-14D of the bus system 1 completes the synchronization stage ST_Sync, and then the scheduling controller 145A-145D will control the slave components 14A-14D to enter the distribution stage ST_Ass from the synchronization end stage ST_SyncEnd (step S310).

[0063] After entering the distribution stage ST_Ass, the schedule controller 145A-145D of each slave element 14A-14D determines whether there is an interruption requirement for SWDA communication and / or eSPI communication, so as to control the corresponding alert handshake pins Alert_1-Alert_4 to drive the alert handshake control line ALERT_HAND (step S312). If there is no need to drive the alert handshake control line ALERT_HAND (i.e., no interruption requirement), the corresponding alert handshake pins Alert_1-Alert_4 are controlled to be in input mode or tri-state mode (Tri-State ( Figure 3 If one of the slave components 14A-14D drives the alert handshake control line ALERT_HAND through the corresponding alert handshake pin, it is determined whether the slave component is to perform SWDA communication (step S314). If the slave component only performs eSPI communication, the slave component controls the corresponding alert handshake pin to be in input mode or tri-state mode ( Figure 3 If the slave component wants to perform SWDA communication with other slave components, the schedule controller of the slave component will control the corresponding alert handshake pin to control the alert handshake control line ALERT_HAND to perform SWDA communication (step S316). Then, when it is detected that the alert handshake control line ALERT_HAND is not driven (step S320), the schedule controller 145A-145D will control the slave components 14A-14D to enter the standby waiting stage ST_IdleWait again (step S302). If it is detected that the alert handshake control line ALERT_HAND is driven (step S320), the process returns to step S312.

[0064] exist FIG. 4A to FIG. 4B In the distribution stage ST_Ass, the slave components 14A-14D monitor the state of the alert handshake control line ALERT_HAND through the alert handshake pins Alert_1-Alert_4 in each distribution period AP1-AP4. In addition, each slave component 14A-14D has a distribution period AP1-AP4 with the same time period. In this embodiment, each distribution period AP1-AP4 has 2×4 clock pulse periods CY1-CY8. In addition, each distribution period AP1-AP4 can be divided into 4 phases PH1-PH4, and each phase includes 2 clock pulse periods. For example, phase PH1 includes clock pulse periods CY1 and CY2, phase PH2 includes clock pulse periods CY3 and CY4, phase PH3 includes clock pulse periods CY5 and CY6, and phase PH4 includes clock pulse periods CY7 and CY8.

[0065] In the distribution stage ST_Ass, each slave component 14A-14D performs corresponding operations according to the stages PH1-PH4. In this embodiment, slave component 14A corresponds to the stage PH1, slave component 14B corresponds to the stage PH2, slave component 14C corresponds to the stage PH3, and slave component 14D corresponds to the stage PH4. In some embodiments, the correspondence between the slave components 14A-14D and the stages PH1-PH4 is determined by Figure 2 In other embodiments, other hardware or software settings may be used to determine the corresponding relationship between the slave components 14A-14D and the phases PH1-PH4.

[0066] exist FIG. 4A to FIG. 4B In the distribution cycle AP1-AP4, the slave components 14A-14D count the clock pulse periods CY1-CY8 according to the rising edge of the internal clock pulse signals clk1-clk4. In addition, in the distribution phase ST_Ass, when the alert handshake control line ALERT_HAND is not driven, if each slave component 14A-14D is to perform eSPI communication with the master component 10 or SWDA communication with the slave components 14B-14D, then the slave component will have the power to drive the alert handshake control line ALERT_HAND in the corresponding phase of its distribution cycle. For example, if the slave component 14A is to perform eSPI communication with the master component 10 or SWDA communication with the slave components 14B-14D, then the slave component 14A will have the power to drive the alert handshake control line ALERT_HAND in the phase PH1 of the distribution cycle AP1. Specifically, when the slave device 14A performs eSPI communication and / or SWDA communication, the schedule controller 145A of the slave device 14A controls the alert handshake pin Alert_1 to be in output mode and output a low voltage level in phase PH1 to drive the alert handshake control line ALERT_HAND ( Figure 3 In step S312), the alert handshake control line ALERT_HAND is controlled to be at a low voltage level.

[0067] If the slave device 14A does not need to perform eSPI communication or SWDA communication, the schedule controller 145A of the slave device 14A will control the alert handshake pin Alert_1 to be in input mode or tri-state mode in phase PH1 ( Figure 3Then, in the phases PH2-PH4 of the distribution cycle AP1, the slave component 14A will monitor the voltage level of the alert handshake control line ALERT_HAND to determine whether the slave components 14B-14D have an interruption requirement to perform eSPI communication and / or SWDA communication. In other words, in the phases PH2-PH4, the schedule controller 145A of the slave component 14A will control the alert handshake pin Alert_1 to be in input mode. For example, the slave component 14A will monitor the voltage level of the alert handshake control line ALERT_HAND through the alert handshake pin Alert_1 in phase PH2 to determine whether the slave component 14B has driven the alert handshake control line ALERT_HAND. If the slave device 14A detects that the alert handshake control line ALERT_HAND is at a high voltage level in phase PH2, the schedule controller 145A determines that the slave device 14B does not drive the alert handshake control line ALERT_HAND. If the slave device 14A detects that the alert handshake control line ALERT_HAND is at a low voltage level in phase PH2, the schedule controller 145A determines that the slave device 14B has an interrupt request to perform eSPI communication and / or SWDA communication.

[0068] refer to Figure 4A , corresponding to the interrupt request REQ1, the slave component 14A needs to perform SWDA communication. Before the slave component 14A wants to communicate with the slave components 14B-14D, it will first monitor the voltage level of the alert handshake control line ALERT_HAND to determine that the alert handshake control line ALERT_HAND is not driven by the slave components 14B-14D. Then, at time point t1, the slave component 14A will control the alert handshake pin Alert_1 to the output mode and output a low voltage level within 3 clock pulse cycles of the clock pulse signal clk1 to drive the alert handshake control line ALERT_HAND, so as to notify the slave components 14B-14D to enter the synchronization stage ST_Sync. Then, at time point t2, after completing the synchronization stage ST_Sync, the slave component 14A will control the alert handshake pin Alert_1 to the input mode to stop driving the alert handshake control line ALERT_HAND. Therefore, each slave component 14A-14D of the bus system 1 enters the synchronization end phase ST_SyncEnd. In some embodiments, in the synchronization end phase ST_SyncEnd, each schedule controller 145A-145D waits for at least one clock pulse cycle, and then the schedule controller 145A-145D controls the slave components 14A-14D to enter the distribution phase ST_Ass from the synchronization end phase ST_SyncEnd.

[0069] exist Figure 4A In the distribution phase ST_Ass of the slave component 14A, the slave component 14A obtains control of the alert handshake control line ALERT_HAND so as to perform eSPI communication with the master component 10 and / or SWDA communication with other slave components. Therefore, at time point t3, the alert handshake control line ALERT_HAND changes to a low voltage level in phase PH1 of the distribution cycle AP1 of the slave component 14A. Thus, the slave component 14A can obtain the right to perform SWDA communication and / or eSPI communication. Next, the slave component 14D detects that the alert handshake control line ALERT_HAND is at a low voltage level in phase PH1 of the distribution cycle AP4 (as shown by arrow 402). Thus, the slave component 14D can know that the slave component 14A corresponding to phase PH1 wants to perform SWDA communication and / or eSPI communication (for example, to handle an interrupt request). Next, the slave component 14B detects that the alert handshake control line ALERT_HAND is at a low voltage level in phase PH1 of the distribution cycle AP2 (as shown by arrow 404). Therefore, the slave component 14B can know that the slave component 14A corresponding to phase PH1 is performing SWDA communication and / or eSPI communication (for example, processing an interrupt request). At the same time, the slave component 14C also detects that the alert handshake control line ALERT_HAND is at a low voltage level in phase PH1 of the distribution cycle AP3 (as shown by arrow 406). Therefore, the slave component 14C can know that the slave component 14A corresponding to phase PH1 is performing SWDA communication and / or eSPI communication (for example, processing an interrupt request).

[0070] In some embodiments of eSPI communication, when the slave component 14A is communicating with the master component 10, the slave component 14A provides an event alert signal ALERT to the input / output signal line eSPI_IO of the bus 12 through its input / output signal line eSPI_IO1, so as to transmit the event alert signal ALERT to the master component 10. The event alert signal ALERT is a request signal indicating that the slave component 14A requests the master component 10 to communicate. When it is detected that the slave component 14A drives the alert handshake control line ALERT_HAND, if other slave components 14B-14D want to communicate with the master component 10, they will store the event information and communicate with the master component 10 when they obtain the control right of the alert handshake control line ALERT_HAND later. When the slave component 14A performs eSPI communication with the master component 10, the slave component 14A drives the alert handshake control line ALERT_HAND at the phase PH1 of each distribution cycle AP1 until the eSPI communication with the master component 10 is terminated. Similarly, when the slave component 14A performs SWDA communication with other slave components, the slave component 14A drives the alert handshake control line ALERT_HAND at the phase PH1 of each distribution cycle AP1 until the SWDA communication is terminated. After the eSPI communication and SWDA communication are terminated, the slave component 14A will not drive the alert handshake control line ALERT_HAND at the phase PH1 of the distribution cycle AP1, so the slave components 14A-14D will enter the standby waiting phase ST_IdleWait after the phase PH1. As described above, in the idle waiting stage ST_IdleWait, the schedule controller 145A-145D of each slave device 14A-14D controls the corresponding alert handshake pins Alert_1-Alert_4 to be in input mode to monitor whether the alert handshake control line ALERT_HAND is driven by any slave device 14A-14D.

[0071] At time point t4, when the slave component 14A performs SWDA communication, the slave component 14A controls the alert handshake pin Alert_1 to be in output mode in phases PH2-PH4 of the distribution cycle AP1, and transmits the target identification Target_ID to each slave component 14B-14D through the alert handshake control line ALERT_HAND, so as to notify the slave component corresponding to the target identification Target_ID to perform SWDA communication. In addition, for the slave components 14B-14D, the alert handshake pins Alert_2-Alert_4 are controlled to be in input mode in phases PH2-PH4 of the corresponding distribution cycle AP2-AP4, so as to obtain the target identification Target_ID from the slave component 14A through the alert handshake control line ALERT_HAND. In some embodiments, the target identification Target_ID from the slave component 14A only includes the identification ID of a single slave component. In some embodiments, the target identification Target_ID from the slave component 14A includes the identification IDs of multiple slave components. In these embodiments, the slave component 14A is the master or transmitter of the SWDA communication, and the slave component having the identification ID corresponding to the target identification Target_ID is the slave or receiver of the SWDA communication.

[0072] In the bus system 1, each slave component 14A-14D has an individual identification ID. In some embodiments, the identification ID of the slave components 14A-14D can be set by the address segment selection pins 18A-18D and the address entry selection pins 16A-16D. In some embodiments, the identification ID of the slave components 14A-14D is related to the priority order of the slave components 14A-14D controlling the alert handshake control line ALERT_HAND.

[0073] For the slave components 14B-14D, in the corresponding distribution cycles AP2-AP4, the phases PH2-PH4 control the alert handshake pins Alert_2-Alert_4 to be in input mode, so as to obtain the target identification Target_ID from the slave component 14A through the alert handshake control line ALERT_HAND. In some embodiments, the target identification Target_ID from the slave component 14A only includes the identification ID of a single slave component. In some embodiments, the target identification Target_ID from the slave component 14A includes the identification IDs of multiple slave components.

[0074] After obtaining the target identification Target_ID, the slave components 14B-14D further determine whether the slave component 14A requires SWDA communication. For example, if the target identification Target_ID includes the identification ID of the slave component 14B, it means that the slave component 14A wants to perform SWDA communication with the slave component 14B. If the target identification Target_ID includes the identification IDs of all other slave components 14B-14D, it means that the slave component 14A wants to broadcast to other slave components 14B-14D.

[0075] Then, at time point t5, the slave component 14A changes the alert handshake control line ALERT_HAND to a low voltage level in phase PH1 of the distribution cycle AP1. Thus, the slave component 14A can continue to obtain the right to perform SWDA communication and / or eSPI communication. Then, at time point t6, the slave component 14A controls the alert handshake pin Alert_1 to output mode in phases PH2-PH4 of the distribution cycle AP1, and transmits the command COM through the alert handshake control line ALERT_HAND. Thus, after receiving the command COM from the slave component 14A through the alert handshake control line ALERT_HAND, the slave component with the identification ID corresponding to the target identification Target_ID will perform subsequent operations corresponding to the command COM. In some embodiments, the command COM includes a read command, a write (programming) command, and a setting command, etc.

[0076] refer to Figure 4B Then, at time point t7, the slave device 14A changes the alert handshake control line ALERT_HAND to a low voltage level at phase PH1 in the distribution cycle AP1. Thus, the slave device 14A can continue to obtain the right to perform SWDA communication and / or eSPI communication. Then, starting from time point t8, the slave device 14A and the slave device with the identification ID corresponding to the target identification Target_ID control their alert handshake pins at phases PH2-PH4 in the distribution cycle to execute the command COM through the alert handshake control line ALERT_HAND.

[0077] In some embodiments, it is assumed that the command COM is a write command, and the target identification Target_ID includes the identification ID of the slave components 14B-14D. In such an embodiment, the slave component 14A controls the alert handshake pin Alert_1 to be in output mode in phases PH2-PH4 of the distribution cycle AP1, so as to transmit the data SWDA_DATA through the alert handshake control line ALERT_HAND. At the same time, corresponding to the command COM from the slave component 14A, the slave components 14B-14D control the alert handshake pins Alert_2-Alert_4 to be in input mode in phases PH2-PH4 of the distribution cycles AP2-AP4, so as to receive the data SWDA_DATA from the slave component 14A through the alert handshake control line ALERT_HAND. Then, the slave components 14B-14D store the received data SWDA_DATA or perform subsequent operations. In some embodiments, if the command COM is a setting command, the slave components 14B-14D perform corresponding settings according to the data SWDA_DATA.

[0078] In some embodiments, it is assumed that the command COM is a read command, and the target identification Target_ID includes the identification ID of the slave component 14B. In such an embodiment, corresponding to the command COM, the slave component 14B controls the alert handshake pin Alert_2 to the output mode in the phases PH2-PH4 of the distribution cycle AP2, so as to transmit the data SWDA_DATA to the slave component 14A through the alert handshake control line ALERT_HAND. In addition, the slave component 14A controls the alert handshake pin Alert_1 to the input mode in the phases PH2-PH4 of the distribution cycle AP1, so as to receive the data SWDA_DATA from the slave component 14B through the alert handshake control line ALERT_HAND. Then, the slave component 14A stores the received data SWDA_DATA or performs subsequent operations.

[0079] In the bus system 1, corresponding to the command COM, each slave device 14A-14D can control the corresponding alert handshake pin Alert_1-Alert_4 to be in input mode or output mode, so as to receive or transmit data SWDA_DATA to perform SWDA communication. Then, the slave device 14A will drive the alert handshake control line ALERT_HAND in the phase PH1 of each distribution cycle AP1 until the SWDA communication is terminated.

[0080] At time point t9, the slave component 14D detects that the alert handshake control line ALERT_HAND changes to a high voltage level in phase PH1 of the distribution cycle AP4. Therefore, the slave component 14D can know that the slave component 14A has ended the SWDA communication. Then, at time point t10, the slave components 14B and 14C detect that the alert handshake control line ALERT_HAND changes to a high voltage level in phase PH1 of the distribution cycles AP2 and AP3, respectively. Therefore, the slave components 14B and 14C can know that the slave component 14A has ended the SWDA communication. Then, the scheduling controller 145B-145D controls the slave components 14B-14D to enter the standby waiting phase ST_IdleWait. In other words, after the SWDA communication and / or the eSPI communication are terminated, the slave device 14A will not drive the alert handshake control line ALERT_HAND in the phase PH1 of the distribution cycle AP1, so the slave devices 14A-14D will enter the standby waiting phase ST_IdleWait after the phase PH1. As described previously, in the standby waiting phase ST_IdleWait, the schedule controller 145A-145D of each slave device 14A-14D will control the corresponding alert handshake pin Alert_1-Alert_4 to the input mode, so as to monitor whether the alert handshake control line ALERT_HAND is driven by any slave device 14A-14D.

[0081] At time point t11, when the slave component 14B also has an interrupt request REQ2, the slave component 14B controls the alert handshake pin Alert_2 to be in output mode and outputs a low voltage level within 3 clock pulse cycles of the clock pulse signal clk2 to drive the alert handshake control line ALERT_HAND, so as to notify the slave components 14A and 14C-14D to enter the synchronization phase ST_Sync. Then, the bus system 1 will sequentially enter the synchronization end phase ST_SyncEnd and the distribution phase ST_Ass. As previously described, in the distribution phase ST_Ass, the slave component 14B controls the alert handshake pin Alert_2 to be in output mode and outputs a low voltage level in phase PH2 of the distribution cycle AP2 to drive the alert handshake control line ALERT_HAND, and perform SWDA communication and / or eSPI communication.

[0082] In some embodiments, the signals (such as target identification Target_ID, command COM and data SWDA_DATA, etc.) transmitted by the bus system 1 during SWDA communication through the alert handshake control line ALERT_HAND will be maintained for two clock pulse cycles to avoid the phase difference between the clock pulse signals clk1-clk4 of the slave components 14A-14D causing data sampling errors between the slave components 14A-14D.

[0083] In the embodiment of the present invention, the signal and / or packet transmitted by SWDA communication on the alert handshake control line ALERT_HAND is only an example. In other embodiments, the slave components 14A-14D can transmit signals and packets of any protocol on the alert handshake control line ALERT_HAND, such as serial communication protocols such as I2C, UART, and SPI.

[0084] FIG. 5A to FIG. 5B The exemplary waveform diagram of the warning handshake control line ALERT_HAND is shown to illustrate the slave components 14A-14D according to Figure 3 The scheduling control method drives the operation of the alert handshake control line ALERT_HAND. In addition, FIG. 5A to FIG. 5B The waveforms of the clock pulse signals clk1 - clk4 and the alert handshake control line ALERT_HAND shown are only examples and are not intended to limit the present invention.

[0085] In response to the interrupt request REQ2, the slave component 14B needs to perform eSPI communication and SWDA communication. Before the slave component 14B wants to perform eSPI communication and SWDA communication, it will first monitor the voltage level of the alert handshake control line ALERT_HAND to determine that the alert handshake control line ALERT_HAND is not driven by the slave components 14A and 14C-14D. Then, at time point t21, the slave component 14B will control the alert handshake pin Alert_2 to be in output mode and output a low voltage level within 3 clock pulse cycles of the clock pulse signal clk1 to drive the alert handshake control line ALERT_HAND so as to notify the slave component 14A and the slave components 14C-14D to enter the synchronization stage ST_Sync. At time point t22, after completing the synchronization stage ST_Sync, the slave component 14B will control the alert handshake pin Alert_2 to be in input mode to stop driving the alert handshake control line ALERT_HAND. Therefore, each slave component 14A-14D of the bus system 1 enters the synchronization end phase ST_SyncEnd. In some embodiments, in the synchronization end phase ST_SyncEnd, each schedule controller 145A-145D waits for at least one clock pulse cycle, and then the schedule controller 145A-145D controls the slave components 14A-14D to enter the distribution phase ST_Ass from the synchronization end phase ST_SyncEnd.

[0086] In the distribution phase ST_Ass, the slave component 14B obtains the control right of the alert handshake control line ALERT_HAND so as to perform eSPI communication and SWDA communication with the master component 10. Therefore, at time point t23, the alert handshake control line ALERT_HAND becomes a low voltage level in phase PH2 of the distribution cycle AP2 of the slave component 14B. Thus, the slave component 14B can obtain the right to perform SWDA communication and / or eSPI communication. At the same time, the slave component 14B communicates with the master component 10 through its input / output signal line eSPI_IO2. In this distribution cycle AP2, the slave component 14B only performs eSPI communication. Therefore, the slave component 14B does not drive the alert handshake control line ALERT_HAND in phases PH3 and PH4. Next, since the slave component 14B still needs to perform eSPI communication and SWDA communication, the slave component 14B will drive the alert handshake control line ALERT_HAND in the phase PH2 of each distribution cycle AP2 until the eSPI communication and SWDA communication are completed. Figure 5B At time point t24, although the slave component 14B has completed the eSPI communication, the SWDA communication has not yet been completed, so the slave component 14B controls the alert handshake control line ALERT_HAND to a low voltage level in phase PH2 of the distribution cycle AP2 to continue the SWDA communication.

[0087] Figure 6 A connection configuration diagram of a bus system 1A according to some embodiments of the present invention is shown. As previously described, the bus 12 is an eSPI bus. The master component 10 is electrically connected to the slave components 14A-14N through the bus 12. In addition, the master component 10 performs eSPI communication with the slave components 14A-14N in a one-to-one mechanism, and the slave components 14A-14N communicate with the master component 10 according to an arbitration mechanism. It is worth noting that the number of slave components 14A-14N is only an example and is not intended to limit the present invention.

[0088] As previously described, the alert handshake pins of the slave components 14A-14N are electrically connected to the alert handshake control line ALERT_HAND. In some embodiments, the alert handshake control line ALERT_HAND is electrically connected to the power supply VDD through a pull-up resistor (not shown). In some embodiments, the alert handshake control line ALERT_HAND is electrically connected to the ground terminal GND through a pull-down resistor (not shown).

[0089] In some embodiments, any slave component 14A-14N in the bus system 1A can store non-real-time and important data in other slave components to disperse the risk of data being stolen when the bus system 1A is attacked. For example, the slave component 14A can store some important data (such as encryption / decryption keys, etc.) in other slave components 14B-14N. When the data is needed, the slave component 14A can communicate with the slave components 14B-14N through the alert handshake control line ALERT_HAND through SWDA communication. In addition, SWDA communication can support encrypted data transmission to avoid the risk of signals and packets on the alert handshake control line ALERT_HAND being stolen during the transmission process.

[0090] In some embodiments, when any slave component 14A-14N in the bus system 1A is busy, the slave component can provide the data to be processed to other idle slave components through SWDA communication so that other slave components can share part of the operation, so as to improve the system efficiency of the bus system 1A. For example, when the slave component 14A is busy, the slave component 14A can provide the data to be processed to the slave components 14B-14N through SWDA communication so as to share the operation. When the slave components 14B-14N complete the operation, they will transmit the processed data back to the slave component 14A or perform the corresponding operation.

[0091] In the bus system 1A, the slave components 14A-14N are further electrically connected to the peripheral components 15A-15M through the alert handshake control line ALERT_HAND. In some embodiments, the peripheral components 15A-15M are fans for cooling the bus system 1A. For example, when the slave component 14A is busy, the slave component 14A can notify one of the idle (or standby) slave components 14B-14N to control the fan 15A-15M through SWDA communication. Therefore, the idle slave components can use time-division multiplexing to control each fan 15A-15M in sequence through the alert handshake control line ALERT_HAND. In other words, in the bus system 1A, any one of the slave components 14A-14N can control each peripheral component 15A-15M through the alert handshake control line ALERT_HAND. In some embodiments, the number of slave components 14A-14N can be different from the number of peripheral components 15A-15M.

[0092] Figure 7 A diagram showing a connection configuration of a busbar system 1B according to some embodiments of the present invention. Figure 7 The busbar system 1B has a similar Figure 6The bus system 1A is similar to the bus system 1B, and the difference between the bus system 1B and the bus system 1A is that each peripheral component 15A-15N of the bus system 1B is controlled by a respective slave component 14A-14N. In some embodiments, the number of slave components 14A-14N may be the same as the number of peripheral components 15A-15N.

[0093] In the bus system 1B, the master control component 10 performs eSPI communication with the slave components 14A-14N in a one-to-one mechanism. Therefore, the master control component 10 cannot give instructions to the slave components 14A-14N through the bus 12 at the same time. By performing SWDA communication through the alert handshake control line ALERT_HAND, the instructions from the master control component 10 can be transmitted to other slave components, such as a one-to-many broadcast. Therefore, the time required for the master control component 10 to perform eSPI communication with the slave components 14A-14N individually through the bus 12 can be saved. For example, when the master control component 10 wants to turn off the peripheral components 15A-15N, the slave component 14A can turn off the peripheral component 15A after receiving the instruction to turn off the peripheral components 15A-15N and immediately notify the slave components 14B-14N through SWDA communication so as to turn off the peripheral components 15B-15N.

[0094] In some embodiments, when the slave component 14A receives a specific instruction from the master component 10 via the bus 12, the slave component 14A may first notify the slave component 14B via SWDA communication, so that the slave component 14B may perform related procedures in advance. Therefore, when the slave component 14B receives the specific instruction from the master component 10 via the bus 12, the slave component 14B may immediately perform the operation corresponding to the specific instruction and continue to notify the slave component 14C via SWDA communication, and so on, such as the operation of the branch prediction concept of the central processor. Therefore, other slave components may be notified in advance via SWDA communication to improve the performance of the bus system 1B.

[0095] According to an embodiment of the present invention, each slave component in the bus system 1 can perform SWDA communication through the alert handshake control line ALERT_HAND. Compared with the traditional bus system, the slave components of the bus systems 1, 1A and 1B can perform SWDA communication without additional pins. In addition, when the slave component performs eSPI communication with the master component, the slave component uses the window period of the alert handshake control line ALERT_HAND to perform SWDA communication, thereby increasing the efficiency and flexibility of the bus systems 1, 1A and 1B in scheduling.

[0096] Although the present invention has been described above with reference to the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of protection of the claims.

Claims

1. A busbar system, characterized in that: include: A main control element; an enhanced serial peripheral interface bus; as well as A plurality of slave components electrically connected to the master component via the enhanced sequence peripheral device interface bus; Each of the slave components has a warning handshake pin, and the warning handshake pins of the slave components are electrically connected together through a warning handshake control line; When the warning handshake control line is at a first voltage level and a first slave element of the plurality of slave elements wants to communicate with other slave elements, the first slave element controls the warning handshake control line to a second voltage level through the warning handshake pin, so that the plurality of slave elements enter a synchronization stage; wherein after the synchronization stage, in a first stage corresponding to the first slave element in a plurality of stages of each distribution cycle of a distribution stage, the first slave element controls the warning handshake control line to the second voltage level through the warning handshake pin, and in the stages other than the first stage in each distribution cycle, the first slave element controls the warning handshake control line to communicate with other slave elements through the warning handshake pin; In the stages other than the first stage in a first distribution cycle of the distribution stage, the first slave component controls the alert handshake control line through the alert handshake pin to transmit a target identification to other slave components so as to communicate with a second slave component of the slave component corresponding to the target identification.

2. The busbar system according to claim 1, characterized in that: In the phase other than the first phase in a second distribution cycle of the distribution phase, the first slave component controls the alert handshake control line through the alert handshake pin to transmit a first command to the second slave component, wherein the first distribution cycle is between the second distribution cycle and the synchronization phase.

3. The busbar system according to claim 1, characterized in that: When the other slave components detect that the warning handshake control line is at the second voltage level in the first phase of each distribution cycle, the other slave components further determine whether to communicate with the first slave component according to the target identification.

4. The busbar system according to claim 2, characterized in that: Corresponding to the first instruction, the second slave component receives and stores data from the first slave component through the warning handshake control line, wherein the received data includes a key or data to be calculated.

5. The busbar system according to claim 4, characterized in that: The second slave component determines whether to communicate with the master component according to the received data or the first instruction.

6. The busbar system according to claim 1, characterized in that: Also includes: A plurality of peripheral components are electrically connected to the plurality of slave components through the warning handshake control line, In each of the distribution cycles, in the phases other than the first phase, the first slave component controls the peripheral component via the alert handshake control line.

7. The busbar system according to claim 1, characterized in that: Also includes: A plurality of peripheral components, each of which is electrically connected to a respective one of the slave components; In each of the distribution cycles, in the phases other than the first phase, the first slave component communicates with the other slave components via the warning handshake control line so as to control the other peripheral components.

8. The busbar system according to claim 1, characterized in that: In each of the stages except the first stage in the distribution cycle, the first slave component further communicates with the master component through the enhanced sequence peripheral device interface bus to obtain a second instruction from the master component, and provides a third instruction corresponding to the second instruction to other slave components through the alert handshake control line.

9. A busbar system, characterized in that: include: A main control element; an enhanced serial peripheral interface bus; as well as A plurality of slave components electrically connected to the master component via the enhanced sequence peripheral device interface bus; Each of the slave components has a warning handshake pin, and the warning handshake pins of the slave components are electrically connected together through a warning handshake control line; When the warning handshake control line is at a first voltage level and a first slave element of the plurality of slave elements intends to communicate with the master element via the ESPI bus, the first slave element controls the warning handshake control line to a second voltage level via the warning handshake pin, so that the plurality of slave elements enter a synchronization phase; wherein after the synchronization phase, the other slave components except the first slave component detect the warning handshake control line in the other phases except a first phase corresponding to the first slave component in the multiple phases of each distribution cycle of a distribution phase, so as to determine whether to communicate with the first slave component through the warning handshake control line; In the stages other than the first stage in a first distribution cycle of the distribution stage, the first slave component controls the alert handshake control line through the alert handshake pin to transmit a target identification to other slave components so as to communicate with a second slave component of the slave component corresponding to the target identification.

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