Multi-FPGA Routing Method Based on Maze Algorithm

Abstract

The present invention relates to a multi-FPGA routing method based on a maze algorithm, comprising the following steps: Step S1: In the initial routing phase, a maze routing algorithm strategy is introduced to obtain an initial routing result; Step S2: In the updated routing phase, a wire removal and rewinding strategy is employed to reduce the number of edges on FPGA connection pairs; Step S3: Introducing a cost improvement strategy, which estimates the differences in cost weights for different edges, thereby obtaining a more optimal routing result in the wire removal and rewinding phase and optimizing the TDM ratio. By optimizing the routing results, the present invention effectively reduces corresponding system latency, thereby improving chip performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit computer-aided design, and in particular relates to a multi-FPGA wiring method based on a maze algorithm. Background Art

[0002] It's estimated that approximately 60% to 80% of the time spent designing an ASIC is spent on verification. Common logic verification methods include software logic simulation, hardware simulation, and Field Programmable Gate Array (FPGA) prototyping. Software simulation requires significant time and effort to simulate each logic gate, while hardware simulation is expensive to implement. With the continuous advancement of integrated circuit manufacturing processes and the increasing scale of chips, the shortcomings of these two logic verification methods are becoming increasingly apparent. FPGA prototyping can complete logic verification with minimal time and implementation costs, making it a widely used method in industry.

[0003] As chip designs continue to expand, a single FPGA becomes inadequate for large-scale chip designs. Consequently, large-scale chip designs are divided across multiple FPGAs. To complete chip design functions, FPGAs need to transmit signals to each other. Since the number of signals transmitted between FPGAs far exceeds the number of I / O pins between them, time-division multiplexing (TDM) technology has been proposed to address the issue of insufficient I / O pins. TDM uses the same physical signal line to transmit different signals. It divides the transmission time into non-overlapping time intervals, allocating each time interval to each signal, thereby enabling multiple signals to be transmitted on the same physical signal line. While TDM effectively addresses the issue of insufficient I / O pins, it significantly increases system latency. The TDM ratio is often used to measure the quality of routing results. While TDM was proposed to improve the availability of prototype systems, it also leads to a significant increase in system latency. Therefore, reducing the corresponding system latency to improve chip performance has become an urgent issue.

[0004] The signal multiplexing ratio can be used to measure system latency. Throughout the design process, the TDM ratio is typically determined after inter-FPGA routing. Common methods for optimizing the signal multiplexing ratio are based on integer linear programming. However, these methods typically use arbitrary integer TDM ratios, which falls short of practical requirements. While there are various methods for optimizing time-division multiplexing technology, achieving a good solution within a reasonable runtime is difficult.

[0005] In summary, for the design of multi-FPGA prototype systems, it is very critical to design a wiring method that simultaneously addresses the wiring scheme and the actual system delay optimization issues. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a multi-FPGA wiring method based on a maze algorithm, which improves chip performance by optimizing wiring results and effectively reducing corresponding system delays.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] A multi-FPGA routing method based on a maze algorithm includes the following steps:

[0009] Step S1: Introduce the maze routing algorithm strategy in the initial routing stage to obtain the initial routing result;

[0010] Step S2: using a wire removal and rewinding strategy to reduce the number of edges on the FPGA connection pairs during the update routing phase;

[0011] Step S3: Introduce a cost improvement strategy to estimate the difference in cost weights of different edges, so as to obtain a better wiring result in the wire removal and rewinding stage and optimize the TDM ratio.

[0012] Furthermore, the time division multiplexing ratio is used as an indicator to measure the system delay. In the system wiring diagram, each edge needs to calculate the TDM ratio through formula (1)

[0013]

[0014] Where De(e) is the demand for e, capacity is the capacity of e, and Tre(e) represents the TDM ratio.

[0015] Furthermore, the step S1 is specifically as follows:

[0016] In the wiring diagram, each FPGA can be regarded as a node, each connected FPGA connection pair can be regarded as a line segment connecting the nodes, and the cost can be regarded as the path cost through this FPGA connection pair;

[0017] First, the maze routing algorithm randomly selects a node from the nodes that need to be connected and sets it as V_Source, i.e. the initial node; the remaining nodes that need to be connected are V_Sink nodes, i.e. the target nodes;

[0018] Then, take the V_Source node as the wavefront node set and the V_Sink node as the target node set; secondly, calculate the cost of the V_Source node and its adjacent nodes, with the cost value being 1; and select the node V1 with the smallest cost compared to the V_Source node. If the V1 node is a V_Sink node, remove the node from the target node set. Then, add the node V1 with the smallest cost to the wavefront node set and update the cost of the nodes adjacent to the V1 node. The cost calculation formula for V1 is as follows

[0019] Cost = Cost V1 +1 (3)

[0020] Among them, Cost is the wiring cost of the node adjacent to the V1 node, Cost V1 is the wiring cost of V1 node;

[0021] Then, the above operation is repeated until the target node set is empty and the loop ends; finally, each network obtains the initial routing result through the maze routing algorithm.

[0022] Furthermore, the stitch removal and rewinding strategy is specifically as follows:

[0023] First, calculate the number of edges on each FPGA connection pair;

[0024] Next, determine whether the number of edges in the FPGA connection pair exceeds a threshold x, where the threshold x is the number of edges in the FPGA connection pair with the largest number of edges in the wiring diagram multiplied by 0.9. If the number of edges in the FPGA connection pair exceeds the threshold x, then the FPGA connection pair is considered a busy connection pair.

[0025] Finally, as long as one FPGA connection pair in the connection path between the two FPGAs is a busy connection pair, the connection path between the two FPGAs is removed.

[0026] Furthermore, after the connection path is removed, the two FPGAs need to be rewired. Specifically, the busy connection pairs are removed according to the wiring diagram to generate a rewiring diagram G'. Then, the two FPGAs are routed through the maze routing algorithm to find the shortest path in the rewiring diagram G'. If the cost of two shortest paths is the same, the one with fewer FPGA connection pairs is preferentially selected.

[0027] Furthermore, the cost improvement strategy is specifically as follows:

[0028] Divide the two FPGAs into a V_Source node and a V_Sink node; calculate the routing cost of the node Vn adjacent to the V_Source node. The cost calculation formula is as follows:

[0029] cost=back_cost(s,n)+α×estimate (3)

[0030] back_cost(s,n)=back_cost(s,n pre )+cost (4)

[0031]

[0032] Among them, cost(s,n) is the initial cost from the current node Vn to the V_Source node, back_cost(s,n) is the cost of each V_Sink node to the Vn node, estimate is the estimated path cost from the node V_Sink to V_Source, and α is the weight ratio of the estimated path cost.

[0033] Furthermore, the optimized TDM ratio is specifically:

[0034] Preprocess each network group and calculate the number of edges in each network group required to assign TDM ratio to each edge;

[0035] Calculate the weight ratio of each edge of the current FPGA connection pair, and then obtain the TDM ratio allocated to each edge of each line network;

[0036] Sort all the lines from largest to smallest according to their TDM ratios, increase the TDM ratios of the line groups whose TDM ratios are smaller than a preset value, and at the same time, decrease the TDM ratios of the line groups whose TDM ratios are larger than the preset value;

[0037] Perform legalization operations on the FPGA connection pairs that violate the TDM ratio constraint.

[0038] Furthermore, the weight ratio is calculated as follows:

[0039]

[0040] ngmec j,k ={x|x=max(ngec j,1 ,…,ngec j,β )} (7)

[0041] Among them, ng j,m It is ngl j The mth network group, ngec j,m It is a line network groupj,m The number of edges, ngmec j,k It is edge e j,k The maximum number of edges of the wire mesh group, β is ngl j Number of centerline network groups, pct j,k That is the weight ratio;

[0042] Based on the weight ratio, the TDM ratio is calculated as follows:

[0043]

[0044] Furthermore, the TDM ratio update formula is as follows:

[0045]

[0046] Among them, star is the optimization target of ngmtr defined by the user, mng_sum j is the TDM ratio of the network group with the largest TDM ratio, etr j,k For edge e j,k TDM ratio.

[0047] Furthermore, after the update step, if the FPGA connection is k If the TDM ratio constraint is satisfied, the new TDM ratio etr j，k Replace p k Middle side e j，k The TDM ratio before, on the contrary, if p k If the TDM ratio constraint cannot be satisfied, then the edge e with increased TDM ratio j，k Directly use the new TDM ratio etr' j，k , but the TDM ratio is reduced by j，k , should be legalized by the following formula:

[0048]

[0049] Among them, rec_sum is the TDM ratio reduced etr' after the update phase j,k The reciprocal sum of ad_sum is the increase in TDM ratio after the update phase etr' j,k The reciprocal sum of .

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] The present invention effectively reduces corresponding system delays to improve chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a schematic diagram of a time division multiplexing technology in one embodiment of the present invention;

[0053] Figure 2 This is a wiring diagram in one embodiment of the present invention;

[0054] Figure 3 FIG. 4 is a diagram showing TDM ratio allocation results in one embodiment of the present invention. DETAILED DESCRIPTION

[0055] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0056] The present invention provides a multi-FPGA wiring method based on a maze algorithm, comprising the following steps:

[0057] Step S1: Introduce the maze routing algorithm strategy in the initial routing stage to obtain the initial routing result;

[0058] Step S2: using a wire removal and rewinding strategy to reduce the number of edges on the FPGA connection pairs during the update routing phase;

[0059] Step S3: Introduce a cost improvement strategy to estimate the difference in cost weights of different edges, so as to obtain a better wiring result in the wire removal and rewinding stage and optimize the TDM ratio.

[0060] In this embodiment, the time division multiplexing ratio is used as an indicator to measure the system delay. In the wiring diagram of the system, each edge needs to calculate the TDM ratio by formula (1):

[0061]

[0062] Where De(e) is the demand for e, capacity is the capacity of e, and Tre(e) represents the TDM ratio.

[0063] refer to Figure 1 The figure below shows a simple diagram of time-division multiplexing between two FPGAs. The two rectangles, two trapezoids, and six squares represent the FPGA, converter, and sample, respectively. The three dashed arrows represent three different signals. The solid arrows are the physical connections between the two FPGAs. Within a system clock cycle, only one signal can be transmitted between the two FPGAs via a single physical conductor. However, using TDM, three different signals can be transmitted via a single physical conductor within a single system cycle. Therefore, time-division multiplexing improves system routability.

[0064] Given a network set N consisting of dual FPGA networks or multiple FPGA networks. Given a network group set NG, each network group ng i ∈NG. Given a set of FPGA connection pairs P, each FPGA connection pair p kConnect two FPGAs. Given an FPGA set F, there is at most one FPGA connection pair between every two FPGAs. Each network n j May belong to different network groups, the network group subset has

[0065] The basic requirement of the FPGA prototype system wiring problem is to connect all FPGAs of each network together through FPGA connection pairs. In addition, each network n j Each FPGA connection pair used k The generated edge e j,k Assign a TDM ratio. According to the requirements of the actual problem, the TDM ratio needs to meet the following requirements.

[0066]

[0067] Among them, e j,k It is the FPGA connection to each edge on the epl, epl k is the set of edges connected to the FPGA, etr j,k Every e j,k TDM ratio.

[0068] In this embodiment, the maze wiring strategy is specifically as follows:

[0069] FPGA prototype systems are composed of multiple network groups. A network group is composed of numerous network groups. A network consists of multiple FPGA-to-FPGA connection pairs. There are often more than one optional line between two FPGAs, and sometimes dozens. The routing of a network can have a variety of outcomes. Different routing results can affect system latency and, in turn, chip performance. Therefore, to obtain a routing diagram that minimizes system latency, the present invention uses a maze routing algorithm for routing.

[0070] To generate a minimal-cost routing diagram, a maze algorithm is applied to routing, generating a minimum spanning tree (MST) to reduce system latency. In the routing diagram, each FPGA can be considered a node, each connected FPGA pair can be considered a line segment connecting the nodes, and the cost can be considered the path cost of the path through this FPGA pair. First, the maze routing algorithm randomly selects a node from the nodes to be connected and sets it as V_Source, the initial node. The remaining nodes to be connected are designated as V_Sink nodes, the target nodes. The V_Source node is then used as the wavefront node set, and the V_Sink node as the target node set. Next, the cost of the V_Source node and its adjacent nodes is calculated, with the cost value set to 1. The node V1 with the lowest cost relative to the V_Source node is selected. If V1 is a V_Sink node, it is removed from the target node set. Node V1 with the lowest cost is then added to the wavefront node set, and the costs of the nodes adjacent to V1 are updated. The cost calculation formula for V1 is as follows.

[0071] Cost = Cost V1 +1 (3)

[0072] Among them, Cost is the wiring cost of the node adjacent to the V1 node, Cost V1 is the wiring cost of the V1 node.

[0073] Then, the above operation is repeated until the target node set is empty and the loop ends. Finally, each network is routed through the maze routing algorithm to obtain the initial routing result.

[0074] In this embodiment, the stitch removal and rewinding strategy is specifically as follows:

[0075] Because the TDM ratio is linearly related to the number of edges passing through each FPGA connection pair, the maze routing algorithm can cause excessive edges to pass through some FPGA connection pairs, resulting in an excessively high TDM ratio for these edges and increased system latency. Therefore, reducing the maximum number of edges within a channel can effectively lower the TDM ratio, thereby reducing system latency. Therefore, the present invention uses a wire removal and rewinding strategy to mitigate the problem of excessive edges on some FPGA connection pairs.

[0076] During the wiring removal phase, consider removing connection paths with a large number of edges on FPGA connection pairs. First, calculate the number of edges on each FPGA connection pair. Then, determine whether the number of edges on the FPGA connection pair exceeds a threshold x, where the threshold x is the number of edges on the FPGA connection pair with the largest number of edges in the wiring diagram multiplied by 0.9. If the number of edges on the FPGA connection pair exceeds the threshold x, the FPGA connection pair is considered a busy connection pair. Finally, if at least one FPGA connection pair in the connection path between two FPGAs is a busy connection pair, the connection path between the two FPGAs is removed.

[0077] After removing the connection path, the two FPGAs need to be rerouted. First, based on the routing diagram, busy connection pairs are removed to generate a rerouted graph G'. Then, a maze routing algorithm is used to find the shortest path between the two FPGAs in the rerouted graph G'. If two shortest paths have the same cost, the one with the fewer FPGA connection pairs is preferred.

[0078] In this embodiment, the cost improvement strategy is specifically as follows:

[0079] When generating initial routing results, the default routing cost between FPGA connection pairs is set to 1. However, during the wire removal and rewinding phase, factors such as the number of edges on the wire net need to be considered to achieve better routing results. Therefore, a cost improvement strategy is needed to calculate the routing cost during the rewinding phase.

[0080] First, the two FPGAs are divided into a V_Source node and a V_Sink node. Then, the routing cost of the node Vn adjacent to the V_Source node is calculated. The cost calculation formula is as follows.

[0081] cost=back_cost(s,n)+α×estimate (3)

[0082] back_cost(s,n)=back_cost(s,n pre )+cost (4)

[0083]

[0084] Among them, cost(s,n) is the initial cost from the current node Vn to the V_Source node, back_cost(s,n) is the cost of each V_Sink node to the Vn node, estimate is the estimated path cost from the node V_Sink to V_Source, and α is the weight ratio of the estimated path cost.

[0085] In this embodiment, the TDM ratio optimization method is specifically as follows:

[0086] First, preprocess each net group to calculate the number of edges in each net group required to assign a TDM ratio to each edge. Then, calculate the weight ratio of each edge in the current FPGA connection pair to obtain the TDM ratio assigned to each edge in each net. For each edge, the weight ratio is calculated as follows:

[0087]

[0088] ngmec j,k ={x|x=max(ngec j,1 ,…,ngec j,β )} (7)

[0089] Among them, ng j,m It is ngl j The mth network group, ngec j,m It is a line network group j,m The number of edges, ngmec j,k It is edge e j,k The maximum number of edges of the wire mesh group, β is ngl j Number of centerline network groups, pct j,k This is the weight ratio. Based on this weight ratio, the TDM ratio of this edge is calculated as follows:

[0090]

[0091] When calculating the initial TDM ratio, the maximum number of edges for a network group is not exactly consistent with the TDM ratio, so the TDM ratio needs to be optimized. Therefore, after the initial allocation, the TDM ratio needs to be reduced through system delay optimization methods to achieve the optimal maximum TDM ratio for all network groups.

[0092] The algorithm consists of three main steps. The first step is to sort all the nets from largest to smallest according to their TDM ratio. Since reducing the TDM ratio of the previous net will reduce the optimization space for the TDM ratio of the subsequent nets, following this order allows for flexible optimization of the net groups with the largest TDM ratio.

[0093] The second step is the update step. In this step, the TDM ratio of the wire net group with a smaller TDM ratio needs to be increased, while the TDM ratio of the wire net group with a larger TDM ratio needs to be reduced. By increasing the TDM ratio of the wire net group with a smaller TDM ratio, the TDM ratio on the FPGA connection pair can be inversely reduced, thereby obtaining more room for optimization of the TDM ratio of the wire net group with a larger TDM ratio. Figure 2 and Figure 3As shown, the TDM ratios for FPGA connection pair P1 are 2, 4, and 6, respectively. Since 1 / 2 + 1 / 4 + 1 / 6 < 1, FPGA connection pair P1 satisfies the TDM ratio constraint. However, the sum of the reciprocals of the TDM ratios of 2, 4, and 6 for FPGA connection pair P1 differs from the constraint target value of 1 by 1 / 12, leaving room for improvement. Therefore, the TDM ratios of the network groups with larger TDM ratios need to be further reduced. The updated formula is shown below.

[0094]

[0095] Among them, star is the optimization target of ngmtr defined by the user, mng_sum j is the TDM ratio of the network group with the largest TDM ratio, etr j,k For edge e j,k The TDM ratio of the maximum network group can be calculated by this formula to obtain a new ratio, thereby reducing the TDM ratio of the maximum network group and further reducing the system delay.

[0096] The third step is to legalize the TDM ratio after the update phase. After the update step in the second step, some FPGA connection pairs may violate the TDM ratio constraint. Therefore, we need to legalize these FPGA connection pairs. After the update step, if the FPGA connection pair p k If the TDM ratio constraint is satisfied, the new TDM ratio etr j，k Replace p k Middle side e j，k The previous TDM ratio. On the contrary, if p k If the TDM ratio constraint cannot be satisfied, then the edge e with increased TDM ratio j，k You can directly use the new TDM ratio etr' j，k But the TDM ratio is reduced j，k , should be legalized by the following formula.

[0097]

[0098] Among them, rec_sum is the TDM ratio reduced etr' after the update phase j,k The reciprocal sum of ad_sum is the increase in TDM ratio after the update phase etr' j,k The reciprocal sum of .

[0099] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A multi-FPGA wiring method based on a maze algorithm, characterized in that: The following steps are involved: Step S1: Introduce the maze routing algorithm strategy in the initial routing stage to obtain the initial routing result; Step S2: using a wire removal and rewinding strategy to reduce the number of edges on the FPGA connection pairs during the update routing phase; Step S3: Introducing a cost improvement strategy, by estimating different cost weights for different edges, to obtain a better routing result during the wire removal and rewinding phase and optimize the TDM ratio; The step S1 is specifically as follows: In the wiring diagram, each FPGA is considered a node, each connected FPGA connection pair is considered a line segment connecting the nodes, and the cost is considered the path cost through this FPGA connection pair; (1) The maze routing algorithm randomly selects a node from the nodes that need to be connected and sets it as V_Source, i.e., the initial node; the remaining nodes that need to be connected are V_Sink nodes, i.e., the target nodes; (2) Take the V_Source node as the wavefront node set and the V_Sink node as the target node set; secondly, calculate the cost of the V_Source node and its adjacent nodes, with the cost value being 1; and select the node V1 with the smallest cost compared to the V_Source node; if the V1 node is a V_Sink node, remove the node from the target node set; then, add the node V1 with the smallest cost to the wavefront node set and update the cost of the nodes adjacent to the V1 node. The cost calculation formula for V1 is as follows: Cost=Cost V1 +1 Among them, Cost is the wiring cost of the node adjacent to the V1 node, Cost V1 is the wiring cost of V1 node; Then, repeat the above (1)-(2) operations until the target node set is empty and the loop ends. Finally, each network obtains the initial routing result through the maze routing algorithm. The cost improvement strategy is specifically as follows: Divide the two FPGAs into a V_Source node and a V_Sink node; calculate the routing cost of the node Vn adjacent to the V_Source node; the cost calculation formula is as follows: cost=back_cost(s,n)+α×estimate back_cost(s,n)=back_cost(s,n pre )+cost Among them, cost(s,n) is the initial cost from the current node Vn to the V_Source node, back_cost(s,n) is the cost of each V_Sink node to the Vn node, estimate is the estimated path cost from the node V_Sink to V_Source, and α is the weight ratio of the estimated path cost.

2. The multi-FPGA wiring method based on the maze algorithm according to claim 1, characterized in that: The time division multiplexing ratio is used as an indicator to measure system delay. In the system wiring diagram, each edge needs to calculate the TDM ratio using the following formula Where De(e) is the demand for e, capacity is the capacity of e, and Tre(e) represents the TDM ratio.

3. The multi-FPGA wiring method based on the maze algorithm according to claim 1, characterized in that: The stitch removal and rewinding strategy is specifically as follows: First, calculate the number of edges on each FPGA connection pair; Then, determine whether the number of edges on the FPGA connection pair exceeds a threshold x, where the threshold x is the number of edges of the FPGA connection pair with the largest number of edges in the wiring diagram multiplied by 0.9; if the number of edges on the FPGA connection pair exceeds the threshold x, then the FPGA connection pair is considered a busy connection pair; Finally, as long as one FPGA connection pair in the connection path between the two FPGAs is a busy connection pair, the connection path between the two FPGAs is removed.

4. The multi-FPGA wiring method based on the maze algorithm according to claim 3, characterized in that: After removing the connection path, the two FPGAs need to be rewired. Specifically, the following steps are performed: first, the busy connection pairs are removed according to the wiring diagram to generate a rewiring diagram G'. Then, the two FPGAs are routed through the rewiring diagram G' using a maze routing algorithm to find the shortest path. If two shortest paths have the same cost, the one with fewer FPGA connection pairs is preferred.

5. The multi-FPGA wiring method based on the maze algorithm according to claim 1, characterized in that: The optimized TDM ratio is specifically: Preprocess each network group and calculate the number of edges in each network group required to assign TDM ratio to each edge; Calculate the weight ratio of each edge of the current FPGA connection pair, and then obtain the TDM ratio allocated to each edge of each line network; Sort all the lines from largest to smallest according to their TDM ratios, increase the TDM ratios of the line groups whose TDM ratios are smaller than a preset value, and at the same time, decrease the TDM ratios of the line groups whose TDM ratios are larger than the preset value; Perform legalization operations on the FPGA connection pairs that violate the TDM ratio constraint.

6. The multi-FPGA wiring method based on the maze algorithm according to claim 5, characterized in that: The weight ratio is calculated as follows: moisture j,k [x|x=max(knowledge j,1 ,…,knowledge j,β )} Among them, ng j,m It is ngl j The mth network group, ngec j,m It is a line network group j,m The number of edges, ngmec j,k It is edge e j,k The maximum number of edges of the network group, β is ngl j Number of midline network groups, pct j,k That is the weight ratio; Based on the weight ratio, the TDM ratio is calculated as follows:

7. The multi-FPGA wiring method based on the maze algorithm according to claim 5, characterized in that: The TDM ratio update formula is as follows: Among them, star is the optimization target of ngmtr defined by the user, mng_sum j is the TDM ratio of the network group with the largest TDM ratio, etr j,k For edge e j,k TDM ratio.

8. The multi-FPGA wiring method based on the maze algorithm according to claim 5, characterized in that: After the update step, if the FPGA connection is k If the TDM ratio constraint is satisfied, the new TDM ratio etr j，k Replace p k Middle side e j，k The TDM ratio before, on the contrary, if p k If the TDM ratio constraint cannot be satisfied, then the edge e with increased TDM ratio j，k Directly use the new TDM ratio etr' j，k But the TDM ratio decreases j,k , should be legalized by the following formula: Among them, rec_sum is the TDM ratio reduced etr' after the update phase j,k The reciprocal sum of ad_sum is the increase in TDM ratio after the update phase etr' j,k The reciprocal sum of .

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