Dynamic random access memory with refresh architecture and clear circuit

Abstract

A dynamic random access memory is disclosed. The dynamic random access memory includes a first sustain voltage source, a dynamic random access memory cell, a sense amplifier, a voltage equalization circuit and a clearing circuit. The first sustain voltage source generates a first voltage. The dynamic random access memory cell includes an access transistor and a storage capacitor. The sense amplifier is coupled to a bit line and a complementary bit line. The voltage equalization circuit connects the bit line and the complementary bit line to a preset reference voltage during a voltage equalization period. The first sustain voltage source is electrically coupled to the bit line during an off period of the access transistor, and the clearing circuit is activated during the voltage equalization period to reduce a difference between a voltage on the bit line and a target reference voltage. Thus, the present invention can achieve the correct bit line equalization voltage during the voltage equalization period and the correct development voltage following the next activation command.

Description

TECHNICAL FIELD

[0001] The present invention relates to a dynamic random access memory, and more particularly, to a dynamic random access memory with a sustain memory architecture and a cleaning circuit. BACKGROUND

[0002] In the prior art, the most widely used dynamic random access memory (DRAM) cell comprises an access transistor and a storage capacitor, wherein the source of the access transistor is connected to the storage capacitor and the drain of the access transistor is connected to a bit line. The bit line is connected to a first level sense amplifier, and the first level sense amplifier is used to transmit a signal read out from the dynamic random access memory cell through column switches to a second level sense amplifier, wherein the second level sense amplifier is connected to an input / output line (i.e. a data line). During a write operation, a signal driven by an input / output buffer is stabilized at the data line, and the data line further stabilizes the signal driven by the input / output buffer through the first level sense amplifier to write the correct signal to the storage capacitor through the access transistor. During the active mode of the access transistor (i.e. the opening period of the access transistor), the access transistor is responsible for the read operation of the storage capacitor or the write operation of the storage capacitor, and during the inactive mode of the access transistor (i.e. the closing period of the access transistor), the access transistor can prevent the data stored in the storage capacitor from being lost.

[0003] In the prior art, the access transistor is designed with a high threshold voltage to minimize the leakage current through the access transistor, but the consequent disadvantage is that the performance of the access transistor is reduced when the access transistor is turned on. Therefore, the word line connected to the gate of the access transistor must be boosted or connected to a high voltage VPP (usually from a word line driver) to allow the access transistor to have high driving capability to write a signal to the storage capacitor, where the voltage VPP is loaded to the word line or the gate of the access transistor by the word line driver. Because the voltage VPP is a high voltage stress applied to the access transistor, the dielectric material (e.g., oxide layer or high-k material) of the gate of the access transistor must be thicker than the dielectric material of the gate applied to other support circuits or peripheral circuits (e.g., command decoder, address decoder and other input / output circuits, etc.) of the dynamic random access memory cell. Therefore, the design of the access transistor faces the challenge of having to maintain high performance or high reliability, and a difficult trade-off between the reliability and performance of the access transistor must be made. However, in the prior art, the design of the access transistor is more focused on achieving high reliability of the access transistor, but at the same time, the performance of the access transistor must be sacrificed.

[0004] In summary, regarding the design of the access transistor, the access transistor must have the high threshold voltage to reduce the leakage current of the access transistor (where reducing the leakage current of the access transistor helps to prolong the retention time of the charge stored in the storage capacitor), have a thick gate dielectric material to withstand a high word line voltage (e.g., voltage VPP), and sacrifice the performance of the access transistor. Therefore, it will take a longer time to reach or not be able to fully reach the voltage VCCSA corresponding to the signal "ONE" by the access transistor writing a high level signal (i.e., a signal "ONE", where the signal "ONE" usually corresponds to the voltage VCCSA as shown) to the storage capacitor. That is, the write time (WRITE time) spent on fully writing the voltage VCCSA corresponding to the signal "ONE" to the storage capacitor will be longer. Figure 1A

[0005] In addition, please refer again to Figure 1A wherein Figure 1A ​is a schematic diagram illustrating the most commonly used design of the DRAM cell, and the DRAM cell comprises an access transistor 11 and a storage capacitor 12. The gate of the access transistor 11 is coupled to a word line WL and a sense amplifier 20 (with 4 cross-coupled transistors) is coupled to the access transistor 11 through a bit line BL, wherein the sense amplifier 20 is composed of P-type metal-oxide-semiconductor transistors P1, P2 and N-type metal-oxide-semiconductor transistors N1, N2, and the coupling relationship of the P-type metal-oxide-semiconductor transistors P1, P2 and the N-type metal-oxide-semiconductor transistors N1, N2 can refer to Figure 1A , which will not be described herein again. In addition, as shown in Figure 1A , a node SAP (close to one side of the P-type metal-oxide-semiconductor transistors P1, P2 of the sense amplifier 20) connects the two P-type metal-oxide-semiconductor transistors P1, P2 in the sense amplifier 20, and a node SAN (close to one side of the N-type metal-oxide-semiconductor transistors N1, N2 of the sense amplifier 20) connects the two N-type metal-oxide-semiconductor transistors N1, N2 in the sense amplifier 20. When the switch transistor between the voltage VCCSA and the node SAP is turned on, the voltage value of the node SAP is almost equal to the voltage VCCSA (or the supply voltage VCC), wherein the supply voltage VCC usually also corresponds to the signal "ONE" stored in the DRAM cell. Similarly, when the switch transistor between the voltage VSS and the node SAN is turned on, the voltage value of the node SAN is almost equal to the voltage VSS or the ground level GND, wherein the ground level GND usually corresponds to the signal "ZERO" stored in the DRAM cell.

[0006] The dynamic random access memory cell utilizes the access transistor 11 as a switch to control the storage of charge to the storage capacitor 12 through the bit line BL during the WRITE operation, or to transfer the charge stored in the storage capacitor 12 to the bit line BL during the READ operation, where a plurality of dynamic random access memory cells are connected to the bit line BL. For example, the sense amplifier 20 latches the signal "ONE" (where the signal "ONE" can be, for example, 1.2V, and the signal "ONE" is typically the voltage VCCSA or the supply voltage VCC provided to the sense amplifier 20) or the signal "ZERO" (where the signal "ZERO" can be, for example, 0V, and the signal "ZERO" is typically the level or voltage VSS of the ground terminal GND provided to the sense amplifier 20) by amplifying the signal transferred to the bit line BL from the dynamic random access memory cell during the READ operation, or the external write signal "ONE" or the signal "ZERO" is applied to the sense amplifier 20 to store the correct signal to the storage capacitor 12 of the dynamic random access memory cell during the WRITE operation.

[0007] Please refer to Figure 1B , Figure 1B is a schematic diagram illustrating the waveforms of the voltages associated with the dynamic random access memory cell during the access (READ or WRITE) operation. For example, the design of the dynamic random access memory cell (25 nanometer (nm) process) typically has the following parameters associated with the design of the dynamic random access memory cell array: the voltage of the signal "ONE" on the bit line BL is 1.2V, the turn-on voltage on the word line WL is 2.7V (i.e., the voltage VPP is 2.7V), and the standby voltage on the word line WL is about -0.3V, the threshold voltage is between 0.7V and 0.9V, the gate dielectric of the access transistor 11 has to withstand a voltage of 2.7V (where the gate dielectric of the access transistor 11 has to withstand a voltage of 3.4V under burn-in stress to maintain an acceptable reliability margin), and thick gate dielectric of the access transistor 11 has to be used, where the thick gate dielectric of the access transistor 11 sacrifices the performance of the access transistor 11.

[0008] As Figure 1BAs shown, the storage capacitor 12 is initially in a standby mode (or the inactive mode) (i.e., the access transistor 11 is off), and the voltage on the word line WL is -0.3 V (the standby voltage). The voltages on the bit line BL and a bit line BLB are equalized to a voltage half-VCCSA (0.6 V) by a voltage equalization circuit to be described later, where the voltage half-VCCSA is between the voltage VCCSA (1.2 V) and 0 V.

[0009] When the storage capacitor 12 enters the active mode (i.e., the access transistor 11 is on) to start the access operation, the voltage on the word line WL is boosted from the standby voltage (-0.3 V) to a voltage VPP (e.g., 2.7 V), where the voltage VPP is greater than the sum of the voltage VCCSA (1.2 V) and a threshold voltage VT (which can be 0.7 V or 0.8 V) of the access transistor 11 to provide a sufficient driving force on the gate-source voltage of the access transistor 11 (e.g., 2.7 V - 1.2 V - 0.8 V = 0.7 V). In addition, because the access transistor 11 is on, the bit line BL coupled to the storage capacitor 12 can be shared with the storage capacitor 12. As shown, during the access (read or write) operation, the voltage on the word line WL is continuously maintained at the voltage VPP, and the sense amplifier 20 amplifies the voltage difference between the bit line BL and the bit line BLB. Figure 1B

[0010] Furthermore, after the access operation, a restore phase is performed. During the restore phase, the sense amplifier 20 recharges the storage capacitor 12 according to the signal "ONE" or the signal "ZERO" stored in the storage capacitor 12. After the restore phase, the voltage on the word line WL is pulled down from the voltage VPP to the standby voltage (-0.3 V), causing the access transistor 11 to be in the inactive mode again (i.e., the access transistor 11 is off again).

[0011] To explain the operation of the dynamic random access memory cell described above in detail, the following uses the access (read) operation of the dynamic random access memory cell with the stored signal "ONE" as an example, and the following contents are quoted from pages 362-365 of the book "Memory Systems - Cache Dram and Disk" published by Elsevier Inc. in 2008, where the authors of "Memory Systems - Cache Dram and Disk" are Bruce Jacob et al., and the contents of pages 362-365 are incorporated herein by reference. Please refer to Figure 1C Figure 1C ​​is a schematic diagram illustrating a dynamic random access memory cell having a sense amplifier (or sense circuit) 20 and a voltage equalization circuit 21 in the prior art. The voltage equalization circuit 21 ensures that the voltages on the bit line pair BL, BLB are as closely matched as possible. As previously mentioned, the sense amplifier 20 comprises four cross-coupled transistors (i.e. two P-type metal-oxide-semiconductor transistors and two N-type metal-oxide-semiconductor transistors). The sense amplifier 20 can be activated based on the signals on the nodes SAN and SAP (i.e. as shown in Figure 1A , the nodes SAN and SAP are connected to the voltages VSS and VCCSA respectively) to drive the voltages on the bit line pair BL, BLB to the limits of the complementary voltages (i.e. the bit line BL is driven to the voltage VCCSA as shown in Figure 1A , and the bit line BLB is driven to the voltage VSS as shown in Figure 1A ). After the nodes SAN and SAP are connected to the voltages VSS and VCCSA respectively, the voltage on the bit line BL can be driven to a full voltage level, i.e. the bit line BL is fully driven. The column select line CSL is then turned on to allow the fully driven voltage to reach the output terminals OUTPUT and OUTPUTB which form an output differential pair, and to be read out from the dynamic random access memory cell. At this point, the access transistor 11 is still in an on state, so the fully driven voltage on the bit line BL can re-charge the storage capacitor 12.

[0012] based on an access (read) operation on the dynamic random access memory cell, Figures 1D-1G four different phases are shown in relation to the operation of the sense amplifier 20, which include a pre-charge phase, an access phase, a sense phase, and a restore phase. First, as shown in Figure 1D , in the pre-charge phase (i.e. phase (0)), the bit line pair BL, BLB is pre-charged to a reference voltage VREF (where the reference voltage VREF is equal to half of the supply voltage VCC, i.e. the reference voltage VREF is between the level of the supply voltage VCC and the ground terminal GND). In the pre-charge phase, the voltage equalization circuit 21 is activated to transfer the reference voltage VREF to the bit line pair BL, BLB, i.e. both the bit line BL and the bit line BLB (also known as the complementary bit line) are pre-charged to the reference voltage VREF. In addition, in the pre-charge phase, the sense amplifier 20 is not activated. In addition, as shown in Figure 1DAs shown, "1" represents the signal "ONE" and "0" represents the signal "ZERO".

[0013] Then, as Figure 1E As shown, during the access phase (i.e., phase (1)), the voltage equalization circuit 21 is not activated, and a voltage (e.g., VCC+VT or such) is applied. Figure 1B The voltage VPP shown is applied to a word line WL corresponding to the dynamic random access memory (DRAM) cell. The voltage on word line WL can activate or activate the access transistor 11 of the DRAM cell, and then the storage capacitor 12 of the DRAM cell releases its contents onto bit line BL through charge sharing, wherein... Figure 1E As shown, the storage capacitor 12 stores the signal "ONE". Therefore, the shared charge can slightly increase the voltage on the bit line BL from VREF to VREF+. Then, because of the change in voltage on the bit line BL, the voltage on the bit line BL begins to affect the operation of the sensing amplifier 20. For example, a slightly higher voltage on the bit line BL (i.e., voltage VREF+) begins to drive the N-type metal-oxide-semiconductor transistor below the sensing amplifier 20 to be more conductive than the N-type metal-oxide-semiconductor transistor above the sensing amplifier 20. Conversely, a slightly higher voltage on the bit line BL (i.e., voltage VREF+) also begins to drive the P-type metal-oxide-semiconductor transistor below the sensing amplifier 20 to be less conductive than the P-type metal-oxide-semiconductor transistor above the sensing amplifier 20. Therefore, the voltage VREF+ on the bit line BL biases the sensing amplifier 20 for subsequent sensing stages.

[0014] After that, as Figure 1F As shown, during the sensing phase (i.e., phase (2)), the voltage equalization circuit 21 is still not activated. At this time, the small voltage difference between the voltage on bit line BL and the voltage on bit line BLB will drive a bias to the sensing amplifier 20, so the signal on node SAN will reduce the voltage on bit line BLB. Because the signal on node SAN is turned on (i.e., node SAN is connected to...), Figure 1A The voltage VSS or ground level shown below (the lower N-type metal-oxide-semiconductor transistor) allows the signal on node SAN to drive the voltage on bit line BLB from the reference voltage VREF to the ground level GND (that is, the voltage on bit line BLB decreases from the reference voltage VREF to voltage VREF-, and then to the ground level GND (signal "ZERO")). Similarly, the signal on node SAP (that is, the signal on node SAP connected to...) Figure 1AThe voltage VCCSA (or supply voltage VCC) shown can drive the voltage on bit line BL to the full voltage value, where the full voltage value represents the signal "ONE" and the signal "ONE" corresponds to voltage VCCSA or supply voltage VCC. Additionally, signals on node SAN and node SAP can jointly force the sensing amplifier 20 to be driven to its respective maximum or minimum voltage rail.

[0015] Finally, as Figure 1G As shown, in the recovery phase (i.e., phase (3)), after the voltage on bit line BL and the voltage on bit line BLB are driven to their respective maximum values ​​(voltage VCCSA or supply voltage VCC) and minimum values ​​(voltage VSS or ground level GND), word line WL is still in the startup state. Therefore, the fully driven voltage (VCCSA or VCC) on bit line BL can now restore the charge in storage capacitor 12 through access transistor 11. It is worth noting that in the recovery phase, as Figure 1G As shown, the dynamic random access memory unit restores the charge in the storage capacitor 12 using voltage VCCSA or supply voltage VCC, where voltage VCCSA or supply voltage VCC corresponds to the signal "ONE". Therefore, the voltage stored in the storage capacitor 12 will be the same as or substantially the same as the voltage of the signal "ONE".

[0016] Please refer to Figure 1H , Figure 1H This means that in Figures 1D-1G A schematic diagram of the signals on the SAN node, the signals on the SAP node, the voltage on the bit line BL, and the voltage on the word line WL. Before the access phase (i.e., phase (0)), the voltage on the bit line BL is pre-charged to the reference voltage VREF (VCC / 2). During the access phase (i.e., phase (1)), the voltage on the word line WL can be driven to be at least VT higher than the supply voltage VCC, and the storage capacitor 12 of the dynamic random access memory cell can release its contents onto the bit line BL through the charge sharing, and slightly raise the voltage on the bit line BL from VREF to VREF+. During the sensing phase (i.e., phase (2)), the signals on the SAP node (i.e., the signals on the SAP node, the voltage on the word line WL) are pre-charged to the reference voltage VREF (VCC / 2). Figure 1A The voltage VCCSA (or supply voltage VCC) shown can drive the voltage on bit line BL to the full voltage value, where the full voltage value represents the signal "ONE". Then, in the recovery phase (i.e., phase (3)), the voltage VCCSA or supply voltage VCC on bit line BL corresponding to the signal "ONE" can restore the charge in the storage capacitor 12 in the dynamic random access memory cell.

[0017] Thus, according to the above Figures 1C-1H In the pre-charge phase, bit line BL (e.g.)Figure 1H The voltage on the bit line BL (shown by the dotted line) can be pre-charged to the reference voltage VREF (or VCC / 2) by the voltage equalization circuit 21. Then, during the access phase, after the access transistor 11 is turned on, the voltage on the bit line BL can be raised from VREF to VREF+ by the charge sharing. Then, during the sense phase, the node SAP connected to the voltage VCCSA (or the supply voltage VCC) as shown can pull the voltage on the bit line BL from the voltage VREF+ to close to the voltage VCCSA (or the supply voltage VCC), where the voltage VCCSA (or the supply voltage VCC) corresponds to the signal “ONE”. Finally, during the recovery phase, because the sense amplifier 20 is still in the active state, the voltage VCCSA (or the supply voltage VCC) coupled to the bit line BL can recover the charge in the storage capacitor 12 through the sense amplifier 20. Thus, from the access phase through the sense phase to the recovery phase, only the voltage VCCSA (or the supply voltage VCC) connects the sense amplifier 20 through the node SAP and only the low voltage VSS (or the level of the ground GND) connects the sense amplifier 20 through the node SAN, without any other voltage connecting the sense amplifier 20. Figure 1A

[0018] However, the high voltage stress caused by the voltage VPP will cause the gate of the access transistor 11 to be designed with a thicker dielectric material, where the dielectric material of the gate of the access transistor 11 is thicker than the dielectric material of the gate of the transistors applied in the peripheral circuits of the dynamic random access memory unit, and the thicker dielectric material of the gate of the access transistor 11 will reduce the performance of the access transistor 11 (e.g. the short channel effect of the access transistor 11 is more serious, the ratio of the on / off current of the access transistor 11 is smaller, and the swing slope that measures the response ability of the on / off of the access transistor 11 is worse, etc.). In addition, although the threshold voltage is higher than the threshold voltage of the transistors applied in the peripheral circuits of the dynamic random access memory unit, the leakage current through the access transistor 11 during the standby mode or the inactive mode is still large enough to reduce the storage charge in the storage capacitor 12 required for sensing. Especially in the process of 12 nanometer or 7 nanometer fin field-effect transistor (FinFET), when the voltage VCCSA is low (e.g. 0.6V), the leakage current of the access transistor 11 during the standby mode or the inactive mode will become worse. SUMMARY

[0019] ​Therefore, a dynamic random access memory (DRAM) with a sustainable storage structure and a cleaning circuit is disclosed. According to an embodiment of the present application, the DRAM includes a first sustain voltage source, a DRAM cell, a sense amplifier, a voltage equalization circuit, and a cleaning circuit. The first sustain voltage source is configured to generate a first voltage, wherein the first voltage is higher than a voltage of a high level signal applied in the DRAM. The DRAM cell includes an access transistor and a storage capacitor. The sense amplifier is coupled to a bit line and a complementary bit line, wherein the bit line is coupled to the storage capacitor through the access transistor. The voltage equalization circuit is coupled to the bit line and the complementary bit line, wherein the voltage equalization circuit connects the bit line and the complementary bit line to a preset reference voltage during a voltage equalization period. The cleaning circuit is coupled to the sense amplifier or the voltage equalization circuit. The first sustain voltage source is electrically coupled to the bit line during a turn-off period of the access transistor, and the cleaning circuit is activated to reduce a difference between a voltage on the bit line and a target reference voltage during the voltage equalization period.

[0020] According to an embodiment of the present application, the DRAM further includes a word line. The word line is coupled to a gate of the access transistor, wherein the word line is selected to turn on the access transistor in a first period and a second period, the second period is after the first period, and the first sustain voltage source is electrically coupled to the bit line in the second period.

[0021] According to an embodiment of the present application, the first sustain voltage source is electrically coupled to the sense amplifier in the second period, and the first sustain voltage source is electrically coupled to the storage capacitor of the DRAM cell through the sense amplifier and the bit line.

[0022] According to an embodiment of the present application, the first period is during an access operation, and the second period is a recovery phase.

[0023] According to an embodiment of the present application, a pumping voltage source is electrically coupled to the bit line during the access operation.

[0024] According to an embodiment of the present application, the first period includes a first kick period and a second kick period, the first kick period and the second kick period are separated, and a pumping voltage source is coupled to the bit line during the first kick period, or coupled to the bit line during the first kick period and the second kick period.

[0025] According to an embodiment of the present application, the pumping voltage source provides a voltage less than the first voltage.

[0026] According to an embodiment of the present application, the word line is selected to turn on the access transistor during the first period and the second period according to a refresh operation.

[0027] According to an embodiment of the present application, a pumping voltage source is electrically coupled to the bit line during a kick period, the kick period preceding the first period, and the first sustain voltage source is electrically coupled to the bit line throughout the second period.

[0028] According to an embodiment of the present application, the second period is at least 20% of the sum of the kick period, the first period and the second period.

[0029] According to an embodiment of the present application, the second period is at least 50% of the sum of the kick period, the first period and the second period.

[0030] According to an embodiment of the present application, the voltage equalization period is after the access transistor is turned off, and the clearing circuit is activated during the voltage equalization period to make the voltage on the bit line equal to the predetermined reference voltage after the voltage equalization period.

[0031] According to an embodiment of the present application, the clearing circuit is activated by a clearing pulse, and the width of the clearing pulse is not greater than the width of the voltage equalization period.

[0032] According to an embodiment of the present application, the clearing circuit is activated by a clearing pulse, and the rising edge of the clearing pulse is substantially aligned with the rising edge of the voltage equalization period.

[0033] According to an embodiment of the present application, the clearing circuit comprises a switching circuit, and the switching circuit is coupled to the sensing amplifier and a predetermined voltage.

[0034] According to an embodiment of the present application, the clearing circuit comprises a switching circuit, and the switching circuit is coupled to the voltage equalization circuit and a predetermined voltage.

[0035] A dynamic random access memory with a cleaning circuit is disclosed. The dynamic random access memory includes a dynamic random access memory cell, a sense amplifier, a voltage equalization circuit, and a cleaning circuit. The dynamic random access memory cell includes an access transistor and a storage capacitor. The sense amplifier is coupled to a bit line and a complementary bit line, wherein the bit line is coupled to the storage capacitor through the access transistor. The voltage equalization circuit is coupled to the bit line and the complementary bit line, wherein the voltage equalization circuit connects the bit line and the complementary bit line to a predetermined reference voltage during a voltage equalization period. The cleaning circuit is coupled to the bit line and the complementary bit line during the voltage equalization period, wherein the cleaning circuit reduces a difference between a voltage on the bit line and a target reference voltage during the voltage equalization period.

[0036] According to an embodiment of the present invention, the voltage on the bit line is equal to the predetermined reference voltage after the voltage equalization period.

[0037] According to an embodiment of the present invention, the cleaning circuit is electrically coupled to the bit line and the complementary bit line through the sense amplifier or the voltage equalization circuit during the voltage equalization period.

[0038] According to an embodiment of the present invention, the cleaning circuit includes a switching circuit, and the switching circuit is coupled to the sense amplifier and a predetermined voltage.

[0039] According to an embodiment of the present invention, the cleaning circuit includes a switching circuit, and the switching circuit is coupled to the voltage equalization circuit and a predetermined voltage.

[0040] According to an embodiment of the present invention, the cleaning circuit is activated by a cleaning pulse during the voltage equalization period, and a rising edge of the cleaning pulse is substantially aligned with a rising edge of the voltage equalization period.

[0041] According to an embodiment of the present invention, the dynamic random access memory further includes a comparator circuit. The comparator circuit receives the voltage on the bit line, the voltage on the complementary bit line, and the predetermined reference voltage during the voltage equalization period or at the beginning of the voltage equalization period, and sends a control signal to the cleaning circuit when a half of a sum of the voltage on the bit line and the voltage on the complementary bit line is not equal to the predetermined reference voltage. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1A is a schematic diagram illustrating a most commonly used design of the dynamic random access memory cell.

[0043] Figure 1Bis a schematic diagram illustrating the waveforms of the relevant voltages of the dynamic random access memory cell during an access (read or write) operation.

[0044] Figure 1C is a schematic diagram illustrating a prior art dynamic random access memory cell with a sense amplifier and a voltage equalization circuit.

[0045] Figures 1D-1G is a schematic diagram showing four different phases (including a precharge phase, an access phase, a sense phase, and a restore phase) of an access (read) operation of the dynamic random access memory cell with respect to the sense amplifier.

[0046] Figure 1H is a schematic diagram illustrating the waveforms of the relevant voltages of the dynamic random access memory cell during an access (read or write) operation. Figures 1D-1G

[0047] Figure 2 is a schematic diagram illustrating the waveforms of the relevant voltages of the dynamic random access memory cell during an access (read or write) operation.

[0048] Figure 3A is a schematic diagram illustrating the sense amplifier selectively coupled to a first sustain voltage source.

[0049] Figure 3B is a schematic diagram illustrating the sense amplifier selectively coupled to the second sustain voltage source

[0050] Figure 4 is a schematic diagram illustrating the waveforms of the relevant voltages of the dynamic random access memory cell during an access (read or write) operation.

[0051] Figure 5 is a schematic diagram illustrating the waveforms of the relevant voltages of the dynamic random access memory cell during an access (read or write) operation.

[0052] Figure 6 is a schematic diagram illustrating the waveforms of the relevant voltages of the dynamic random access memory cell during an access (read or write) operation.

[0053] Figure 7 is a schematic diagram illustrating the waveforms of the relevant voltages of the dynamic random access memory cell during an access (read or write) operation.

[0054] Figure 8A is a schematic diagram illustrating the waveforms of the relevant voltages of the dynamic random access memory cell during an access (read or write) operation. ​

[0055] Figure 8B is a graph of waveforms of voltages associated with a dynamic random access memory cell during operation according to another embodiment of the invention.

[0056] Figure 8C is a graph of waveforms of voltages associated with a dynamic random access memory cell during operation according to another embodiment of the invention.

[0057] Figure 8D is a graph of waveforms of voltages associated with a dynamic random access memory cell during operation according to a sixth embodiment of the invention.

[0058] Figure 9 is a graph illustrating the relationship between the voltage on the bit line during operation of the dynamic random access memory cell and the kick.

[0059] Figure 10A is a graph of waveforms of voltages associated with a dynamic random access memory cell during operation according to a seventh embodiment of the invention.

[0060] Figure 10B is a graph of waveforms of voltages associated with a dynamic random access memory cell during operation according to another embodiment of the invention.

[0061] Figure 11A is a graph of waveforms of voltages associated with a dynamic random access memory cell during refresh operation according to another embodiment of the invention.

[0062] Figure 11B is a graph of waveforms of voltages associated with a dynamic random access memory cell during refresh operation and performing early recovery kick at timing 3 according to another embodiment of the invention.

[0063] Figure 11C is a graph of waveforms of voltages associated with a dynamic random access memory cell during refresh operation and performing early recovery kick at timing 2 according to another embodiment of the invention.

[0064] Figure 11D is a graph of waveforms of voltages associated with a dynamic random access memory cell during refresh operation and performing early recovery kick at timing 1 according to another embodiment of the invention.

[0065] Figure 12A is a graph illustrating the waveforms of voltages associated when the voltage on the bit line is pumped (or kicked) during the recovery phase.

[0066] Figure 12Bis a graph illustrating the temporary bit line equalization voltage disruption of the developed voltage that accompanies the next activation command after the voltage on the bit line is pumped (or kicked) during the recovery phase.

[0067] Figure 13 is a graph illustrating the relevant voltages for the activation of the word line after the voltage on the bit line is pumped (or kicked) during the recovery phase and the activation of the clean-up circuit during the voltage equalization.

[0068] Figure 14A is a graph illustrating a prior art dynamic random access memory cell having a sense amplifier and a voltage equalization circuit.

[0069] Figure 14B is a graph illustrating a dynamic random access memory cell having a clean-up circuit coupled to a sense circuit as disclosed in the present invention.

[0070] Figure 14C is a graph illustrating a dynamic random access memory cell having a clean-up circuit coupled to a voltage equalization circuit as disclosed in the present invention.

[0071] Figure 15A is a graph illustrating a dynamic random access memory cell having a clean-up circuit comprising a switch circuit coupled to a node of a sense amplifier and a ground terminal as disclosed in the present invention.

[0072] Figure 15B is a graph illustrating a dynamic random access memory cell having a clean-up circuit comprising a switch circuit coupled to a node of a voltage equalization circuit and a ground terminal as disclosed in the present invention.

[0073] Figure 15C is a graph illustrating a dynamic random access memory cell having a comparator circuit coupled to the clean-up circuit as disclosed in the present invention.

[0074] wherein the reference numerals are explained as follows:

[0075] 1, 0 signal

[0076] 11 access transistor

[0077] 12 storage capacitor

[0078] 13, 14, 23, 24 switch

[0079] 20, 41, 42 sense amplifier

[0080] 21 voltage equalization circuit

[0081] 202 pre-charge pulse signal

[0082] 141 clean-up circuit

[0083] 142 switch circuit

[0084] 143 comparator circuit

[0085] ACM start instruction

[0086] BL, BLB, BL1, BL9, BL1B, BL9B bit line

[0087] CP clear pulse

[0088] CSL column select line

[0089] EN1, EN2, EN3, CS control signal

[0090] EQBL voltage equalization period

[0091] GND ground

[0092] K1, K2, K3, K4 kick period

[0093] LSLP, LSLN, SAP, SAN, NBL node

[0094] N3, N4, N7, N8 N-type metal oxide semiconductor transistor

[0095] OUTPUTB, OUTPUT output terminal

[0096] P1, P2, P5, P6 P-type metal oxide semiconductor transistor

[0097] Pa, Pb time period

[0098] RC read instruction

[0099] Sec storage area

[0100] SN1, SN9 storage node

[0101] T0, T1, T2, T3 time

[0102] VREF reference voltage

[0103] VREF+, VREF-, VCCSA, VSS, Vb1, voltage

[0104] VPP, M1, M2, K, ΔN, ΔV,

[0105] V1, VCCSAh, V2

[0106] VT threshold voltage

[0107] VCC supply voltage

[0108] Vp1 common voltage

[0109] VHSA third voltage

[0110] VBL bit line equalization voltage

[0111] WL, WL00 word line DETAILED DESCRIPTION

[0112] A Dynamic Random Access Memory (DRAM) with a sustain storage architecture is disclosed, wherein a sustain voltage source is electrically connected to a storage capacitor included in a DRAM cell before an access transistor included in the DRAM cell is turned off, and the voltage provided by the sustain voltage source is either higher than a signal "ONE" (i.e., a high level signal) or lower than a signal "ZERO" (i.e., a low level signal). The operation of the DRAM (e.g., an auto-precharge phase, a restore phase, a refresh phase, and a precharge phase) will turn on the access transistor of the DRAM cell. Therefore, during the period when the access transistor is turned on, by electrically connecting the sustain voltage source to the storage capacitor, even though there is a leakage current through the access transistor after the access transistor is turned off, the charge stored in the storage capacitor can still be maintained for a longer period of time than the existing DRAM architecture.

[0113] First embodiment of the present application:

[0114] Figure 2 is a schematic diagram illustrating the waveforms of the relevant voltages of the DRAM cell disclosed in the first embodiment during an access (read or write) operation, wherein the DRAM cell can refer to Figure 1A . As Figure 2As shown, the DRAM is initially in a standby mode or an inactive mode, and the word line WL is biased at a standby voltage (-0.3V) to completely turn off the access transistor 11. In the first embodiment, the voltage VCCSA is 1.2V, the voltage VSS is 0V, the signal "ONE" (i.e., a high signal) is 1.2V, and the signal "ZERO" is 0V (i.e., a low signal and equal to the level of the ground GND). In addition, in the first embodiment, the voltages on the bit line BL and the bit line BLB are equalized at 0.6V, i.e., the voltages on the bit line BL and the bit line BLB are between the signal "ONE" (1.2V) and the signal "ZERO" (0V).

[0115] At a time TO, the voltage on the word line WL is raised from the standby voltage (-0.3V) to a voltage VPP (2.7V) to turn on the access transistor 11, where the voltage VPP (2.7V) is much greater than the sum of the voltage VCCSA (1.2V) and the threshold voltage VT (0.8V) of the access transistor 11, i.e., the voltage VPP (2.7V) provides sufficient drive to the turned on access transistor 11 to transfer the signal "ONE" or the signal "ZERO" to the bit line BL and the bit line BLB. The sense amplifier 20 is then enabled to amplify the signals on the bit line BL and the bit line BLB until the signals on the bit line BL and the bit line BLB are developed to a certain magnitude, where the sense amplifier 20 is a cross-coupled sense amplifier. After a time Tl, the read operation (amplifying the signals transferred by the DRAM cell on the bit line BL and the bit line BLB by the sense amplifier 20) or the write operation (writing the signal "ONE" or the signal "ZERO" to the sense amplifier 20 to store the correct signal to the storage capacitor 12 of the DRAM cell) can be performed. During the access operation, a voltage source is electrically connected or coupled to the sense amplifier 20 to be coupled to the storage capacitor 12 by turning on a switch 14 (as shown). Figure 3A The voltage source can provide the voltage VCCSA (i.e., the signal "ONE" or the supply voltage), where Figure 3A is a schematic diagram showing that the sense amplifier 20 is selectively coupled to a first sustain voltage source. As Figure 3AAs shown, during the access operation, the sensor amplifier 20 is prevented from receiving a first voltage VCCSA+M1 by turning off a switch 13. However, in addition to the read operation and the write operation, other operations of the dynamic random access memory can also be performed after time T1, that is, between time T1 and time T2, the dynamic random access memory cell can perform the access operation, wherein the time interval between time T1 and time T2 is a first time interval.

[0116] During the recovery phase after time T2, voltage VPP is continuously loaded from word line WL into the dielectric material of the gate of access transistor 11 to shorten the recovery phase time. During the recovery phase, a first sustaining voltage source is coupled to the storage capacitor 12 of the dynamic random access memory cell, wherein the first sustaining voltage source can provide a first voltage VCCSA+M1 higher than voltage VCCSA (1.2V) or signal "ONE" (1.2V), and the first sustaining voltage source can be activated by switching on switch 13 (e.g., ...). Figure 3A (As shown) The sensing amplifier 20 is electrically connected or coupled to the storage capacitor 12, and the voltage M1 is a positive voltage so that the first voltage VCCSA+M1 is higher than the voltage VCCSA (1.2V). Additionally, as... Figure 3A As shown, during the recovery phase, the sensor amplifier 20 is prevented from receiving voltage VCCSA by turning off switch 14. Alternatively, in one embodiment of the invention, voltage M1 may be between 1 / 3 and 2 / 3 of voltage VCCSA (1.2V), for example, 0.6V. In another embodiment of the invention, voltage M1 may also be any value between 0.1V and 0.8V, such as 0.1V, 0.2V, 0.3V, or 0.4V. For example, when storage capacitor 12 initially stores the signal "ONE" (1.2V), during the recovery phase, the first voltage VCCSA + M1 (1.2V + 0.6V) is transmitted from the first sustaining voltage source through sensor amplifier 20 and bit line BL and stored in storage capacitor 12. That is, as... Figure 2As shown, before the access transistor 11 is turned off at a time T3 (where the voltage on the word line WL is pulled down from the voltage VPP to a standby voltage of the word line WL in the standby mode when the access transistor 11 is turned off), the storage capacitor 12 is provided with a first voltage VCCSA+Ml by the first sustain voltage source (i.e. before the access transistor 11 is turned off at the time T3, the storage capacitor 12 stores the first voltage VCCSA+Ml), where the first voltage VCCSA+Ml is higher than the signal "ONE" (i.e. the high level signal), the time interval between the time T2 and the time T3 (i.e. the recovery phase) is a second time interval, and the second time interval is after the first time interval. Therefore, even though there is a leakage current through the access transistor 11 after the access transistor 11 is turned off, the charge stored in the storage capacitor 12 can still be maintained for a longer period of time than the existing dynamic random access memory architecture. In an embodiment of the present application, the first sustain voltage source can disconnect the sense amplifier 20 after the access transistor 11 is turned off or after the recovery phase. In addition, the bit line BL and the bit line BLB can be coupled to a bit line voltage source to provide a voltage Vbl after the access transistor 11 is turned off or after the recovery phase, so that the voltages on the bit line BL and the bit line BLB can be reset to the voltage Vbl (as shown) after the access transistor 11 is turned off or after the recovery phase. Figure 2

[0117] In another embodiment of the present application, a second sustain voltage source is coupled to the storage capacitor 12 of the dynamic random access memory cell during the recovery phase. The second sustain voltage source can provide a second voltage VSS-M2 lower than the voltage VSS (0V) or the signal "ZERO" (0V) to the sense amplifier 20 by turning on a switch 23 (as shown). Figure 3B Figure 3B is a schematic diagram showing that the sense amplifier 20 is selectively coupled to the second sustain voltage source, the voltage M2 is a positive voltage, and another voltage source has been previously provided to the sense amplifier 20 by turning on a switch 24 (as shown) during the access operation. Figure 3B ​​The second voltage source can provide a voltage VSS (i.e., a signal "ZERO" or another supply voltage). In one embodiment of the present application, the voltage M2 can be between 0.4V and 0.8V, for example, 0.6V. In addition, in another embodiment of the present application, the voltage M2 can also be any value between 0.1V and 0.8V, such as 0.1V, 0.2V, 0.3V, or 0.4V, etc. In addition, when the second sustain voltage source is coupled to the sense amplifier 20 during the recovery phase, the switch 24 is closed so that the sense amplifier 20 cannot receive the voltage VSS. When the storage capacitor 12 is initially storing the signal "ZERO", during the recovery phase, the second voltage VSS-M2 (-0.6V) is transferred from the second sustain voltage source through the sense amplifier 20 and the bit line BL and stored to the storage capacitor 12. That is, as shown in FIG. 6, before the access transistor 11 is closed at time T3 (where the voltage on the word line WL will be pulled down from the voltage VPP to the standby voltage of the word line WL in the standby mode when the access transistor 11 is closed), the storage capacitor 12 is provided with the second voltage VSS-M2 by the second sustain voltage source (i.e., before the access transistor 11 is closed at time T3, the storage capacitor 12 is storing the second voltage VSS-M2), where the second voltage VSS-M2 is lower than the signal "ZERO" (i.e., the low level signal). In one embodiment of the present application, after the access transistor 11 is closed or after the recovery phase, the second sustain voltage source can be disconnected from the sense amplifier 20. Figure 2 In addition, in another embodiment of the present application, during the recovery phase, both the first sustain voltage source and the second sustain voltage source are coupled to the storage capacitor 12 of the dynamic random access memory cell. Thus, when the storage capacitor 12 is initially storing the signal "ONE", the first voltage VCCSA+Ml (1.2V + 0.6V) is transferred from the first sustain voltage source through the sense amplifier 20 and stored to the storage capacitor 12 before the voltage on the word line WL is pulled down from the voltage VPP to the standby voltage of the word line WL in the standby mode; or when the storage capacitor 12 is initially storing the signal "ZERO", the second voltage VSS-M2 (-0.6V) is transferred from the second sustain voltage source through the sense amplifier 20 and stored to the storage capacitor 12.

[0118] In addition, in another embodiment of the present application, during the recovery phase, both the first sustain voltage source and the second sustain voltage source are coupled to the storage capacitor 12 of the dynamic random access memory cell. Thus, when the storage capacitor 12 is initially storing the signal "ONE", the first voltage VCCSA+Ml (1.2V + 0.6V) is transferred from the first sustain voltage source through the sense amplifier 20 and stored to the storage capacitor 12 before the voltage on the word line WL is pulled down from the voltage VPP to the standby voltage of the word line WL in the standby mode; or when the storage capacitor 12 is initially storing the signal "ZERO", the second voltage VSS-M2 (-0.6V) is transferred from the second sustain voltage source through the sense amplifier 20 and stored to the storage capacitor 12.

[0119] Second embodiment of the present application:

[0120] To reduce the leakage current so that the charge stored in the storage capacitor 12 will not be leaked out through the access transistor 11, the access transistor 11 is usually designed to have a very high threshold voltage. When the voltage VCCSA is reduced to 0.6V, in the design of the dynamic random access memory, the 7-nanometer or 5-nanometer process three-gate transistors or fin field effect transistors will be applied to the peripheral circuit of the dynamic random access memory cell, in which the threshold voltage of the transistors applied to the peripheral circuit will be correspondingly reduced, for example, the threshold voltage of the transistors applied to the peripheral circuit is reduced to 0.3V. However, in the second embodiment of the present application, the threshold voltage of the access transistor 11 can be intentionally increased to 0.5V-0.6V according to the above-mentioned concept of reducing the leakage current. Therefore, the leakage current from the storage capacitor 12 can be greatly reduced by at least 3-4 orders of magnitude (if the S factor for measuring the leakage current is 68mV / decade and the threshold voltage of the access transistor 11 is increased to 0.6V, the leakage current from the storage capacitor 12 will be 4 orders of magnitude lower than that of the three-gate transistors applied to the peripheral circuit; if the threshold voltage of the access transistor 11 is increased to 0.5V, the leakage current from the storage capacitor 12 will be reduced by 2-3 orders of magnitude than that of the three-gate transistors applied to the peripheral circuit). Therefore, in the second embodiment of the present application, the threshold voltage of the access transistor 11 will be increased to close to the voltage VCCSA or at least more than 80% of 0.6V. In addition, in the second embodiment of the present application, the thickness of the dielectric material of the gate of the access transistor 11 (for example, the fin field effect transistor or the three-gate transistor) is still the same as that of the gate of the transistors applied to the peripheral circuit, so the advantage of high performance of the access transistor 11 using the three-gate structure can still be maintained.

[0121] Figure 4is a schematic diagram illustrating the waveforms of the voltages associated with the dynamic random access memory cell during an access (read or write) operation, wherein in the second embodiment, the signal "ONE" is 0.6V and the signal "ZERO" is 0V (i.e. the level of the ground). In the recovery phase, a first sustain voltage source is coupled to the storage capacitor 12 of the dynamic random access memory cell. The first sustain voltage source can provide a first voltage VCCSA+K, which is higher than the voltage VCCSA (0.6V) or the signal "ONE" (0.6V), wherein the first sustain voltage source can be coupled to the storage capacitor 12 through an electrical connection or coupling of the sense amplifier 20, and the voltage K is a positive voltage. In an embodiment of the present application, the voltage K can be between 1 / 3 of the voltage VCCSA (0.6V) and 2 / 3 of the voltage VCCSA (0.6V), for example 0.3V or 0.4V. Thus, when the storage capacitor 12 initially stores the signal "ONE" (0.6V), in the recovery phase, the first voltage VCCSA+K (0.6V+0.4V) is provided to the storage capacitor 12. That is, as shown in Figure 4 the storage capacitor 12 is provided with the first voltage VCCSA+K by the first sustain voltage source, which is higher than the signal "ONE" (0.6V), before the access transistor 11 is turned off at a time T3 (wherein when the access transistor 11 is turned off, the voltage on the word line WL will be pulled down from the voltage VPP to the standby voltage of the word line WL in the standby mode). Thus, when the storage capacitor 12 initially stores the signal "ONE" (0.6V), the first voltage VCCSA+K (1V) can be stored to the storage capacitor 12 after the voltage on the word line WL is pulled up to the voltage VPP and before it is pulled down to the standby voltage. In addition, in an embodiment of the present application, after the recovery phase, the bit line BL and the bit line BLB can be coupled to the bit line voltage source to provide the voltage Vbl, so that the voltages on the bit line BL and the bit line BLB will be reset to the voltage Vbl (as shown in Figure 4 ).

[0122] In addition, as mentioned earlier, when the storage capacitor 12 initially stores the signal "ZERO", before the voltage on the word line WL is pulled down from the voltage VPP to the standby voltage of the word line WL in the standby mode, the second voltage provided by the second sustain voltage source, which is lower than the storage signal "ZERO", for example -0.4V, can be stored to the storage capacitor 12.

[0123] Third embodiment of the present application:

[0124] Figure 5is a schematic diagram of the circuit and functional block diagram for the pre-charge operation disclosed in the third embodiment of the present invention, wherein in the third embodiment, the voltage VCCSA is 0.6V and the voltage VSS is 0V (i.e. the level of the ground). In the pre-charge operation, all the dynamic random access memory cells (hereinafter referred to as first dynamic random access memory cells) in the storage area 5 (Sec 5) connected to the selected word line will be pre-charged, and all the dynamic random access memory cells (hereinafter referred to as second dynamic random access memory cells) in other storage areas (e.g. Sec 4, Sec 6, etc.) connected to the unselected word line will be in idle state.

[0125] The sense amplifier 41, 42 (coupled to the first dynamic random access memory cells) will be connected to a third sustain voltage source according to a pre-charge pulse signal 30, wherein the third sustain voltage source can provide a third voltage VHSA (0.6V+K), so that a stronger drain-source electric field can accelerate the recovery of the signals of the first dynamic random access memory cells in the recovery phase. The third voltage VHSA is about several hundred millivolts (mV) higher than the voltage VCCSA (0.6V), for example, 0.3V or 0.4V. In addition, before the selected word line is turned off (i.e. before the access transistor in the first dynamic random access memory cell is turned off), the third voltage VHSA (0.6V+0.4V) is higher than the signal "ONE" to be subsequently stored in the storage capacitor in the first dynamic random access memory cell. On the other hand, the second dynamic random access memory cells still receive the voltage VCCSA.

[0126] In addition, please refer to Figure 6 , Figure 6 is a schematic diagram of the sense amplifier coupled to the first dynamic random access memory cells in the pre-charge operation, wherein the symbols used to assist in the explanation of Figure 6 are explained as follows:

[0127] LSLP: node for receiving high voltage in the sense amplifier connected to the first dynamic random access memory cells;

[0128] LSLN: node for receiving low voltage in the sense amplifier connected to the first dynamic random access memory cells;

[0129] Vpl: common voltage on the circuit board;

[0130] SN: storage node;

[0131] WL: word line;

[0132] BL: bit line;

[0133] Vsgl,2: source-gate voltage of P-type metal oxide semiconductor transistors Pl, P2 in the sense amplifier of the first dynamic random access memory cell;

[0134] Vgs3,4: gate-source voltage of N-type metal oxide semiconductor transistors N3, N4 in the sense amplifier of the first dynamic random access memory cell;

[0135] Vsg5,6: source-gate voltage of P-type metal oxide semiconductor transistors P5, P6 in the sense amplifier of the first dynamic random access memory cell;

[0136] Vgs7,8: gate-source voltage of N-type metal oxide semiconductor transistors N7, N8 in the sense amplifier of the first dynamic random access memory cell.

[0137] Referring again to Figure 6 , the word line WL00 is coupled to a plurality of storage nodes, such as storage nodes SNl, SN9. When a signal "ONE" (0.6V) is stored in the storage node SNl coupled to the word line WL00, and after the pre-charge command is enabled and the word line WL00 is selected (i.e., the word line WL00 is enabled), the node LSLP receives the third voltage VHSA (1.0V) and the voltage on the node LSLN remains at 0V, i.e., the voltage on the node LSLP is boosted from 0.6V to 1.0V. As such, the P-type metal oxide semiconductor transistor Pl is turned off and the source-gate voltage Vsgl is 0V. Similarly, the P-type metal oxide semiconductor transistor P2 is turned on and the source-gate voltage Vsg2 is boosted from 0.6V to 1.0V, and the voltage of 1.0V is fully charged to the storage node SNl through the bit line BLl. At this time, the N-type metal oxide semiconductor transistor N3 is turned on and the gate-source voltage Vgs3 is also boosted from 0.6V to 1.0V. In addition, the N-type metal oxide semiconductor transistor N4 is turned off and the gate-source voltage Vgs4 is 0V.

[0138] When the signal "ZERO" (0V) is stored in the storage node SN9 connected to the word line WL00, and after the pre-charge command is enabled and after the word line WL00 is selected, the node LSLP receives the third voltage VHSA (1.0V) and the voltage on the node LSLN remains 0V. As such, the P-type metal oxide semiconductor transistor P5 is turned on and the source-gate voltage Vsg5 is boosted from 0.6V to 1.0V. Similarly, the P-type metal oxide semiconductor transistor P6 is turned off and the source-gate voltage Vsg6 is 0V. At this time, the N-type metal oxide semiconductor transistor N7 is turned off and the gate-source voltage Vgs7 is 0V. In addition, the N-type metal oxide semiconductor transistor N8 is turned on and the gate-source voltage Vgs8 is boosted from 0.6V to 1.0V, and the voltage of the storage node SN9 is strongly restored to 0V through the bit line BL9. Of course, as previously mentioned, during the pre-charge operation, when the signal "ONE" is stored in the storage node SN9 connected to the word line WL00, the node LSLP receives the second voltage VLSA (0.6V) and the voltage on the node LSLN remains 0V. As such, the P-type metal oxide semiconductor transistor P5 is turned on and the source-gate voltage Vsg5 is boosted from 0.6V to 0.6V. Similarly, the P-type metal oxide semiconductor transistor P6 is turned off and the source-gate voltage Vsg6 is 0V. At this time, the N-type metal oxide semiconductor transistor N7 is turned off and the gate-source voltage Vgs7 is 0V. In addition, the N-type metal oxide semiconductor transistor N8 is turned on and the gate-source voltage Vgs8 is boosted from 0.6V to 0.6V, and the voltage of the storage node SN9 is strongly restored to 0V through the bit line BL9. Figure 6 When the storage capacitor shown is initially storing the signal "ZERO", the node LSLN can receive a voltage VLSN (0V-K) provided by other sustain voltage sources, where the voltage VLSN is lower than the signal "ZERO", and for example the voltage VLSN can be -0.4V. Then, during the pre-charge operation, the voltage of the storage node SN9 is strongly restored to -0.4V through the bit line BL9.

[0139] In another embodiment of the present application, the concept of coupling the first sustain voltage source providing the first voltage (higher than the signal "ONE") to the sense amplifier (or the dynamic random access memory cell) can also be applied to the refresh phase or other operations (such as access operations (READ / WRITE) with an auto-precharge phase) as long as the first sustain voltage source is coupled to the sense amplifier (or the dynamic random access memory cell) before the word line coupled to the dynamic random access memory cell is turned off. Similarly, the concept of coupling the second sustain voltage source providing the second voltage (lower than the signal "ZERO") to the sense amplifier (or the dynamic random access memory cell) can also be applied to the refresh phase or other operations as long as the second sustain voltage source is coupled to the sense amplifier (or the dynamic random access memory cell) before the word line coupled to the dynamic random access memory cell is turned off.

[0140] Fourth embodiment of the present application:

[0141] Figure 7is a schematic diagram of the waveforms of the relevant voltages during operation of a dynamic random access memory cell according to a fourth embodiment of the present application. Initially, the word line WL is biased to fully turn off the access transistor of the dynamic random access memory cell. In the fourth embodiment, the voltage VCCSA is 1.1 V, the voltage VSS is 0 V, the signal "ONE" is 1.1 V, and the signal "ZERO" is 0 V (i.e., the level of ground GND). The voltages on the bit line BL and the bit line BLB are equalized between the signal "ONE" (1.1 V) and the signal "ZERO" (0 V). After time TO, the voltage on the word line WL is raised to turn on the access transistor of the dynamic random access memory cell. Between times Tl and T2, an activation command ACM is executed, and during the execution of the activation command ACM, the sensing amplifier 20 is connected to the first sustain voltage source (which provides the voltage VCCSA+Ml) by turning on the switch 13 and turning off the switch 14 as shown in FIG. 4. Thus, during the execution of the activation command ACM, the voltage on the bit line BL is at least pumped (or kicked up) to the voltage VCCSA+Ml. After the execution of the activation command ACM is completed, the sensing amplifier 20 is connected to the voltage VCCSA by turning on the switch 14 and turning off the switch 13 as shown in FIG. 3, and then the voltage on the bit line BL returns to the voltage VCCSA, where the pumped (or kicked up) voltage on the bit line BL accelerates the sensing of the signal. Figure 3A Figure 3A

[0142] Similarly, during the recovery (or the pre-charge) phase after time T2, the first sustain voltage source (or a voltage source that provides a different sustain voltage higher than the voltage VCCSA) is coupled to the storage capacitor of the dynamic random access memory cell. That is, during the recovery (or the pre-charge) phase, the sensing amplifier 20 is connected to the first sustain voltage source (which provides the voltage VCCSA+Ml) by turning on the switch 13 and turning off the switch 14 as shown in FIG. 4, and the voltage source that provides the voltage VCCSA is disconnected from the sensing amplifier 20. At this time, the voltage on the bit line BL is at least pumped (or kicked up) to the voltage VCCSA+Ml. Thus, before the voltage on the word line WL is pulled down to fully turn off the access transistor of the dynamic random access memory cell, the voltage VCCSA+Ml higher than the signal "ONE" (the voltage VCCSA) is provided to the storage capacitor of the dynamic random access memory cell, so the charge stored in the storage capacitor of the dynamic random access memory cell can be maintained for a longer period of time than the existing dynamic random access memory architecture even if there is a leakage current through the access transistor after the access transistor of the dynamic random access memory cell is turned off. Figure 3A

[0143] Fifth embodiment of the present application:​​​

[0144] Figure 8A is a schematic diagram of the waveforms of the relevant voltages during operation of the dynamic random access memory cell disclosed in the fifth embodiment of the present application. Similar to the fourth embodiment shown in Fig. 4, between time Tl and time T2, the start-up command ACM is executed, and during the execution of the start-up command ACM, the first sustain voltage source (providing voltage VCCSA+Ml) is connected to the sense amplifier 20. Thus, during the execution of the start-up command ACM, the voltage on the bit line BL is at least pumped (or kicked up) to the voltage VCCSA+Ml. After the execution of the start-up command ACM, the voltage VCCSA is connected to the sense amplifier 20, and then the voltage on the bit line BL will return to the voltage VCCSA. Figure 7

[0145] After the start-up command ACM, one (or more) read command(s) RC can be executed before time T2, and during the execution of the read command(s) RC, the first sustain voltage source (providing voltage VCCSA+Ml) is again connected to the sense amplifier 20. Thus, during the execution of the read command(s) RC, the voltage on the bit line BL is at least pumped (or kicked up) to the voltage VCCSA+Ml. After the execution of the read command(s) RC, the voltage VCCSA is connected to the sense amplifier 20 by turning on the switch 14 and turning off the switch 13 as shown in Fig. 5, and then the voltage on the bit line BL will return to the voltage VCCSA. This pumping (or kicking up) of the bit line BL during the execution of the read command(s) RC will improve the signal development time. For example, in the fifth embodiment, the voltage VCCSA is 1.1 V and Ml is 0.2 V, then the signal development time with the pumping (or kicking up) during the execution of the read command(s) RC will be about 20% to 30% faster than the signal development time without the pumping (or kicking up). Figure 3A

[0146] Similarly, during the recovery phase after time T2, the voltage source providing voltage VCCSA is disconnected from the sense amplifier 20 and the first sustain voltage source (providing voltage VCCSA+Ml) is connected to the sense amplifier 20, at this time, the voltage on the bit line BL is at least pumped (or kicked up) to the voltage VCCSA+Ml. In this way, the voltage VCCSA+Ml which is higher than the signal "ONE" (voltage VCCSA) is provided to the storage capacitor of the dynamic random access memory cell. However, in another embodiment of the present application, during the recovery phase after time T2, the voltage source providing voltage VCCSA is still connected to the sense amplifier 20 instead of the first sustain voltage source being connected to the sense amplifier 20 as shown in Fig. 6. Figure 8B

[0147] ​​​Additionally, in another embodiment of the present invention, such as Figure 8C As shown, during the execution of the start instruction ACM, the voltage on bit line BL is not pumped (or kicked) to voltage VCCSA+M1, but during the execution of the read instruction RC, the voltage on bit line BL is pumped (or kicked) to voltage VCCSA+M1. During the recovery phase after time T2, the first sustaining voltage source (providing voltage VCCSA+M1) is connected to the sensing amplifier 20, at which time the voltage on bit line BL is at least pumped (or kicked) to voltage VCCSA+M1.

[0148] The sixth embodiment of the present invention:

[0149] Figure 8D This is a schematic diagram of the waveforms of the relevant voltages of the dynamic random access memory cell during operation, as disclosed in the sixth embodiment of the present invention. Similar to... Figure 8A In the fifth embodiment shown, between time T1 and time T2, a start instruction ACM and at least one read instruction RC following the start instruction ACM are executed, and during the execution of the start instruction ACM and the read instruction RC, by enabling... Figure 3A The switch 13 shown connects the first sustaining voltage source (providing voltage VCCSA+M1) to the sensing amplifier 20. Furthermore, during the execution of the start command ACM and read command RC, by turning on... Figure 3B The switch 23 shown connects the second sustaining voltage source (VSS-M2) to the sensing amplifier 20. Therefore, during the execution of the start instruction ACM and read instruction RC, the voltage on bit line BL is pumped (or kicked) to voltage VCCSA+M1 and the voltage on bit line BLB is pumped (or kicked) to voltage VSS-M2. After the execution of the start instruction ACM and read instruction RC ends, the switch 23 is activated by turning on the sensor amplifier 20. Figure 3A The switch 14 shown and the switch 13 closed are used to connect the voltage VCCSA to the sensing amplifier 20 and to open the circuit as shown. Figure 3B Switch 24 and switch 23 are shown to connect voltage VSS to the sensing amplifier 20, and then the voltage on bit line BL will return to voltage VCCSA and the voltage on bit line BLB will return to voltage VSS.

[0150] Similarly, in the recovery phase after time T2, by respectively closing Figure 3A The switch 14 shown and as Figure 3B The switch 24 shown disconnects the voltage source providing voltage VCCSA and the voltage source providing voltage VSS from the sensing amplifier 20, and also turns it on. Figure 3A The switch 13 shown allows the first sustaining voltage source (providing voltage VCCSA+M1) to connect to the sensing amplifier 20 and to be turned on.Figure 3B The switch 23 is shown to connect the second sustain voltage source (providing voltage VSS-M2) to the sense amplifier 20. As such, the voltage on the bit line BL is pumped (or kicked) at least to the voltage VCCSA+M1 and the voltage on the bit line BLB is pumped (or kicked) at least to the voltage VSS-M2.

[0151] Figure 9 is a schematic diagram illustrating the relationship of the voltage on the bit line BL during the operation of the dynamic random access memory cell and the kick period. The length of the kick period K4 corresponding to the voltage on the bit line BL during the recovery (or the pre-charge) phase is longer than the length of the kick period K1 corresponding to the voltage on the bit line BL during the activation command ACM, or the kick period K4 is longer than the length of the kick periods K2, K3 corresponding to the voltage on the bit line BL during the read command RC. In addition, the length of the kick period K1 corresponding to the voltage on the bit line BL during the activation command ACM is equal to the length of the kick periods K2, K3 corresponding to the voltage on the bit line BL during the read command RC. Of course, during the kick periods K1-K3, the voltage on the bit line BL can be pumped (or kicked) to the voltage VCCSA+M1 or other voltage level higher than the voltage VCCSA (e.g. voltage VCCSA+ΔN, where 0<ΔN<M1) by a bootstrap circuit, where a capacitor in the bootstrap circuit is coupled to the bit line BL, and the bootstrap circuit is also referred to as a pumping voltage source. Either the voltage source or the bootstrap circuit can be regarded as a charging source, so the voltage on the bit line BL can be pumped (or kicked) to the voltage VCCSA+M1 or the voltage VCCSA+ΔN by the charging source. Similarly, the voltage on the bit line BLB can also be pumped (or kicked) to the voltage VSS-M2 (or voltage VSS-ΔN, where 0<ΔN<M2).

[0152] Seventh embodiment of the present application:

[0153] In another embodiment of the present application, as shown in Figure 10A After time TO, the voltage on the word line WL is raised to turn on the access transistor of the dynamic random access memory cell. Then, during the access (read or write) of the dynamic random access memory cell, the activation command ACM is executed, and during the execution of the activation command ACM, the switch 23 is closed as shown in Figure 3AThe switch 14 and the on switch 13 are shown to connect a voltage source providing the voltage VCCSA+ΔN to the sense amplifier 20 to reduce the time interval tRCD, where the time interval tRCD is defined by the double data rate memory specification of the Joint Electron Device Engineering Council (JEDEC), and the voltage VCCSA+ΔN is slightly higher than the voltage VCCSA. Thus, between the time Tl and the time T2, that is, during the access operation, the voltage on the bit line BL is at least pumped (or kicked) to the voltage VCCSA+ΔN during the execution of the activate command ACM. This pumping (or kicking) of the voltage on the bit line BL can be referred to as an active kick, and the active kick will speed up the sensing of the signal. In addition, the voltage on the bit line BL can be pumped (or kicked) to the voltage VCCSA+ΔN by a bootstrap circuit, where a capacitor in the bootstrap circuit is coupled to the bit line BL. Either the voltage source or the bootstrap circuit can be considered as a charge source, so the voltage on the bit line BL can be pumped (or kicked) to the voltage VCCSA+ΔN by the charge source.

[0154] After the execution of the activate command ACM or the active kick, during the subsequent access (read or write), the voltage VCCSA is connected to the sense amplifier 20, and then the voltage on the bit line BL will return to the voltage VCCSA. Similarly, during the recovery phase after the time T2, the first sustain voltage source (or a voltage source providing a different sustain voltage higher than the voltage VCCSA) is again coupled to the storage capacitor of the DRAM cell. That is, during the recovery phase, the switches 14 and 13 are shown to disconnect the voltage source providing the voltage VCCSA from the sense amplifier 20, and to connect the first sustain voltage source providing the voltage VCCSA+Ml to the sense amplifier 20. At this time, the voltage on the bit line BL is at least pumped (or kicked) to the voltage VCCSA+Ml. This pumping (or kicking) of the voltage on the bit line BL can be referred to as a recovery kick. Thus, before the voltage on the word line WL is pulled down to completely turn off the access transistor of the DRAM cell, the voltage VCCSA+Ml higher than the signal "ONE" (the voltage VCCSA) is provided to the storage capacitor of the DRAM cell, so the charge stored in the storage capacitor of the DRAM cell can be maintained for a longer period of time than in the existing DRAM architecture even if there is a leakage current through the access transistor after the access transistor of the DRAM cell is turned off. Figure 3A

[0155] ​In one embodiment of the invention, the voltage VCCSA+ΔN applied to the initiation kick is lower than the voltage VCCSA+M1 applied to the recovery kick. Voltages VCCSA+ΔN and VCCSA+M1 can be generated by two different voltage sources, or the voltage VCCSA+ΔN applied to the initiation kick can also be generated by the first sustaining voltage source, but the period during which the first sustaining voltage source is connected to bit line BL is adjusted so that the voltage on bit line BL is pumped (or kicked) to voltage VCCSA+ΔN, instead of being pumped (or kicked) to voltage VCCSA+M1. Of course, in this invention, voltages VCCSA+M1, VCCSA+ΔN, and VCCSA can be generated or converted internally by the dynamic random access memory (DRAM), or provided or converted by other voltage sources external to the DRAM.

[0156] However, as Figure 10B As shown, during the recovery kick, due to the resistance-capacitance delay (RC delay) caused by imperfections in the power network and bit line BL within the dynamic random access memory array or other delays, the first sustaining voltage source may not be able to quickly raise the voltage on the bit line BL. That is, the recovery kick may not allow the voltage VCCSA+M1 to be fully stored in the storage capacitance of the dynamic random access memory cell through the bit line BL, and only the voltage VCCSA+M1-ΔV may be stored in the storage capacitance of the dynamic random access memory cell, where ΔV>0. Additionally, as... Figure 10B As shown, in the regular access command of the dynamic random access memory unit, the access (read or write) operation can be performed between the start kick and the recovery kick, so it is not suitable to perform the recovery kick earlier to overcome the problem of the resistor-capacitor delay (RC delay).

[0157] However, as Figure 11A As shown, for executing a refresh command within the dynamic random access memory (DRAM) cell, since no access (read or write) operation is included in the refresh command, it is suitable to execute the recovery kick earlier (hereinafter referred to as "early restore kick," for example, executing an early restore kick in timing 1, timing 2, or timing 3) to overcome the problem of the resistor-capacitor delay (RC delay). The early restore kick allows the voltage VCCSA+M1 to be fully or substantially stored through the bit line BL in the storage capacitance of the DRAM cell, rather than as... Figure 10BAs shown, only the voltage VCCSA+M1-ΔV is stored in the storage capacitor of the dynamic random access memory cell. Therefore, the charge stored in the storage capacitor can be maintained for a longer period of time.

[0158] Additionally, reliability issues arise when the voltage VCCSA+M1 is too high (e.g., when VCCSA is 1.1V, a voltage of 1.5V or 1.6V might be too high for VCCSA+M1). Therefore, optimized voltage and earlier kicking time are necessary. Different timing sequences for the early recovery kick can be generated through internal timing control during refresh. Figure 11B (Performing an early recovery kick in timing 3) This indicates that the time period Pa between the start kick and the early recovery kick is less than 50% or 60% of the time period Pb between time T1' and time T3, where time T1' is the time when the voltage difference between bit line BL and bit line BLB is sufficient to be sensed by sensing amplifier 20, and time T3 is the time when word line WL begins to be pulled down. Therefore, time period Pb includes the kicking period of the start kick, voltage VCCSA is coupled to bit line BL in another time period (or the first time period), and voltage VCCSA+M1 is coupled to bit line BL in another time period (or the second time period). Voltage VCCSA+M1 is applied to bit line BL (the storage capacitance of the dynamic random access memory cell) for approximately more than 20% or 30% of time period Pb. Additionally, in another embodiment of the invention, the start kick is not required during the refresh period, that is, the voltage on bit line BL during the refresh period only includes the recovery kick.

[0159] Figure 11C (Early recovery kick performed in time series 2) This indicates that the time period Pa between the start kick and the early recovery kick is less than 30% of the time period Pb between time T1' and time T3. Therefore, the voltage VCCSA+M1 is applied to bit line BL for approximately 50% or 60% of the time period Pb. Figure 11D (Early recovery kick performed in timing 1) indicates that time period Pa is zero, meaning the early recovery kick replaces the start kick and continues until the voltage of word line WL is pulled low. Therefore, voltage VCCSA+M1 is applied to bit line BL for approximately more than 90% of time period Pb. However, if any reliability issues arise when a higher kick voltage VCCSA+M1 is continuously applied to the sensing amplifier 20 and the dynamic random access memory cell, then the voltage used for... Figure 11D The voltage VCCSA+M1 (when performing an early recovery kick in timing 1) will be less than the voltage used for... Figure 11C The voltage VCCSA+M1 (for early recovery kicking during timing 2). For example, when voltage VCCSA = 1.1V, it is used for... Figure 11DThe voltage VCCSA+M1 for early recovery kick in timing 1 can be 1.3V, and for Figure 11C The voltage VCCSA+M1 for early recovery kick in timing 2 can be 1.31-1.35V, and for Figure 11B The voltage VCCSA+M1 for early recovery kick in timing 3 can be 1.36-1.4V.

[0160] The eighth embodiment of the present application:

[0161] On the other hand, in a dynamic random access memory cell as shown in Figure 1B , 1H After the recovery phase, the voltage on the word line WL will be pulled down from voltage VPP (or a voltage higher than voltage VCC+VT) to the standby voltage (e.g. -0.3V) to inactivate the access transistor of the dynamic random access memory cell, the pre-charge phase will start and the voltage equalization circuit 21 will be activated to apply the reference voltage VREF to the bit line BL and the bit line BLB, where the reference voltage VREF is equal to 1 / 2* voltage VCCSA (or 1 / 2* voltage VCC), or equal to the bit line equalization voltage VBL at the recovery phase (where the bit line equalization voltage VBL is equal to half of the sum of the voltage on the bit line BL and the voltage on the bit line BLB). In a dynamic random access memory cell as shown in Figure 1B , 1H The bit line equalization voltage VBL is also equal to 1 / 2* voltage VCCSA (or 1 / 2* voltage VCC).

[0162] In the present application, during the recovery phase, the voltage on the bit line BL will be pumped (or kicked) to voltage VCCSA+M1 or a voltage higher than voltage VCCSA (hereinafter referred to as voltage "VCCSAh" or voltage "V2") by the sense amplifier 20. Similarly, after the recovery phase, the voltage on the word line WL will be lowered to turn off the access transistor of the dynamic random access memory cell, and the pre-charge phase will start and the voltage equalization circuit 21 will be activated to apply the reference voltage VREF to the bit line BL and the bit line BLB, where after the reference voltage VREF is applied to the bit line BL and the bit line BLB, the target value of the bit line equalization voltage VBL on the bit line BL and the bit line BLB is theoretically equal to the reference voltage VREF (i.e. 1 / 2* voltage VCCSA (or 1 / 2* voltage VCC) or the target reference voltage). However, in the present application, the bit line equalization voltage VBL between the voltage on the bit line BL and the voltage on the bit line BLB at the recovery phase will be equal to 1 / 2 voltage VCCSAh, where 1 / 2 voltage VCCSAh is higher than the reference voltage 1 / 2* voltage VCCSA.

[0163] Please refer toFigure 12A , Figure 12A is a schematic diagram illustrating a waveform of the relevant voltages during the recovery phase, when the voltage on the bit line BL is pumped (or kicked) to the voltage VCCSAh. Since, during the recovery phase, the voltage on the bit line BL is pumped (or kicked) to the voltage VCCSAh (or voltage "V2", which is the recovery voltage within the DRAM cell), at the beginning of the voltage equalization period EQBL, the voltage on the bit line BL and the voltage on the bit line BLB will be pulled to the voltage V1 (i.e., at the beginning of the voltage equalization period EQBL, the bit line BL can share the charge with the bit line BLB), where the voltage V1 is equal to 1 / 2*VCCSAh, and then the voltage on the bit line BL and the voltage on the bit line BLB gradually decrease to the target value of the bit line equalization voltage VBL. Since the voltage V1 is not equal to the target value of the bit line equalization voltage VBL (e.g., V1 > the target value of the bit line equalization voltage VBL), at the voltage equalization period EQBL, the excess voltage (V1 - the target value of the bit line equalization voltage VBL) will temporarily cause the bit line equalization voltage VBL on the bit line BL to rise (hereinafter referred to as the temporary bit line equalization voltage). Therefore, after the voltage equalization circuit 20 is not activated at the end of the voltage equalization period EQBL, the temporary bit line equalization voltage is still at an incorrect voltage level. Thus, it is necessary to wait for the low dropout circuit (LDO) within the bit line equalization voltage generator to correct the temporary bit line equalization voltage back to the target value of the bit line equalization voltage VBL (1 / 2*VCCSA). However, the low dropout circuit slowly corrects the temporary bit line equalization voltage such that the next activation command will be affected. For example, as shown in FIG. 6, when the next activation command occurs after the end of the voltage equalization period EQBL, since the temporary bit line equalization voltage is still higher than the target value of the bit line equalization voltage VBL, the temporary bit line equalization voltage will destroy the developed voltage accompanying the next activation command. Therefore, during the voltage equalization period EQBL, the excess voltage (V1 - the target value of the bit line equalization voltage VBL) must be removed, so that the correct bit line equalization voltage (i.e., the target value of the bit line equalization voltage VBL) and the correct developed voltage accompanying the next activation command can be achieved. Figure 12B

[0164] Thus, as shown in FIG. 7, during the voltage equalization period EQBL, the voltage on the bit line BL is pumped (or kicked) to the voltage VCCSAh, and then the voltage on the bit line BL and the voltage on the bit line BLB gradually decrease to the target value of the bit line equalization voltage VBL. Since the voltage V1 is not equal to the target value of the bit line equalization voltage VBL (e.g., V1 > the target value of the bit line equalization voltage VBL), at the voltage equalization period EQBL, the excess voltage (V1 - the target value of the bit line equalization voltage VBL) will temporarily cause the bit line equalization voltage VBL on the bit line BL to rise (hereinafter referred to as the temporary bit line equalization voltage). Therefore, after the voltage equalization circuit 20 is not activated at the end of the voltage equalization period EQBL, the temporary bit line equalization voltage is still at an incorrect voltage level. Thus, it is necessary to wait for the low dropout circuit (LDO) within the bit line equalization voltage generator to correct the temporary bit line equalization voltage back to the target value of the bit line equalization voltage VBL (1 / 2*VCCSA). However, the low dropout circuit slowly corrects the temporary bit line equalization voltage such that the next activation command will be affected. For example, as shown in FIG. 6, when the next activation command occurs after the end of the voltage equalization period EQBL, since the temporary bit line equalization voltage is still higher than the target value of the bit line equalization voltage VBL, the temporary bit line equalization voltage will destroy the developed voltage accompanying the next activation command. Therefore, during the voltage equalization period EQBL, the excess voltage (V1 - the target value of the bit line equalization voltage VBL) must be removed, so that the correct bit line equalization voltage (i.e., the target value of the bit line equalization voltage VBL) and the correct developed voltage accompanying the next activation command can be achieved. Figure 12A or Figure 12B ​As shown, during the recovery phase, the voltage on bit line BL is pumped (or kicked), and then the voltage on word line WL is reduced to turn off the access transistors of the dynamic random access memory cell, after which voltage equalization circuit 21 is activated. However, the excessive voltage (V1 - the target value of bit line equalization voltage VBL) will affect the next startup instruction. Therefore, the present invention discloses a clearing circuit, and during voltage equalization EQBL, the excessive voltage (V1 - the target value of bit line equalization voltage VBL) or excessive charge on bit lines BL / BLB can be reduced or cleared by the clearing circuit. Thus, before the next word line is started, the voltage on bit line BL and the voltage on bit line BLB are both set to the target value of bit line equalization voltage VBL (i.e., 1 / 2 * voltage VCCSA).

[0165] like Figure 13 As shown, the clearing circuit is controlled by a clear pulse CP. The start time of the clear pulse CP can be approximately the same as the on-time of EQBL during voltage equalization, or triggered by the rising edge of EQBL during voltage equalization (i.e., the rising edge of the clear pulse CP is substantially aligned with the rising edge of EQBL during voltage equalization). The width of the clear pulse CP depends on the recovery voltage (VCCSAh), so the wider the clear pulse CP needs to be, the higher the recovery voltage and the greater the excess voltage (V1 - the target value of the bit line equalization voltage VBL). With the help of the clearing circuit, the voltage on bit lines BL / BLB can be quickly changed from voltage V1 to the target value of the bit line equalization voltage VBL before the next startup of the character line WL, and the same applies to the temporary bit line equalization voltage. Therefore, the correct bit line equalization voltage (i.e., the target value of the bit line equalization voltage VBL) and the correct development voltage accompanying the next startup command can be achieved.

[0166] Please refer to Figure 14A ,in Figure 14A similar Figure 1C .like Figure 14A As shown, the sensing amplifier 20 and the voltage equalization circuit 21 are coupled to bit line BL and bit line BLB, while the clearing circuit 141 can be coupled to the sensing amplifier 20 (e.g., Figure 14B (as shown) or coupled to voltage equalization circuit 21 (such as Figure 14C (as shown), and the clearing circuit 141 can be activated during the voltage equalization period EQBL to clear the excess voltage.

[0167] For example, such as Figure 15AAs shown, the clearing circuit 141 includes a switching circuit 142 coupled to node SAP (or node LSLP) and ground GND (or other predetermined voltage level) of the sensing amplifier 20. Because the bit line BL / BLB is coupled to node SAP (or node LSLP) via two P-type metal-oxide-semiconductor transistors of the sensing amplifier 20, when the switching circuit 142 is activated by the clearing pulse CP during voltage equalization, the aforementioned excess voltage (V1 – the target value of the bit line equalization voltage VBL) will decrease, and excess charge will be released through the clearing pulse CP. Figure 15A The dashed path shown discharges to ground (GND). Therefore, after the clear pulse CP ends, the voltage on bit lines BL / BLB will be set to the target value of the bit line equalization voltage VBL. Additionally, EN1, EN2, and EN3 are control signals for the switches.

[0168] In such Figure 15B In another example, the clearing circuit 141 includes a switching circuit 142 coupled to node NBL of the voltage equalization circuit 21 and ground (or other predetermined voltage level). Because the bit lines BL / BLB are coupled to node NBL via two metal-oxide-semiconductor transistors of the voltage equalization circuit 21, when the switching circuit 142 is activated by the clearing pulse CP during the voltage equalization period EQBL, the aforementioned excess voltage (V1 - the target value A of the bit line equalization voltage VBL) will be reduced and excess charge will be released through the clearing pulse CP. Figure 15B The dashed path shown discharges to ground (GND). Therefore, at the end of the clear pulse CP, the voltage on bit lines BL / BLB will be set to the target value of the bit line equalization voltage VBL.

[0169] In practice, during voltage equalization (EQBL), the clearing circuit 141 can be coupled to any location that can clear the excess voltage (e.g., node SAN or node LSLN). For example, during EQBL, the clearing circuit 141 can be directly or indirectly electrically coupled to bit lines BL / BLB such that the clearing circuit 141 can reduce the difference between the voltage on bit line BL (or the voltage on bit line BLB) and the target value of the bit line equalization voltage VBL during EQBL.

[0170] In addition, even if the kick up voltage is not applied during the recovery phase, the cleaning circuit 141 can still be applied to the dynamic random access memory circuit as long as there is a difference between the voltage V1 and the target value of the bit line equalization voltage VBL. For example, if the voltage V1 > the target value of the bit line equalization voltage VBL, that is, the half of the sum of the voltage on the bit line BL and the voltage on the bit line BLB is higher than the target value of the bit line equalization voltage VBL at the beginning of the voltage equalization period EQBL, the cleaning circuit 141 can still be applied to the dynamic random access memory circuit. Therefore, because the bit line BL and the bit line BLB can be coupled to the ground GND (or other predetermined low voltage) through the cleaning circuit 141 during the cleaning pulse CP, the voltage on the bit line BL / BLB can be pulled down with the help of the cleaning circuit 141. Thus, after the cleaning pulse CP ends, the voltage on the bit line BL / BLB will be set at the target value of the bit line equalization voltage VBL.

[0171] On the other hand, if the voltage V1 < the target value of the bit line equalization voltage VBL, that is, the half of the sum of the voltage on the bit line BL and the voltage on the bit line BLB is lower than the target value of the bit line equalization voltage VBL at the beginning of the voltage equalization period EQBL, because the bit line BL and the bit line BLB can be connected to the voltage VCCSA (or other predetermined high voltage) through the cleaning circuit 141 during the cleaning pulse CP, the voltage on the bit line BL / BLB can be pulled up with the help of the cleaning circuit 141. Thus, after the cleaning pulse CP ends, the voltage on the bit line BL / BLB will be set at the target value of the bit line equalization voltage VBL. In addition, as shown in FIG. 1, the comparator circuit 143 can be used to compare the voltage V1 (or the half of the sum of the voltage on the bit line BL and the voltage on the bit line BLB) with the target value of the bit line equalization voltage VBL (or a predetermined reference voltage). For example, the comparator circuit 143 receives the voltage on the bit line BL, the voltage on the bit line BLB, and the target value of the bit line equalization voltage VBL at the beginning of the voltage equalization period EQBL, and compares the voltage V1 (or the half of the sum of the voltage on the bit line BL and the voltage on the bit line BLB) with the target value of the bit line equalization voltage VBL. If the voltage V1 is not equal to the target bit line equalization voltage 1 / 2*VCCSA, the comparator circuit 143 will send out a control signal CS to the cleaning circuit 141, and then the cleaning circuit 141 will be activated by the cleaning pulse CP during the voltage equalization period EQBL. In an embodiment of the present application, the width of the cleaning pulse CP is not greater than the length of the voltage equalization period EQBL. Thus, after the voltage equalization period EQBL ends, the voltage on the bit line BL / BLB will be set at the target value of the bit line equalization voltage VBL. Figure 15C

[0172] ​In summary, the dynamic random access memory (DRAM) disclosed in this invention restores or stores a first voltage higher than the signal "ONE" (i.e., a high-level signal) to the DRAM cell before the access transistors within the DRAM cell are turned off (or the word lines coupled to the DRAM cell are turned off). Similarly, the DRAM restores or stores a second voltage lower than the signal "ZERO" (i.e., a low-level signal) to the DRAM cell before the access transistors within the DRAM cell are turned off (or the word lines coupled to the DRAM cell are turned off). Thus, even after the access transistors within the DRAM cell are turned off, although leakage current still flows through the access transistors, the charge stored in the storage capacitors within the DRAM cell can be maintained for a longer period than in existing DRAM architectures. Furthermore, during voltage equalization, the clearing circuit is used to clear the excess voltage, thereby achieving the correct bit line equalization voltage and the correct development voltage accompanying the next boot instruction.

[0173] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dynamic random access memory, characterized by Comprising: a first sustain voltage source for generating a first voltage, wherein the first voltage is higher than a voltage of an applied high level signal in the dynamic random access memory; a dynamic random access memory cell comprising an access transistor and a storage capacitor; a sense amplifier coupled to a bit line and a complementary bit line, wherein the bit line is coupled to the storage capacitor through the access transistor; a voltage equalization circuit coupled to the bit line and the complementary bit line, wherein the voltage equalization circuit connects the bit line and the complementary bit line to a preset reference voltage during a voltage equalization period; and a clean-up circuit coupled to the voltage equalization circuit; wherein the first sustain voltage source is electrically coupled to the bit line during a turn-off period of the access transistor, and the clean-up circuit connects the preset reference voltage to a ground to reduce a difference between a voltage on the bit line and a target reference voltage during the voltage equalization period, wherein the target reference voltage is equal to half of the voltage of the high level signal.

2. The dynamic random access memory of claim 1, wherein Further comprising: a word line coupled to a gate of the access transistor, wherein the word line is selected to turn on the access transistor in a first period and a second period, the second period is after the first period, and the first sustain voltage source is electrically coupled to the bit line in the second period.

3. The dynamic random access memory of claim 2, wherein the first sustain voltage source is electrically coupled to the sense amplifier in the second period, and the first sustain voltage source is electrically coupled to the storage capacitor of the dynamic random access memory cell through the sense amplifier and the bit line.

4. The dynamic random access memory of claim 2, wherein the first period is during an access operation, and the second period is a recovery phase.

5. The dynamic random access memory of claim 4, wherein a pump voltage source is electrically coupled to the bit line during the access operation.

6. The dynamic random access memory of claim 2, wherein the first period comprises a first kick period and a second kick period, the first kick period and the second kick period are separated, and a pump voltage source is coupled to the bit line during the first kick period, or coupled to the bit line during the first kick period and the second kick period.

7. The dynamic random access memory of claim 6, wherein a voltage provided by the pump voltage source is less than the first voltage.

8. The dynamic random access memory of claim 2, wherein the word line is selected to turn on the access transistor in the first period and the second period according to a refresh operation.

9. The dynamic random access memory of claim 8, wherein a pump voltage source is electrically coupled to the bit line during a kick period, the kick period is before the first period, and the first sustain voltage source is electrically coupled to the bit line during the entire second period.

10. The dynamic random access memory of claim 9, wherein the second period is at least 20% of a sum of the kick period, the first period and the second period.

11. The dynamic random access memory as claimed in claim 9, wherein the second period is at least 50% of a sum of the kick period, the first period and the second period.

12. The dynamic random access memory of claim 1, wherein the voltage equalization period is after the access transistor is turned off, and the clean-up circuit is activated to make the voltage on the bit line equal to the preset reference voltage after the voltage equalization period.

13. The dynamic random access memory of claim 12, wherein the clean-up circuit is activated by a clean-up pulse, and a width of the clean-up pulse is not greater than a width of the voltage equalization period.

14. The dynamic random access memory as claimed in claim 12, wherein The reset circuit is activated by a reset pulse, and a rising edge of the reset pulse is aligned with a rising edge of the voltage equalization period.

15. The dynamic random access memory of claim 1, wherein The reset circuit includes a switch circuit, and the switch circuit is coupled between the sense amplifier and a predetermined voltage.

16. The dynamic random access memory of claim 1, wherein The reset circuit includes a switch circuit, and the switch circuit is coupled between the voltage equalization circuit and a predetermined voltage.

17. A dynamic random access memory, comprising: Comprise: a dynamic random access memory cell comprising an access transistor and a storage capacitor; a sense amplifier coupled between a bit line and a complementary bit line, wherein the bit line is coupled to the storage capacitor through the access transistor; a voltage equalization circuit coupled between the bit line and the complementary bit line, wherein the voltage equalization circuit connects the bit line and the complementary bit line to a predetermined reference voltage during a voltage equalization period; and a reset circuit coupled between the bit line and the complementary bit line during the voltage equalization period; wherein the reset circuit reduces a difference between a voltage on the bit line and a target reference voltage during the voltage equalization period, wherein the target reference voltage is equal to half of a voltage of a high level signal applied in the dynamic random access memory.

18. The dynamic random access memory as in claim 17, wherein The voltage on the bit line is equal to the predetermined reference voltage after the voltage equalization period.

19. The dynamic random access memory as in claim 17, wherein The reset circuit is electrically coupled between the bit line and the complementary bit line through the sense amplifier or the voltage equalization circuit during the voltage equalization period.

20. The dynamic random access memory as in claim 19, wherein The reset circuit includes a switch circuit, and the switch circuit is coupled between the sense amplifier and a predetermined voltage.

21. The dynamic random access memory as in claim 19, wherein The reset circuit includes a switch circuit, and the switch circuit is coupled between the voltage equalization circuit and a predetermined voltage.

22. The dynamic random access memory as in claim 19, wherein The reset circuit is activated by a reset pulse during the voltage equalization period, and a rising edge of the reset pulse is aligned with a rising edge of the voltage equalization period.

23. The dynamic random access memory as in claim 19, wherein Further comprise: a comparator circuit receiving a voltage on the bit line, a voltage on the complementary bit line, and the predetermined reference voltage during the voltage equalization period or at the beginning of the voltage equalization period, and sending a control signal to the reset circuit when half of a sum of the voltage on the bit line and the voltage on the complementary bit line is not equal to the predetermined reference voltage.

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