Memory operation methods, memory, memory systems and electronic devices

Abstract

This disclosure provides an operation method for a memory, a memory, a memory system, and an electronic device. The memory includes a memory cell array and peripheral circuitry; the memory cell array includes multiple memory cells, each memory cell having any one of multiple memory states; the method includes: detecting a threshold voltage offset value of a target memory state among the multiple memory states; and determining a compensation value for an erase voltage corresponding to the target memory state based on the threshold voltage offset value of the target memory state.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for operating a memory, a memory, a memory system, and an electronic device. Background Technology

[0002] With the continuous development of semiconductor technology, memory manufacturing technology has gradually transitioned from simple planar structures to more complex three-dimensional structures, increasing integration density by arranging memory cells three-dimensionally on a substrate. The development of this three-dimensional memory device (3D NAND) technology is one of the mainstream international research and development efforts.

[0003] Currently, when performing an erase operation on 3D NAND, it is often necessary to adjust the erase voltage multiple times to achieve a successful erase, resulting in a long erase time and poor erase performance. Summary of the Invention

[0004] In view of the above, this disclosure provides a method for operating a memory, a memory, a memory system, and an electronic device to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0006] A first aspect of this disclosure provides a method for operating a memory, the memory including a memory cell array and peripheral circuitry; the memory cell array includes a plurality of memory cells, each memory cell having any one of a plurality of memory states; the method includes:

[0007] Detect the threshold voltage offset value of the target storage state among the multiple storage states;

[0008] Based on the threshold voltage offset value of the target storage state, determine the compensation value of the erase voltage corresponding to the target storage state.

[0009] In some embodiments, detecting the threshold voltage offset of a target storage state among the plurality of storage states includes: performing a read operation on a plurality of target storage cells based on a read voltage to obtain a verification error bit count; determining the number of conducting storage cells based on the verification error bit count; the conducting storage cells being storage cells among the plurality of target storage cells whose threshold voltage is less than the read voltage; and determining the actual threshold voltage of the target storage state based on the number of conducting storage cells.

[0010] In some embodiments, determining the actual threshold voltage of the target storage state based on the number of active storage units includes: in response to the number of active storage units being less than a preset value, gradually increasing the read voltage by a step size until the number of active storage units is greater than or equal to the preset value; and in response to the number of active storage units being greater than or equal to the preset value, determining the actual threshold voltage of the target storage state based on the current read voltage.

[0011] In some embodiments, detecting the threshold voltage offset of a target storage state among the plurality of storage states further includes: determining the threshold voltage offset of the target storage state based on the difference between the current read voltage and the initial read voltage of the target storage state; wherein the initial read voltage is the minimum value of the theoretical threshold voltage of the target storage state.

[0012] In some embodiments, determining the compensation value of the erase voltage corresponding to the target storage state based on the threshold voltage offset value of the target storage state includes: determining the compensation value of the erase voltage corresponding to the target storage state based on the difference between the current read voltage and the initial read voltage of the target storage state.

[0013] In some embodiments, the ratio of the compensation value of the erase voltage to the difference between the current read voltage and the initial read voltage ranges from 0.8 to 1.2.

[0014] In some embodiments, before detecting the threshold voltage offset value of a target storage state among the plurality of storage states, the method further includes: applying a pre-programming voltage to the plurality of target storage cells to perform a pre-programming operation.

[0015] In some embodiments, the target storage state is an erase state prior to the pre-programming operation.

[0016] In some embodiments, the method further includes: determining a compensated erase voltage based on an initial erase voltage and a compensation value for the erase voltage; and performing an erase operation based on the compensated erase voltage.

[0017] A second aspect of this disclosure provides a memory, the memory comprising: a memory cell array, the memory cell array comprising a plurality of memory cells; each memory cell having any one of a plurality of memory states;

[0018] Peripheral circuitry coupled to the memory cell array; the peripheral circuitry is configured to:

[0019] Detect the threshold voltage offset value of the target storage state among the multiple storage states;

[0020] Based on the threshold voltage offset value of the target storage state, determine the compensation value of the erase voltage corresponding to the target storage state.

[0021] In some embodiments, the peripheral circuit is specifically configured to: perform read operations on a plurality of target memory cells based on the read voltage to obtain a verification error bit count; determine the number of active memory cells based on the verification error bit count; the active memory cells are memory cells among the plurality of target memory cells whose threshold voltage is less than the read voltage; and determine the actual threshold voltage of the target memory state based on the number of active memory cells.

[0022] In some embodiments, the peripheral circuit is specifically configured to: in response to the number of conducting memory cells being less than a preset value, gradually increase the read voltage by a step size until the number of conducting memory cells is greater than or equal to the preset value; in response to the number of conducting memory cells being greater than or equal to the preset value, determine the actual threshold voltage of the target storage state based on the current read voltage.

[0023] In some embodiments, the peripheral circuit is specifically configured to: determine a threshold voltage offset value of the target storage state based on the difference between the current read voltage and the initial read voltage of the target storage state; the initial read voltage is the minimum value of the theoretical threshold voltage of the target storage state.

[0024] In some embodiments, the peripheral circuit is specifically configured to: determine a compensation value for the erase voltage corresponding to the target storage state based on the difference between the current read voltage and the initial read voltage of the target storage state.

[0025] In some embodiments, the ratio of the compensation value of the erase voltage to the difference between the current read voltage and the initial read voltage ranges from 0.8 to 1.2.

[0026] In some embodiments, the peripheral circuitry is further configured to apply a pre-programming voltage to the plurality of target memory cells to perform a pre-programming operation before detecting the threshold voltage offset value of the target memory state among the plurality of memory states.

[0027] In some embodiments, the target storage state is an erase state prior to the pre-programming operation.

[0028] In some embodiments, the peripheral circuit is further configured to: determine a compensated erase voltage based on the initial erase voltage and a compensation value for the erase voltage; and perform an erase operation based on the compensated erase voltage.

[0029] A third aspect of this disclosure provides a memory system comprising: at least one memory as described above; and a controller coupled to the memory.

[0030] A fourth aspect of this disclosure provides an electronic device including the memory system described above.

[0031] This disclosure provides an operation method for a memory, a memory, a memory system, and an electronic device. The memory includes a memory cell array and peripheral circuitry; the memory cell array includes multiple memory cells, each memory cell having any one of multiple memory states; the method includes: detecting a threshold voltage offset value of a target memory state among the multiple memory states; and determining a compensation value for an erase voltage corresponding to the target memory state based on the threshold voltage offset value of the target memory state. This disclosure determines the compensation value for the erase voltage corresponding to the target memory state based on the threshold voltage offset value of the target memory state. Using the compensation value for the erase voltage during the erase operation can improve erase efficiency, thereby improving the reliability of the memory. Attached Figure Description

[0032] Figure 1 This is a block diagram of a memory system according to an exemplary embodiment of the present disclosure;

[0033] Figure 2a This is a schematic diagram illustrating a memory card according to an exemplary embodiment of the present disclosure;

[0034] Figure 2b This is a schematic diagram illustrating a solid-state drive (SSD) according to an exemplary embodiment of the present disclosure;

[0035] Figure 3 A schematic diagram of an exemplary memory including peripheral circuitry provided for embodiments of this disclosure;

[0036] Figure 4 A schematic cross-section of an exemplary memory cell array including memory strings, provided for embodiments of this disclosure;

[0037] Figure 5 A block diagram of an exemplary storage device including a storage cell array and peripheral circuitry, provided for embodiments of this disclosure;

[0038] Figure 6 A schematic diagram of an erasure method provided in an embodiment of this disclosure;

[0039] Figure 7 A pulse diagram illustrating an erasure operation provided in an embodiment of this disclosure;

[0040] Figure 8aA schematic diagram illustrating the variation in the number of times an erasure voltage is applied, as provided in an embodiment of this disclosure;

[0041] Figure 8b A schematic diagram illustrating the change in erasure time provided in an embodiment of this disclosure;

[0042] Figure 9 This is a schematic diagram illustrating the variation of VgVt provided in an embodiment of the present disclosure;

[0043] Figure 10 A schematic diagram illustrating the change in threshold voltage of a target storage state provided in an embodiment of this disclosure;

[0044] Figure 11 A schematic diagram illustrating the variation of VwVt provided in an embodiment of this disclosure;

[0045] Figure 12 A flowchart illustrating a method for operating a memory according to an embodiment of this disclosure;

[0046] Figure 13 A detailed flowchart illustrating a memory operation method provided in this embodiment of the present disclosure;

[0047] Figure 14 A schematic diagram of the threshold voltage distribution of a target storage state provided in an embodiment of this disclosure;

[0048] Figure 15a A schematic diagram illustrating another variation in the number of times the erase voltage is applied, provided in an embodiment of this disclosure;

[0049] Figure 15b This is a schematic diagram illustrating another change in erasure time provided by an embodiment of this disclosure. Detailed Implementation

[0050] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0051] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0052] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0053] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0055] refer to Figure 1 , Figure 1 This is a block diagram illustrating a memory system according to an exemplary embodiment of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0056] Memory 104 can be any memory disclosed in this disclosure. As disclosed in detail below, memory 104 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0057] According to some embodiments, controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, controller 106 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. Controller 106 can be configured to control operations of memory 104, such as read, erase, and program operations. Controller 106 can also be configured to manage various functions related to data stored or to be stored in memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to memory 104. Controller 106 may also perform any other suitable functions, such as formatting memory 104. Controller 106 may communicate with external devices (e.g., host 108) according to specific communication protocols. For example, controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0058] The controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, controller 106 and a single memory 104 can be integrated into memory card 202. Memory card 202 can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 202 can also include a connection between memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, controller 106 and multiple memories 104 can be integrated into SSD 206. SSD 206 may also include interfaces for connecting SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0059] Figure 3 A schematic circuit diagram of an exemplary memory 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory 300 may be... Figure 1 An example of memory 104 is shown. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0060] Each of the aforementioned storage units 306 has any one of a plurality of storage states. Specifically, each storage unit 306 can be configured to have 2 N One of the storage states stores N bits of data, where N is a natural number greater than 0. This 2 N The storage states include erase state and 2. N-1 non-erasable state. In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states (levels) and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first threshold voltage range, while a second storage state "1" may correspond to a second threshold voltage range. In some embodiments, each memory cell 306 is an xLC capable of storing more than a single bit of data in more than four storage states (levels). In one example, programming is performed by writing one of three possible nominal storage values ​​to the MLC memory cell to program the MLC memory cell from an erase state to one of three possible programming levels (e.g., 01, 10, and 11). A fourth nominal storage value may be used to indicate an erase state (e.g., 00).

[0061] like Figure 3 As shown, each NAND memory string 308 may further include a source-select-gate (SSG) transistor 310 at its source end and a drain-select-gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 may be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 308 is coupled to a corresponding bit line 316 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage or deselect voltage to the gate of the corresponding DSG transistor 312 via one or more DSG lines 313 and / or by applying a select voltage or deselect voltage to the gate of the corresponding SSG transistor 310 via one or more SSG lines 315.

[0062] like Figure 3As shown, NAND flash memory strings 308 can be organized into multiple memory blocks 304, each memory block may have a common source line 314, for example, coupled to an ACS (Acoustic Array of Elements). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive bias (e.g., 20V or greater)) can be used to bias the source line 314 coupled to the selected memory block 304 and unselected memory blocks 304 in the same plane as the selected memory block 304. Memory cells 306 adjacent to the NAND flash memory string 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit for read and program operations. The size of a page 320, measured in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) and gate lines coupling the control gates at each memory cell 306 in the corresponding page 320.

[0063] like Figure 3 As shown, the memory cell array 301 may include an array of memory cells 306 in multiple rows and columns within each memory block 304. According to some embodiments, a row of memory cells 306 corresponds to one or more pages 320, and a column of memory cells corresponds to a NAND flash memory string 308. Multiple rows of memory cells 306 may be coupled to word lines 318, and multiple columns of memory cells 306 may be coupled to bit lines 316. Peripheral circuitry 302 may be coupled to the memory cell array 301 via bit lines 316 and word lines 318.

[0064] Figure 4 A schematic cross-sectional view of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 can extend vertically through the memory stack layer 404 above the substrate 402. The substrate 402 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0065] The memory stack 404 may include alternating gate conductive layers 406 and gate-to-gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate-to-gate dielectric layers 408 in the memory stack 404 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306 and may extend laterally at the top of the memory stack 404 as a DSG line 313, at the bottom of the memory stack 404 as an SSG line 315, or between DSG lines 313 and SSG lines 315 as a word line 318.

[0066] like Figure 4 As shown, the NAND flash memory string 308 includes a channel structure 412 extending vertically through the memory stack layer 404. In some embodiments, the channel structure 412 includes channel vias filled with one or more semiconductor materials (e.g., as semiconductor channel 420) and one or more dielectric materials (e.g., as memory film 418). In some embodiments, the semiconductor channel 420 includes silicon, for example, polysilicon. In some embodiments, the memory film 418 is a composite dielectric layer including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trap / storage layer"), and a barrier layer 422. The channel structure 412 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 420, tunneling layer 426, storage layer 424, and barrier layer 422 are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 418 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0067] According to some implementation methods, such as Figure 4As shown, a well 414 (e.g., a P-well and / or an N-well) is formed in a substrate 402, and the source terminal of the NAND memory string 308 is in contact with the well 414. For example, a source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory string 308) during an erase operation. In some embodiments, the NAND memory string 308 also includes a channel plug 416 at the drain terminal of the NAND memory string 308. It should be understood that, although in Figure 4 Additional components, not shown, but which may form the memory cell array 301, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0068] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0069] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0070] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive SSG lines 315 and DSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform an erase operation on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0071] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0072] Figure 6 This is a schematic diagram of an erasure method provided in an embodiment of this disclosure. Figure 6 As shown, in step 601, the storage cells in the storage block are pre-programmed.

[0073] Here, before erasing the storage block, the storage cells in the storage block need to be pre-programmed. This is mainly because some storage cells in the storage block may have been written with data and are in a non-erasable state, while other storage cells may not have been written with any data and are in an erasable state. When erasing storage cells that have not been written with data, over-erasure can easily occur, thereby damaging the storage cells.

[0074] To avoid over-erasing of memory cells that have not been written with any data during the erase operation, the memory cells in the memory block are pre-programmed before the erase operation so that all memory cells in the memory block are in a non-erasable state. In some embodiments, the pre-programming operation can be performed only on the memory cells in the memory block that are in the erase state, and the pre-programming operation can program them to the lowest memory state among the non-erasable states, thereby reducing the pre-programming time and thus reducing the erase operation time. For example, for a QLC memory cell, each QLC memory cell can have any of the memory states P0-P15, and the pre-programming operation can program the memory cells in P0 (erasable state) to P1.

[0075] In step 602, the storage block is erased.

[0076] Here, an erase voltage is applied to the memory block to perform an erase operation.

[0077] In step 603, verify whether the erasure operation was successful.

[0078] Here, a verification voltage is applied to the word line of the memory cell in the memory block. Based on the relationship between the threshold voltage of the memory cell and the verification voltage, it is determined whether the erase operation was successful. If the erase operation is determined to have failed, step 604 is executed; if the erase operation is determined to have succeeded, step 605 is executed.

[0079] If the threshold voltage of the storage cell is greater than or equal to the verification voltage, the erase operation is determined to have failed. Step 604 is executed to increase the erase voltage by a certain step, and step 602 is executed again to erase the storage block based on the increased erase voltage, and the success of the erase operation is verified.

[0080] If the threshold voltage of the storage cell is less than the verification voltage, the erase operation is considered successful, and step 605 is executed to end the erase operation.

[0081] The erase operation is performed using Incremental Step Pulse Erase (ISPE). The initial erase voltage and the step size (ISPE step) are fixed. The erase voltage is gradually increased from the initial erase voltage in one step. After each erase voltage is applied, an erase verification is performed.

[0082] In some embodiments, if the number of failed erase operations exceeds a predetermined number, the erase operation on the memory block is stopped. Since memory cells may become damaged during use, and damaged cells may not be successfully erased, an upper limit, or preset number, can be set for the number of failed erase operations. If the number of failed erase operations exceeds the predetermined number, the erase operation is stopped, thus avoiding repeated and ineffective erasure of damaged memory cells and shortening the erase time.

[0083] Combination Figure 7 , Figure 7 This is a pulse diagram illustrating an erasure operation provided in an embodiment of this disclosure. Figure 7 As shown, the horizontal axis represents time, and the vertical axis represents voltage. In the first erase stage 701, an erase voltage is applied to erase the memory block. Then, in the first verification stage 702, a verification voltage is applied to verify whether the erase operation was successful. If the erase operation fails, the erase voltage is increased by V. Step Then perform the erase operation again until the erase operation is successful. Here, V Step This refers to the step size of the erase voltage.

[0084] However, during memory use, as the number of erase / program cycles increases, the tunneling layer of the memory cell develops defects due to repeated electron tunneling. These defects slow down the rate at which electrons are released from the charge trapping layer of the memory cell during the erase operation, resulting in a decrease in erase speed and an increase in erase time. In other embodiments, defects in the tunneling layer of the memory cell can trap some electrons, requiring electrons at the defect sites to recombine preferentially when holes are injected during the erase process, thus slowing down the erase speed. For example, as the number of erase / program cycles increases, the number of erase voltages required for a complete erase operation increases, that is, the number of erase voltages required to successfully erase the memory block increases, which in turn increases the erase time. A complete erase operation includes all erase-verify cycles required to successfully erase the memory block.

[0085] Figure 8a This is a schematic diagram illustrating the variation in the number of times an erase voltage is applied, as provided in an embodiment of this disclosure. Figure 8a As shown, the horizontal axis represents the number of erase / write cycles, and the vertical axis represents the number of times the erase voltage was applied. It should be noted that the number of erase voltage applications on the vertical axis represents the average of multiple test results. As the number of erase / write cycles increases, defects develop in the tunneling layer of the memory cell. These defects slow down the rate at which electrons are released from the charge trapping layer of the memory cell during the erase operation, while simultaneously increasing the rate at which electrons are trapped by the charge trapping layer during the programming operation. This results in a slower erase speed and a faster programming speed. Slower erase speeds mean that a complete erase operation requires more erase voltages. For example, when the erase / write cycle count of a memory cell is 10,000, a complete erase operation only requires 4 erase voltages, meaning the erase voltage needs to be increased 3 times to achieve a successful erase. However, when the erase / write cycle count of the memory cell is 100,000 (equivalent to the end of the lifespan of a conventional SLC memory cell), a complete erase operation requires 6 erase voltages, meaning the erase voltage needs to be increased 5 times to achieve a successful erase.

[0086] Figure 8b This is a schematic diagram illustrating the change in erasure time provided in an embodiment of this disclosure. Figure 8bAs shown, the horizontal axis represents the number of erase / write cycles, and the vertical axis represents the erase time. It should be noted that the erase time on the vertical axis represents the average erase time from multiple tests. As mentioned earlier, as the number of erase / write cycles increases, the erase speed decreases, leading to an increase in the erase time required for a complete erase operation. For example, when the number of erase / write cycles for a memory cell is 10,000, a complete erase operation takes approximately 6.8 ms, while when the number of erase / write cycles for the same memory cell is 100,000, a complete erase operation takes approximately 9.7 ms. It is evident that as the number of erase / write cycles increases, both the number of erase voltages applied and the erase time required for a complete erase operation increase significantly.

[0087] Figure 9 This is a schematic diagram illustrating the variation of VgVt according to an embodiment of this disclosure. Figure 9 As shown, the horizontal axis represents the number of erase / write cycles, and the vertical axis represents VgVt, with units in millivolts (mV). Where VgVt = Vg - Vt, Vg refers to the programming / pre-programming voltage applied to the memory cell, and Vt refers to the threshold voltage of the memory cell after programming / pre-programming based on Vg. As mentioned earlier, the programming speed of the memory cell increases with the increase in the number of erase / write cycles. Figure 9 As shown, VgVt decreases with increasing erase / write cycles. This decrease in VgVt indicates that, assuming Vg remains constant (i.e., the programming / preprogramming voltage remains constant), the threshold voltage of a memory cell will be higher after programming / preprogramming for a higher number of erase / write cycles; or, assuming Vt remains constant (i.e., to keep the threshold voltage of the memory cell constant after programming / preprogramming), the programming / preprogramming voltage Vg applied to a memory cell needs to be smaller for a higher number of erase / write cycles).

[0088] For example, Figure 10 This is a schematic diagram illustrating the change in the threshold voltage of a target storage state, provided as an embodiment of this disclosure. For example... Figure 10 As shown, the horizontal axis represents the number of erase / write cycles, and the vertical axis represents the threshold voltage of the target storage state. It should be noted that the threshold voltage distribution corresponding to any storage state follows a normal distribution; the leftmost side of the distribution represents its minimum value, and the rightmost side represents its maximum value. Here, Figure 10 The threshold voltage of the target storage state refers to the minimum value in the threshold voltage distribution corresponding to the target storage state. Combined with... Figure 9 and Figure 10With a constant applied programming / preprogramming voltage Vg, VgVt decreases as the number of erase / write cycles increases, meaning the threshold voltage of the target memory state increases. For example, compared to a memory cell with 10k erase / write cycles, the threshold voltage of a memory cell with 100k erase / write cycles increases by approximately 350mV.

[0089] Figure 11 This is a schematic diagram illustrating the variation of VwVt according to an embodiment of this disclosure. Figure 11 As shown, the horizontal axis represents the number of erase / write cycles, and the vertical axis represents VwVt, with units in millivolts (mV). Here, VwVt = Vw + Vt, where Vw is the erase voltage applied to the memory cell, and Vt is the threshold voltage of the memory cell after the erase operation based on the erase voltage Vw. As mentioned earlier, as the number of erase / write cycles increases, the erase speed of the memory cell slows down. Figure 11 As shown, VwVt increases with the number of erase / write cycles. Furthermore, combining... Figure 9 and Figure 11 It can be seen that the decreasing trend of VgVt is close to the increasing trend of VwVt, meaning that the increasing trend of programming speed of memory cells is close to the decreasing trend of erasure speed. Here, the increasing VwVt indicates that, assuming Vw remains constant (i.e., the erase voltage remains constant), for memory cells with more erase / write cycles, the threshold voltage of that memory cell after the erase operation will be higher; or, assuming Vt remains constant, that is, in order to keep the threshold voltage of the memory cell after the erase operation constant, for memory cells with more erase / write cycles, the erase voltage Vw applied to it needs to be higher. For example, to keep the threshold voltage of the memory cell after the erase operation constant, the erase voltage of a memory cell with 100k erase / write cycles needs to be increased by approximately 400mV compared to a memory cell with 10k erase / write cycles. Combined with... Figure 10 and Figure 11 It can be seen that there is a relationship between the change in erase voltage and the change in the threshold voltage of the target storage state. For example, if the threshold voltage of the target storage state increases by about 350mV, then in order to keep the threshold voltage of the storage cell unchanged after the erase operation, the erase voltage needs to be compensated by about 400mV.

[0090] Therefore, this disclosure provides a method for operating a memory. Figure 12 This is a flowchart illustrating a memory operation method provided in an embodiment of the present disclosure, as shown below. Figure 12As shown, in step 1201, the threshold voltage offset value of the target storage state among multiple storage states is detected. The target storage state can be any non-erasable state among the multiple storage states. For example, for a QLC storage cell, P0 is its erased state, and P1-P15 are its non-erasable states; therefore, the target storage state can be any of P1-P15. The threshold voltage distribution corresponding to any storage state satisfies a normal distribution, and the threshold voltage of the target storage state refers to the minimum value in the threshold voltage distribution corresponding to the target storage state. The threshold voltage offset value of the target storage state refers to the difference between the actual threshold voltage and the theoretical threshold voltage of the target storage state. Here, the actual threshold voltage is the minimum value in the actual threshold voltage distribution, and the theoretical threshold voltage is the minimum value in the theoretical threshold voltage distribution. That is, the threshold voltage offset value of the target storage state is the difference between the minimum value in the actual threshold voltage distribution and the minimum value in the theoretical threshold voltage distribution. As mentioned earlier, the increased number of erase / write cycles leads to defects in the tunneling layer of the memory cell. These defects slow down the rate at which electrons are released from the charge trapping layer of the memory cell during the erase operation, while speeding up the rate at which electrons are trapped by the charge trapping layer of the memory cell during the programming operation. This results in a decrease in the erase speed and an increase in the programming speed, which in turn causes a deviation between the actual threshold voltage and the theoretical threshold voltage of the target memory state after programming / preprogramming.

[0091] In step 1202, the compensation value of the erase voltage corresponding to the target storage state is determined based on the threshold voltage offset value of the target storage state.

[0092] Here, the initial erase voltage can be compensated based on the compensation value of the erase voltage corresponding to the target storage state to obtain a compensated erase voltage. In other embodiments, the increment of the erase voltage in subsequent erase operations can also be compensated based on the compensation value of the erase voltage corresponding to the target storage state to obtain a compensated erase voltage increment.

[0093] As mentioned earlier, the increased number of erase / write cycles leads to defects in the tunneling layer of the memory cell. These defects reduce the erasure speed and increase the programming speed, and studies have shown that the trend of decreasing erasure speed is similar to the trend of increasing programming speed. Therefore, in this embodiment, the compensation value of the erase voltage is determined by the threshold voltage offset value of the target memory state, and the erase voltage is compensated based on this compensation value to compensate for the problem of reduced erasure speed caused by the increased number of erase / write cycles. This disclosure determines the compensation value of the erase voltage corresponding to the target memory state based on the threshold voltage offset value of the target memory state, which can dynamically adjust the compensation value of the erase voltage corresponding to the target memory state, and then use the compensation value of the erase voltage to adjust the initial erase voltage for the erase operation. By directly adjusting the initial erase voltage using the compensation value of the erase voltage, this disclosure can reduce the number of adjustments to the initial erase voltage, that is, reduce the number of times the erase voltage needs to be applied in the erase operation, thereby reducing the erase time and improving the erase efficiency.

[0094] Figure 13 This is a detailed flowchart illustrating a method for operating a memory according to an embodiment of this disclosure. Figure 13 As shown, in step 1301, a pre-programming voltage is applied to multiple target memory cells to perform a pre-programming operation. This pre-programming operation is related to... Figure 6 The pre-programming shown is similar and will not be described again. In some embodiments, the target storage state corresponding to the target storage unit is an erased state before the pre-programming operation.

[0095] In step 1302, read operations are performed on multiple target memory cells based on the read voltage to obtain the Verify Failure Count (VFC). Since multiple target memory cells are coupled to the same word line, the read voltage VFC can be used to... rd An application is made to the word lines of multiple target memory cells. Then, based on the sensed voltage generated on the bit line of each target memory cell, it is determined whether the target memory cell is turned on, and the result of whether it is turned on or off is stored in the latch corresponding to that target memory cell. For example, the sensed voltage generated for each target memory cell is compared with a reference voltage. The reference voltage can be preset based on experience. If the sensed voltage is greater than or equal to the reference voltage, it indicates that the target memory cell is turned on; that is, the threshold voltage of the target memory cell is less than the read voltage V. rd At this point, the state value "1" is stored in the latch corresponding to the target memory cell; in response to the sensing voltage being less than the reference voltage, it indicates that the target memory cell is not turned on, that is, the threshold voltage of the target memory cell is greater than the read voltage V. rdAt this point, the state value "0" is stored in the latch corresponding to the target storage unit.

[0096] Furthermore, the threshold voltage below the read voltage V is calculated by verifying the error bit count. rd The number of target memory cells. As mentioned earlier, based on whether the target memory cell is on or off, a status value of "1" or "0" is stored on the latch corresponding to that target memory cell. For example, when a status value of "1" indicates that the target memory cell is on (i.e., the threshold voltage of the target memory cell is less than the read voltage), if there are N latches with a status value of "1", then the verification error bit count is assigned to N. That is, the verification error bit count indicates that the threshold voltage of multiple target memory cells is lower than the read voltage V. rd The number of target storage units.

[0097] In step 1303, the number of active memory cells is determined based on the verification error bit count. Active memory cells are those among the multiple target memory cells whose threshold voltage is less than the read voltage.

[0098] Here, the number of active memory cells is the value of the verification error bit count.

[0099] In step 1304, it is determined whether the number of active memory cells is greater than or equal to a preset value. This preset value can be set based on experience and the product parameters of the memory. If it is determined that the number of active memory cells is less than the preset value, then step 1305 is executed; if it is determined that the number of active memory cells is greater than or equal to the preset value, then step 1306 is executed.

[0100] If the number of activated memory cells is less than a preset value, proceed to step 1305, gradually increasing the read voltage by the first step length, for example, the first step length is V. rd-delta When, then use V rd-delta Increase the reading voltage V rd And based on the reading voltage (V) after the first step length is increased. rd +V rd-delta Continue executing step 1302, and perform read operations on multiple target memory cells again based on the increased read voltage, and obtain the verification error bit count until the number of conducting memory cells is greater than or equal to the preset value.

[0101] If the number of active memory cells is greater than or equal to a preset value, proceed to step 1306 to determine the actual threshold voltage of the target memory state based on the current read voltage. The current read voltage refers to the read voltage corresponding to when the number of active memory cells is greater than or equal to the preset value. The target memory state can be any non-erased state among multiple memory states. Figure 14 This is a schematic diagram of the threshold voltage distribution of a target storage state provided in an embodiment of the present disclosure, as shown below. Figure 14 As shown, the threshold voltage distribution of the target storage state follows a normal distribution, and 1404 is the minimum value in the threshold voltage distribution, which is also the actual threshold voltage of the target storage state. According to the memory operation method provided in this embodiment, 1401 is the first read voltage V applied to multiple target storage cells. rd Then execute as follows Figure 13 Steps 1302-1304 shown herein, in response to the number of conducting memory cells being less than a preset value, are performed with a first step length V. rd-delta Increase the reading voltage V rd This continues until the number of activated memory cells is greater than or equal to a preset value. For example, when the read voltage V... rd When the value is increased from 1401 to 1402, the number of conducting memory cells is less than the preset value, and the read voltage V will be lower. rd When the voltage is increased from 1402 to 1403 again, if the number of conducting memory cells is greater than or equal to the preset value, then the current read voltage, that is, the read voltage at 1403, can be approximated as the actual threshold voltage of the target memory state.

[0102] In step 1307, the threshold voltage offset value of the target storage state is determined based on the difference between the current read voltage and the initial read voltage of the target storage state. The initial read voltage can be set to the minimum value of the theoretical threshold voltage distribution of the target storage state. That is, the value of the initial read voltage can be set based on the minimum value of the theoretical threshold voltage distribution of the target storage state. For example, combined with Figure 14 As shown, the initial read voltage is the read voltage at position 1401, and the current read voltage is the read voltage at position 1403. As mentioned earlier, the current read voltage can be approximated as the actual threshold voltage of the target storage state. Therefore, the threshold voltage offset of the target storage state can be determined based on the difference between the current read voltage and the initial read voltage of the target storage state.

[0103] In step 1308, the compensation value of the erase voltage corresponding to the target storage state is determined based on the threshold voltage offset value of the target storage state.

[0104] As previously shown, the threshold voltage offset of the target memory state can be determined based on the difference between the current read voltage and the initial read voltage of the target memory state. For example, V rd2 V is the current reading voltage. rd1 Given the initial read voltage, the threshold voltage offset value for the target storage state is V. rd2 -V rd1 Furthermore, the compensation value for the erase voltage corresponding to the target storage state is V = ((V rd2 -V rd1 ) / V rd-delta )*Vera-delta Among them, V rd-delta For example Figure 13 In step 1305 shown, the step size of each voltage increase (i.e., the first step size) is read. era-delta This represents the step size for each increment of the initial erase voltage. V rd1 V rd-delta and V rd-delta This can be determined based on experience and the memory's product parameters. In some embodiments, the erase voltage compensation value V and the current read voltage V rd2 With the initial read voltage V rd1 The ratio of the differences between them ranges from 0.8 to 1.2, i.e., V / (V r d2 -V rd1 The value is approximately 0.8-1.2.

[0105] In some embodiments, a compensated erase voltage is determined based on an initial erase voltage and a compensated erase voltage value. The initial erase voltage can be determined based on experience and the memory's product parameters. For example, V era1 Let V be the initial erase voltage, and V be the compensation value for the erase voltage. Then the compensation erase voltage V0 is... era =V era1 +V. Based on the compensated erase voltage V era The erase operation is performed. If the erase fails, the compensation erase voltage V is increased by a certain step. era The erasure continues until successful. In some embodiments, the compensated erase voltage can be used as the initial erase voltage in the ISPE for the erase operation. The compensated erase voltage V... era The increment size for each increase is the same as the increment size V of the initial erase voltage for each increase. era-delta They can be the same or different. The specific steps of the erasure operation are the same as... Figure 6 The erasure operation shown is similar, so it will not be described in detail again.

[0106] In some embodiments, the compensation erase voltage V is determined. era Then, the compensation erase voltage V can be applied. era The compensation erase voltage V is stored in a register so that it can be directly read from the register during subsequent erase operations. eraThis allows for the execution of erase operations. In other words, it eliminates the need to perform the aforementioned step of determining the compensation value for the erase voltage before each erase operation. For a given memory block, the step of determining the compensation value for the erase voltage can be performed at intervals of a certain number of erase / write cycles. For example, the step of determining the compensation value for the erase voltage can be performed approximately every 500 erase / write cycles, allowing the compensation erase voltage to be determined based on the latest compensation value. When the range of the number of erase / write cycles is small, the range of the threshold voltage offset value of the target memory state is also small. Therefore, the same compensation erase voltage can be used for the memory block when the number of erase / write cycles is within the aforementioned range, eliminating the need to perform the step of determining the compensation value for the erase voltage before each erase operation, thereby further improving programming / erasing efficiency.

[0107] Figure 15a This is a schematic diagram illustrating another variation in the number of times an erase voltage is applied, as provided in an embodiment of this disclosure. (See diagram below.) Figure 15a As shown, the horizontal axis represents the number of erase / write cycles, and the vertical axis represents the number of erase voltages required for a complete erase operation. It should be noted that the number of erase voltages applied on the vertical axis is the average of multiple test results. Curve 1501 indicates the use of... Figure 6 The erase method shown illustrates the relationship between the number of erase voltage applications and the number of erase / write cycles during the erase operation; curve 1502 represents the relationship when using the erase method described above. Figure 13 The diagram illustrates the relationship between the number of erase voltage applications and the number of erase / write cycles during the erase operation of the memory. It can be seen that using... Figure 6 When erasing using the method shown, compared to a memory cell with 10,000 erase / write cycles, the number of erase voltages required for a complete erase operation of a memory cell with 100,000 erase / write cycles is increased by nearly two; while using... Figure 13 When performing an erase operation, the number of times the erase voltage is applied varies by the number of erase / write cycles, with the variation being minimal, generally not exceeding 1. Therefore, the memory operation method provided in this disclosure can effectively reduce the number of erase voltages required for the erase operation, improve erase efficiency, and thus enhance memory reliability.

[0108] Figure 15b Another schematic diagram of the erase time variation provided in this embodiment of the present disclosure, as shown below. Figure 15b As shown, the horizontal axis represents the number of erase / write cycles, and the vertical axis represents the erase time. It should be noted that the erase time indicated on the vertical axis is the average of multiple test results. Curve 1503 represents the method used... Figure 6The erase method shown illustrates the relationship between erase time and the number of erase / write cycles during the erase operation; curve 1504 represents the method used... Figure 13 The diagram illustrates the relationship between erase time and the number of erase / write cycles during an erase operation in the illustrated memory operation method. It can be seen that using... Figure 6 When erasing using the method shown, the erasure time for a memory cell with 100,000 erase / write cycles increases by approximately 3 ms compared to a memory cell with 10,000 erase / write cycles; while using... Figure 13 When performing an erase operation, the erase time varies very little with the number of erase / write cycles, generally not exceeding 2ms. Therefore, the memory operation method provided in this disclosure can effectively reduce erase time and improve erase efficiency.

[0109] Furthermore, in the memory operation method provided in this disclosure embodiment, the time required to determine the compensation value of the erase voltage and thus determine the compensated erase voltage is much less than the time required in the conventional method to increase the erase voltage once and perform the erase operation. For example, Figure 6 The process of increasing the erase voltage and performing the erase operation takes approximately 1 ms, while... Figure 13 The process of increasing the read voltage, performing the read operation, and obtaining the verification error bit count, as shown, takes only about 35µs. Therefore, this disclosure can reduce erase time and improve erase efficiency.

[0110] This disclosure also provides a memory, such as... Figure 3 As shown, the memory 300 includes a memory cell array 301 and peripheral circuitry 302. The memory cell array 301 includes multiple memory cells; each memory cell has any one of multiple memory states; the peripheral circuitry 302 is coupled to the memory cell array 301.

[0111] The peripheral circuit 302 is configured to: detect the threshold voltage offset value of the target storage state among multiple storage states; and determine the compensation value of the erase voltage corresponding to the target storage state based on the threshold voltage offset value of the target storage state.

[0112] In some embodiments, the peripheral circuit 302 is specifically configured to: perform a read operation on a plurality of target memory cells based on the read voltage to obtain a verification error bit count; determine the number of conducting memory cells based on the verification error bit count; the conducting memory cells are memory cells among the plurality of target memory cells whose threshold voltage is less than the read voltage; and determine the actual threshold voltage of the target memory state based on the number of conducting memory cells.

[0113] In some embodiments, the peripheral circuit 302 is specifically configured to: in response to the number of activated memory cells being less than a preset value, gradually increase the read voltage by a step size until the number of activated memory cells is greater than or equal to the preset value; and in response to the number of activated memory cells being greater than or equal to the preset value, determine the actual threshold voltage of the target storage state based on the current read voltage.

[0114] In some embodiments, the peripheral circuit 302 is specifically configured to: determine the threshold voltage offset value of the target storage state based on the difference between the current read voltage and the initial read voltage of the target storage state; the initial read voltage is the minimum value of the theoretical threshold voltage of the target storage state.

[0115] In some embodiments, the peripheral circuit 302 is specifically configured to: determine the compensation value of the erase voltage corresponding to the target storage state based on the difference between the current read voltage and the initial read voltage of the target storage state.

[0116] In some embodiments, the ratio of the erase voltage compensation value to the difference between the current read voltage and the initial read voltage ranges from 0.8 to 1.2.

[0117] In some embodiments, the peripheral circuit 302 is further configured to apply a preprogramming voltage to a plurality of target memory cells to perform a preprogramming operation before detecting a threshold voltage offset value of a target memory state among a plurality of memory states.

[0118] In some embodiments, the target storage state is erased before the pre-programming operation.

[0119] In some embodiments, the peripheral circuit 302 is further configured to: determine a compensated erase voltage based on the initial erase voltage and a compensation value for the erase voltage; and perform an erase operation based on the compensated erase voltage.

[0120] This disclosure also provides an electronic device, which includes, as described above, Figure 1 The memory system shown.

[0121] In some embodiments, the above-mentioned electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted device, wearable device, and power bank.

[0122] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0123] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0124] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for operating a memory, characterized in that, The memory includes a memory cell array and peripheral circuitry; The storage cell array includes multiple storage cells, each storage cell having any one of multiple storage states; the method includes: The system performs read operations on multiple target memory cells based on the read voltage to obtain the count of verification error bits. The number of conducting memory cells is determined based on the verification error bit count; the conducting memory cells are memory cells among the plurality of target memory cells whose threshold voltage is less than the read voltage; Based on the number of the conducting memory cells, determine the actual threshold voltage of the target memory state among the plurality of memory states; The threshold voltage offset value of the target storage state is determined based on the actual threshold voltage of the target storage state; Based on the threshold voltage offset value of the target storage state, determine the compensation value of the erase voltage corresponding to the target storage state.

2. The method for operating the memory according to claim 1, characterized in that, Determining the actual threshold voltage of the target storage state among the plurality of storage states based on the number of the conducting storage cells includes: In response to the number of the conducting memory cells being less than a preset value, the read voltage is gradually increased by a first step length until the number of the conducting memory cells is greater than or equal to the preset value; In response to the number of the conducting memory cells being greater than or equal to the preset value, the actual threshold voltage of the target memory state is determined based on the current read voltage.

3. The method for operating the memory according to claim 2, characterized in that, Determining the threshold voltage offset value of the target storage state based on the actual threshold voltage of the target storage state includes: The threshold voltage offset value of the target storage state is determined based on the difference between the current read voltage and the initial read voltage of the target storage state; the initial read voltage is the minimum value of the theoretical threshold voltage of the target storage state.

4. The method for operating the memory according to claim 3, characterized in that, The step of determining the compensation value of the erase voltage corresponding to the target storage state based on the threshold voltage offset value of the target storage state includes: The compensation value for the erase voltage corresponding to the target storage state is determined based on the difference between the current read voltage and the initial read voltage of the target storage state.

5. The method for operating the memory according to claim 4, characterized in that, The ratio of the compensation value of the erase voltage to the difference between the current read voltage and the initial read voltage ranges from 0.8 to 1.

2.

6. The method for operating the memory according to claim 1, characterized in that, Before performing the read operation on multiple target memory cells based on the read voltage, the method further includes: A pre-programming voltage is applied to the plurality of target memory cells to perform a pre-programming operation.

7. The method of operating the memory according to claim 6, characterized in that, Prior to the pre-programming operation, the target storage state is an erased state.

8. The method of operating the memory according to claim 1, characterized in that, The method further includes: The compensated erase voltage is determined based on the initial erase voltage and the compensation value of the erase voltage; The erasure operation is performed based on the compensated erasure voltage.

9. A memory, characterized in that, The memory includes: A storage cell array, the storage cell array comprising a plurality of storage cells; each storage cell having any one of a plurality of storage states; Peripheral circuitry coupled to the memory cell array; the peripheral circuitry is configured to: The system performs read operations on multiple target memory cells based on the read voltage to obtain the count of verification error bits. The number of conducting memory cells is determined based on the verification error bit count; the conducting memory cells are memory cells among the plurality of target memory cells whose threshold voltage is less than the read voltage; Based on the number of the conducting memory cells, determine the actual threshold voltage of the target memory state among the plurality of memory states; The threshold voltage offset value of the target storage state is determined based on the actual threshold voltage of the target storage state; Based on the threshold voltage offset value of the target storage state, determine the compensation value of the erase voltage corresponding to the target storage state.

10. The memory according to claim 9, characterized in that, The peripheral circuit is specifically configured as follows: In response to the number of the conducting memory cells being less than a preset value, the read voltage is gradually increased by a first step length until the number of the conducting memory cells is greater than or equal to the preset value; In response to the number of the conducting memory cells being greater than or equal to the preset value, the actual threshold voltage of the target memory state is determined based on the current read voltage.

11. The memory according to claim 10, characterized in that, The peripheral circuit is specifically configured as follows: The threshold voltage offset value of the target storage state is determined based on the difference between the current read voltage and the initial read voltage of the target storage state; the initial read voltage is the minimum value of the theoretical threshold voltage of the target storage state.

12. The memory according to claim 11, characterized in that, The peripheral circuit is specifically configured as follows: The compensation value for the erase voltage corresponding to the target storage state is determined based on the difference between the current read voltage and the initial read voltage of the target storage state.

13. The memory according to claim 12, characterized in that, The ratio of the compensation value of the erase voltage to the difference between the current read voltage and the initial read voltage ranges from 0.8 to 1.

2.

14. The memory according to claim 9, characterized in that, The peripheral circuit is also configured to: Before performing read operations on the multiple target memory cells based on the read voltage, a pre-programming voltage is applied to the multiple target memory cells to perform a pre-programming operation.

15. The memory according to claim 14, characterized in that, Prior to the pre-programming operation, the target storage state is an erased state.

16. The memory according to claim 9, characterized in that, The peripheral circuit is also configured to: The compensated erase voltage is determined based on the initial erase voltage and the compensation value of the erase voltage; The erasure operation is performed based on the compensated erasure voltage.

17. A memory system, characterized in that, The memory system includes: At least one memory as claimed in any one of claims 9 to 16; and a controller coupled to said memory.

18. An electronic device, characterized in that, The electronic device includes the memory system as described in claim 17.

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