Semiconductor structure and manufacturing method thereof, and display panel
Through the double exposure process, the mountain spacer is formed and combined with the design of the metal trace layer, the problem of difficult to reduce the resolution cycle of the semiconductor structure is solved, and a display panel with higher resolution capabilities and a narrow border with high PPI is achieved.
Patent Information
- Application Number
- CN202210837410.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-15
- Publication Date
- 2025-04-25
- Estimated Expiration
- 2042-07-15
AI Technical Summary
In the prior art, the analytical period of a semiconductor structure is difficult to reduce, due to equipment accuracy and material limitations.
The first spacer portion in a mountain shape is formed by a double exposure process, and combined with the design of the metal trace layer, the spacer portion is thinned to reduce the actual analytical period of the photoresist layer.
Without changing the existing exposure systems and materials, the resolution cycle of the semiconductor structure is successfully reduced, the analysis capability is improved, and the display panel with narrow bezels and high PPI is realized.
Smart Images
Figure CN115206783B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof, and a display panel. Background Art
[0002] In the prior art, an exposure and development process is generally used to form a semiconductor structure. Specifically, the method for manufacturing a semiconductor structure includes: forming a photoresist layer on a substrate, using a mask as a mask, and using an exposure system to expose the photoresist layer, and then removing part of the photoresist layer by a developer to obtain a patterned photoresist layer. In this manufacturing method, the spacing between two adjacent mask strips of the mask and the width of each mask strip are aμm, and correspondingly, the resolution capability of the exposure system for the photoresist layer, the line width of the photoresist layer, and the line spacing of the photoresist layer are all aμm, and the resolution period of the photoresist layer is 2aμm. Since the a value is limited by the equipment, it is difficult to reduce the resolution period of the photoresist layer. Summary of the invention
[0003] In view of this, the present application provides a semiconductor structure and a manufacturing method thereof, and a display panel that can reduce the analysis cycle without changing the existing exposure system and materials.
[0004] To solve the above problems, the technical solutions provided by this application are as follows:
[0005] In a first aspect, the present application provides a semiconductor structure, comprising:
[0006] substrate;
[0007] A photoresist layer is formed on the substrate; the photoresist layer includes a plurality of spacers, and two adjacent spacers are separated by a spacer groove; the spacer includes a first side surface and a second side surface, and one end of the first side surface and the second side surface are connected to the substrate, and the first side surface and the second side surface are arranged opposite to each other; the first side surface of one spacer and the second side surface of another spacer adjacent to the spacer are side walls of the spacer groove, and the substrate exposed from the spacer groove is the bottom wall of the spacer groove; and
[0008] The metal wiring layer includes a plurality of metal wirings; one of the metal wirings is located opposite to one of the spacing grooves, and the metal wirings are formed on the bottom wall and the side wall of one of the spacing grooves;
[0009] The dimension of one end of one of the spacers in contact with the substrate is larger than the dimension of one end of the spacer away from the substrate.
[0010] In an optional embodiment of the present application, the spacer portion further includes a first surface facing away from the substrate, the first surface connects the first side surface and the second side surface, and a size of the first surface is greater than 0.
[0011] In an optional embodiment of the present application, the first surface is flush with an end of the metal trace located on the first side surface and the second side surface away from the substrate.
[0012] In an optional embodiment of the present application, the second side surfaces of two adjacent spacers intersect with the substrate at a first boundary line and a second boundary line respectively; the distance between the first boundary line and the second boundary line is defined as d1, the spacing between the ends of two metal traces located on the first side surface and the second side surface of the same spacer and away from the substrate is defined as the line spacing d2 of the metal traces, and the spacing between the ends of a metal trace located on the first side surfaces of two adjacent spacers and away from the substrate is defined as the line width d3 of the metal trace, and d1, d2 and d3 satisfy: d1=1 / 2(a+b), d2<1 / 2(ba), d3>a; wherein a is the spacing between two adjacent mask strips of the mask for making the photoresist layer, b is the width of the mask for making the photoresist layer, b>a, b>0, a>0.
[0013] In an optional embodiment of the present application, d1, d2 and d3 also satisfy: d2+d3>d1.
[0014] In an optional embodiment of the present application, the distance between the ends of the second side surfaces of two adjacent spacers away from the substrate is defined as the resolution period d4 of the photoresist layer, and d4 satisfies: d4<1 / 2(a+b).
[0015] In an optional embodiment of the present application, the material of the photoresist layer is positive photoresist.
[0016] In an optional embodiment of the present application, the first side surface and the second side surface of the spacing portion are arc surfaces.
[0017] A second aspect of the present application provides a method for manufacturing a semiconductor structure, comprising:
[0018] Providing a substrate and forming a first photoresist layer on the substrate;
[0019] The first photoresist layer is patterned by a double exposure process to obtain a second photoresist layer; the second photoresist layer comprises a plurality of first spacers, two adjacent first spacers are separated by a spacer groove, and a size of an end of the first spacer in contact with the substrate is larger than a size of an end of the first spacer away from the substrate;
[0020] forming a metal layer on the second photoresist layer;
[0021] forming a third photoresist layer on the metal layer;
[0022] removing a portion of the third photoresist layer and removing the first spacer exposed outside the remaining third photoresist layer; and
[0023] removing the remaining third photoresist layer to thin the first spacer to obtain the semiconductor structure;
[0024] The remaining first spacer is a spacer, the remaining second photoresist layer is a photoresist layer, and the remaining metal layer is a metal wiring layer, and the metal wiring layer includes a plurality of metal wirings.
[0025] In an optional embodiment of the present application, the double exposure process is to perform two exposures on the first photoresist layer in succession, and the same mask is used for the two exposures;
[0026] Removing a portion of the third photoresist layer through an exposure and development process or an ashing process;
[0027] The exposure level of the exposure and development process is lower than the exposure level of the double exposure process.
[0028] A third aspect of the present application provides a display panel, including a display portion, the display panel further comprising the semiconductor structure as described above, the display portion being formed on the substrate of the semiconductor structure.
[0029] The semiconductor structure and its manufacturing method and display panel provided by the present application first form a second photoresist layer through a double exposure process, the second photoresist layer includes a plurality of first spacers in a mountain shape (the size of the end of the first spacer in contact with the substrate is larger than the size of the end of the first spacer away from the substrate), then a metal coating is coated on the second photoresist layer and a third photoresist layer is coated on the metal coating, and then a portion of the third photoresist layer is removed, the first spacer exposed outside the third photoresist layer is removed, and the remaining third photoresist layer is removed to thin the first spacer and obtain a semiconductor structure. The width of the end of the first spacer in the obtained second photoresist layer that is in contact with the substrate is the line width of the first spacer, and the line width of the first spacer is equal to 1 / 2 (ba), the resolution capability of the exposure system for the photoresist layer is equal to a, and the resolution period of the first spacer is equal to 1 / 2 (a+b). Because the value of a is limited by the accuracy capability of the equipment and depends on the equipment, the value of a does not change without changing the equipment. If you want to reduce the resolution period, you need to reduce the b value. Reducing the b value will lead to a reduction in 1 / 2 (ba). Due to the equipment alignment accuracy and subsequent process requirements, 1 / 2 (ba) has a minimum value requirement. Since the size of the end of the first spacer that contacts the substrate is larger than the size of the end of the first spacer that is away from the substrate, thinning the first spacer can reduce the actual "a value" of the photoresist layer (the distance between the ends of adjacent first spacers away from the substrate), so that 1 / 2 (b-"a") increases, thereby providing space for reducing the b value, so as to reduce the resolution period of the spacer of the semiconductor structure from the source by reducing the width of each mask strip of the mask (i.e., b). BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.
[0031] Figure 1 A flowchart of a method for manufacturing a semiconductor structure provided in a preferred embodiment of the present application.
[0032] Figure 2 A cross-sectional view of a substrate with a first photoresist layer provided in the present application.
[0033] Figure 3 For the general Figure 2 The cross-sectional view of the first photoresist layer after being patterned into the second photoresist layer is shown.
[0034] Figure 4 A cross-sectional view of a mask provided in this application.
[0035] Figure 5 For Figure 3 A cross-sectional view after a metal layer is formed on the second photoresist layer is shown.
[0036] Figure 6 For Figure 5 A cross-sectional view after a third photoresist layer is formed on the metal layer is shown.
[0037] Figure 7 To remove Figure 6 A cross-sectional view of a portion of the third photoresist layer is shown.
[0038] Figure 8 To remove Figure 7 A cross-sectional view showing the first spacer exposed outside the remaining third photoresist layer.
[0039] Fig. 9 To remove Figure 8 The remaining third photoresist layer is shown to thin the first spacer to obtain a cross-sectional view of the semiconductor structure.
[0040] Fig.10 for Fig. 9 A scanning electron microscope image of the semiconductor structure is shown.
[0041] Fig.11 A schematic diagram of a module of a display panel provided in the present application. DETAILED DESCRIPTION
[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0043] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0044] The present application may repeat reference numerals and / or reference letters in different implementations. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.
[0045] The hybrid display device, the method for manufacturing the hybrid display device and the display terminal provided by the present application will be described in detail below in conjunction with specific embodiments and drawings.
[0046] See also Figure 1-10 A preferred embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:
[0047] Step S1: Please refer to Figure 1-2 , providing a substrate 10 and forming a first photoresist layer 20 on the substrate 10 .
[0048] The substrate 10 may be a substrate that simply plays a supporting role, or may be a substrate with circuit traces and the like.
[0049] The material of the first photoresist layer 20 is preferably high temperature resistant organic photoresist.
[0050] The first photoresist layer 20 may be a positive photoresist or a negative photoresist. Since it is difficult for negative photoresist to form a spacing portion with a smaller line pitch, the present application preferably uses positive photoresist as the first photoresist layer 20 .
[0051] Step S2: Please refer to Figure 1 , Figure 3 and Figure 4 , the first photoresist layer 20 is patterned by a double exposure process to obtain a second photoresist layer 30; the second photoresist layer 30 includes a plurality of first spacers 31, two adjacent first spacers 31 are separated by a spacer groove 32, and the size of one end of the first spacer 31 in contact with the substrate 10 is larger than the size of the end of the first spacer 31 away from the substrate 10.
[0052] The first partition 31 is in a mountain-shaped structure. Preferably, one end of the first partition 31 away from the base 10 is a pointed end.
[0053] In this embodiment, the double exposure process is to perform two exposures on the first photoresist layer 20 continuously, and the same mask 40 can be used for the two exposures. In the second exposure, the mask 40 used in the first exposure is flipped 180° as a mask for the second exposure.
[0054] The mask plate 40 includes a plurality of mask strips 41, which are arranged at intervals. The width of each mask strip 41 in a direction perpendicular to the extension direction of the mask strip 41 is b, and the spacing between two adjacent mask strips 41 is a, then b>a, b>0 and a>0.
[0055] The distance between the tips of two adjacent first spacers 31 is a, and the size of the end of the first spacer 31 in contact with the substrate 10 is 1 / 2 (a+b).
[0056] In an optional embodiment of the present application, the units of a and b are micrometers (μm).
[0057] Specifically, the first spacer 31 includes two side surfaces 311. One end of the two side surfaces 311 is connected to the base 10, and the other ends thereof intersect at a point to form a tip.
[0058] Step S3: Please refer to Figure 1 and Figure 5 , a metal layer 50 is formed on the second photoresist layer 30 .
[0059] Specifically, the metal layer 50 is formed on the two side surfaces 311 and the substrate 10 connecting the two oppositely disposed side surfaces 311 of two adjacent first spacers 31 .
[0060] Step S4: Please refer to Figure 1 and Figure 6 , forming a third photoresist layer 60 on the metal layer 50 .
[0061] The third photoresist layer 60 is a temporary protective layer. Preferably, the third photoresist layer 60 is a positive photoresist of a normal array.
[0062] Step S5: Please refer to Figure 1 and Figure 7-8 , a portion of the third photoresist layer 60 is removed through an exposure and development process or an ashing process, and the first spacer 31 exposed outside the remaining third photoresist layer 60 is removed.
[0063] Specifically, the exposure level of the exposure and development process is lower than the exposure level of the double exposure process, which is weak exposure.
[0064] The first spacer 31 exposed outside the remaining third photoresist layer 60 may be removed by mechanical grinding or chemical etching.
[0065] Step S6: Please refer to Figure 1 and Figure 9-10, removing the remaining third photoresist layer 60 to thin the first spacer 31, and obtaining the semiconductor structure 100. The remaining first spacer 31 is a spacer 71, the remaining second photoresist layer 30 is a photoresist layer 70, and the remaining metal layer 50 is a metal wiring layer 80, and the metal wiring layer 80 includes a plurality of metal wirings 81.
[0066] Among them, the spacer 71 includes a first surface 711 facing away from the substrate 10 and a first side surface 712 and a second side surface 713 connecting the first surface 711 and the substrate 10, and the first side surface 712 is arranged opposite to the second side surface 713; the first side surface 712 of one spacer 71 and the second side surface 713 of another spacer 71 adjacent to the spacer 71 are side walls of the spacer groove 32, and the substrate 10 exposed from the spacer groove 32 is the bottom wall of the spacer groove 32; one of the metal traces 81 is opposite to one of the spacer grooves 32, and the metal trace 81 is formed on the bottom wall and the side wall of one of the spacer grooves 32.
[0067] Specifically, see Fig.10 The first side surface 712 and the second side surface 713 of the spacer 71 are arc surfaces. Specifically, the centers of the arc surfaces of the first side surface 712 and the second side surface 713 are located on both sides of the spacer 71 and away from the substrate 10 .
[0068] The second side surfaces 713 of two adjacent spacers 71 intersect with the substrate 10 at a first boundary line 714 and a second boundary line 715 respectively; the distance between the first boundary line 714 and the second boundary line 715 is defined as d1, the spacing between the ends of two metal traces 81 located on the first side surface 712 and the second side surface 713 of the same spacer 71 and away from the substrate 10 is defined as a line distance d2 of the metal traces 81, and the spacing between the ends of one metal trace 81 located on the first side surface 712 of two adjacent spacers 71 and away from the substrate 10 is defined as a line width d3 of the metal trace 81, and d1, d2 and d3 satisfy d1=1 / 2(a+b), d2<1 / 2(ba), d3>a; wherein a is the spacing between two adjacent mask strips of the mask used in the double exposure process, b is the width of the mask for making the photoresist layer, b>a, b>0, a>0. Among them, the mountain-shaped spacers 71 and metal routings can reduce the actual "a value" of the photoresist layer (i.e., the distance between the ends of adjacent first spacers away from the substrate) to increase 1 / 2 (b-"a"), providing space for the reduction of the b value, so as to reduce the resolution period of the spacers of the semiconductor structure from the source by reducing the width of each mask strip of the mask (i.e., b).
[0069] Among them, d1, d2 and d3 also satisfy: d2+d3>d1, the metal routing 81 is formed on the mountain-shaped spacer 71, and the sum of the line width d3 and the line spacing d2 of the metal routing 81 is greater than d1 (d1=1 / 2(a+b)), so that the metal routing 81 can be arranged in a 2D space, and the wiring space is greatly compressed, so that the corresponding display panel has a narrow border and a high PPI effect.
[0070] The distance between the ends of the second side surfaces 713 of two adjacent spacers 71 away from the substrate 10 is defined as the resolution period d4 of the photoresist layer 70 , and d4 satisfies: d4<1 / 2(a+b).
[0071] See also Fig. 9 and Fig.10The present application also provides a semiconductor structure 100, the semiconductor structure 100 includes a substrate 10, a photoresist layer 70 and a metal wiring layer 80, the photoresist layer 70 is formed on the substrate 10, the photoresist layer 70 includes a plurality of spacers 71, two adjacent spacers 71 are separated by a spacer groove 32; the spacer 71 includes a first surface 711 away from the substrate 10 and a first side surface 712 and a second side surface 713 connecting the first surface 711 and the substrate 10, the first side surface 712 and the second side surface 713 are arranged opposite to each other. The size of one end of the spacer 71 in contact with the substrate 10 is larger than the size of the first surface 711. The first side surface 712 of one spacer 71 and the second side surface 713 of another spacer 71 adjacent to the spacer 71 constitute the sidewalls of the spacer groove 32, and the substrate 10 exposed from the spacer groove 32 constitutes the bottom wall of the spacer groove 32. The metal wiring layer 80 includes a plurality of metal wirings 81 . One of the metal wirings 81 is located opposite to one of the spacing grooves 32 . The metal wiring 81 is formed on the bottom wall and the side wall of one of the spacing grooves 32 .
[0072] Specifically, please refer to Fig.10 The semiconductor structure 100 is shown in a scanning electron microscope image. The spacers 71 and the metal traces 81 are arranged in a mountain shape.
[0073] The second side surfaces 713 of two adjacent spacers 71 are defined to intersect with the substrate 10 at a first boundary line 714 and a second boundary line 715 respectively; the distance between the first boundary line 714 and the second boundary line 715 is defined to be d1; the spacing between the ends of two metal traces 81 located on the first side surface 712 and the second side surface 713 of the same spacer 71 and away from the substrate 10 is defined to be a line distance d2 of the metal traces 81; the spacing between the ends of one metal trace 81 located on the first side surface 712 of two adjacent spacers 71 and away from the substrate 10 is defined to be a line width d3 of the metal trace 81; d1, d2 and d3 satisfy d1=1 / 2(a+b), d2<1 / 2(ba), d3>a; wherein a is the spacing between two adjacent mask strips of the mask used in the double exposure process, b is the width of the mask for making the photoresist layer, b>a, b>0, a>0. Among them, the mountain-shaped spacers 71 and metal routings can reduce the actual "a value" of the photoresist layer (i.e., the distance between the ends of adjacent first spacers away from the substrate) to increase 1 / 2 (b-"a"), providing space for the reduction of the b value, so as to reduce the resolution period of the spacers of the semiconductor structure from the source by reducing the width of each mask strip of the mask (i.e., b).
[0074] Among them, d1, d2 and d3 also satisfy: d2+d3>d1, the metal routing 81 is formed on the mountain-shaped spacer 71, and the sum of the line width d3 and the line spacing d2 of the metal routing 81 is greater than d1 (d1=1 / 2(a+b)), so that the metal routing 81 can be arranged in a 2D space, and the wiring space is greatly compressed, so that the corresponding display panel has a narrow frame and a high PPI effect.
[0075] The distance between the ends of the second side surfaces 713 of two adjacent spacers 71 away from the substrate 10 is defined as the resolution period d4 of the photoresist layer 70 , and d4 satisfies: d4<1 / 2(a+b).
[0076] In an optional embodiment of the present application, the photoresist layer 70 is made of positive photoresist.
[0077] See also Fig.11 The present application also provides a display panel 1000 , wherein the display panel 1000 includes a display portion 200 and the semiconductor structure 100 , wherein the display portion 200 is formed on the substrate 10 of the semiconductor structure 100 .
[0078] In an optional embodiment of the present application, the metal routing 81 and the spacer 71 of the semiconductor structure 100 are located in the array substrate (not shown) of the display panel 1000. Specifically, the metal routing of the semiconductor structure 100 is located in the non-display area of the array substrate. The semiconductor structure 100 can reduce the border of the display panel 1000, which is conducive to achieving narrow-border display.
[0079] In another optional embodiment of the present application, the metal wiring of the semiconductor structure 100 may also be located at other locations of the display panel 1000 where metal wiring needs to be designed, and is not limited to the non-display area of the array substrate.
[0080] The semiconductor structure and its manufacturing method and display panel provided by the present application first form a second photoresist layer through a double exposure process, the second photoresist layer includes a plurality of first spacers in a mountain shape (the size of the end of the first spacer in contact with the substrate is larger than the size of the end of the first spacer away from the substrate), then a metal coating is coated on the second photoresist layer and a third photoresist layer is coated on the metal coating, and then a portion of the third photoresist layer is removed, the first spacer exposed outside the third photoresist layer is removed, and the remaining third photoresist layer is removed to thin the first spacer and obtain a semiconductor structure. The width of the end of the first spacer in the obtained second photoresist layer that is in contact with the substrate is the line width of the first spacer, and the line width of the first spacer is equal to 1 / 2 (ba), the resolution capability of the exposure system for the photoresist layer is equal to a, and the resolution period of the first spacer is equal to 1 / 2 (a+b). Because the value of a is limited by the accuracy capability of the equipment and depends on the equipment, the value of a does not change without changing the equipment. If you want to reduce the resolution period, you need to reduce the b value. Reducing the b value will lead to a reduction in 1 / 2 (ba). Due to the equipment alignment accuracy and subsequent process requirements, 1 / 2 (ba) has a minimum value requirement. Since the size of the end of the first spacer that contacts the substrate is larger than the size of the end of the first spacer that is away from the substrate, thinning the first spacer can reduce the actual "a value" of the photoresist layer (the distance between the ends of adjacent first spacers away from the substrate), so that 1 / 2 (b-"a") increases, thereby providing space for reducing the b value, so as to reduce the resolution period of the spacer of the semiconductor structure from the source by reducing the width of each mask strip of the mask (i.e., b).
[0081] In addition, since thinning the first spacer can reduce the actual "a value" of the photoresist layer (the distance between the ends of adjacent first spacers away from the substrate), the resolution capability of the semiconductor structure of the present invention can be improved.
[0082] In addition, since the size of the end of the first spacer (or spacer) in contact with the substrate is larger than the size of the end of the first spacer away from the substrate, the line spacing between the metal traces in this case is reduced and the line width is increased, thereby achieving the technical effect that the sum of the line width and the line spacing is greater than the resolution period of the second photoresist layer formed after double exposure.
[0083] In addition, the metal routing is formed on the first mountain-shaped spacer (or spacer), and the line width + line spacing is greater than d1, so that the metal routing can arrange the metal lines in the 2D space, and the wiring space is greatly compressed, so that the corresponding display panel has a narrow border and a high PPI effect.
[0084] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that: include: substrate; A photoresist layer is formed on the substrate; the photoresist layer comprises a plurality of spacers, and two adjacent spacers are separated by a spacer groove; the spacer comprises a first side surface and a second side surface, one end of the first side surface and the second side surface are connected to the substrate, and the first side surface and the second side surface are arranged opposite to each other; the first side surface of one spacer and the second side surface of another spacer adjacent to the spacer are side walls of the spacer groove, and the substrate exposed from the spacer groove is the bottom wall of the spacer groove; and The metal wiring layer includes a plurality of metal wirings; one of the metal wirings is located opposite to one of the spacing grooves, and the metal wirings are formed on the bottom wall and the side wall of one of the spacing grooves; The dimension of one end of one of the spacers in contact with the substrate is larger than the dimension of one end of the spacer away from the substrate.
2. The semiconductor structure according to claim 1, wherein: The spacer also includes a first surface facing away from the substrate, the first surface connects the first side surface and the second side surface, and a size of the first surface is greater than 0.
3. The semiconductor structure according to claim 2, wherein: The first surface is flush with an end of the metal trace located on the first side surface and the second side surface away from the substrate.
4. The semiconductor structure according to claim 1, wherein: The second side surfaces of two adjacent spacers intersect with the substrate at a first boundary line and a second boundary line, respectively. The distance between the first boundary line and the second boundary line is defined as d1. The spacing between the ends of two metal traces located on the first side surface and the second side surface of the same spacer and away from the substrate is defined as the line distance d2 of the metal traces. The spacing between the ends of a metal trace located on the first side surfaces of two adjacent spacers and away from the substrate is defined as the line width d3 of the metal trace. The d1, d2 and d3 satisfy: d1=1 / 2(a+b), d2<1 / 2(ba), d3>a; Wherein, a is the distance between two adjacent mask strips of the mask for making the photoresist layer, b is the width of the mask for making the photoresist layer, b>a, b>0, a>0.
5. The semiconductor structure according to claim 4, characterized in that The d1, d2 and d3 also satisfy: d2+d3>d1.
6. The semiconductor structure according to claim 5, characterized in that The distance between the ends of the second side surfaces of two adjacent spacing portions that are away from the substrate is defined as the resolution period d4 of the photoresist layer, and the d4 satisfies: d4<1 / 2(a+b).
7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The material of the photoresist layer is positive photoresist.
8. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The first side surface and the second side surface of the spacing portion are arc surfaces.
9. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate and forming a first photoresist layer on the substrate; Patterning the first photoresist layer through a double exposure process to obtain a second photoresist layer; The second photoresist layer comprises a plurality of first spacers, two adjacent first spacers are separated by a spacer groove, and the size of one end of the first spacer in contact with the substrate is larger than the size of one end of the first spacer away from the substrate; forming a metal layer on the second photoresist layer; forming a third photoresist layer on the metal layer; removing a portion of the third photoresist layer and removing the first spacer exposed outside the remaining third photoresist layer; and removing the remaining third photoresist layer through an exposure and development process or an ashing process to thin the first spacer to obtain the semiconductor structure; The remaining first spacer is a spacer, the remaining second photoresist layer is a photoresist layer, and the remaining metal layer is a metal wiring layer, and the metal wiring layer includes a plurality of metal wirings.
10. A display panel, comprising a display portion, characterized in that: The display panel further comprises a semiconductor structure as claimed in any one of claims 1 to 8, and the display portion is formed on the substrate of the semiconductor structure.
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