Trench memory bit erasable embedded select

Abstract

The present disclosure relates to bit-erasable embedded select in trench memory. In an embodiment, a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second well and the fourth well, the first wall including a conductive or semiconductive core and an insulating sheath, a stack of layers including a first insulating layer at least partially covering the second well and the fourth well, a first semiconductive layer, a second insulating layer, and a second semiconductive layer, and a third semiconductive layer underlying the second well and the fourth well and the first wall.

Description

[0001] Cross Reference to Related Applications

[0002] This application is a translation of French Patent Application No. "FR2103797", filed on April 13, 2021, entitled "Cellule mémoire programmable et " and claiming priority thereto, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to electronic devices, and more specifically, to memory devices, methods of manufacturing thereof, and methods of using thereof. BACKGROUND

[0004] There are many types of memory cells. In particular, there are memory cells known as eSTM (embedded Select in Trench Memory). eSTM type memory cells are re- writable memory cells commonly used in flash type memory circuits.

[0005] eSTM memory cells are arranged in an array forming rows and columns. Cells of the same row are coupled together through connection elements corresponding to bit lines. Cells of the same column are coupled together through connection elements corresponding to word lines. Cells of the array can be programmed and read on a bit by bit basis (i.e. cell by cell). However, eSTM cells are erased on a row by row basis. SUMMARY

[0006] Embodiments provide an eSTM type memory cell that can be erased on a bit by bit basis.

[0007] Embodiments provide an eSTM type memory cell that can be erased faster.

[0008] Embodiments provide an eSTM type memory cell that is more reliable.

[0009] Embodiments provide an eSTM type memory cell that can be controlled by a lower voltage than known eSTM type memory cells.

[0010] Various embodiments overcome all or part of the shortcomings of known eSTM type memory cells.

[0011] In one embodiment, a memory cell comprises:

[0012] a first doped well of a first conductivity type, in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type;

[0013] a third doped well of the second conductivity type, in contact with a fourth doped well of the first conductivity type;

[0014] a first wall in contact with the second and fourth wells, the first wall comprising a conductive or semiconductive core and an insulating sheath;

[0015] a stack of layers comprising a first insulating layer, a first semiconductive layer, a second insulating layer and a second semiconductive layer at least partially covering the second and fourth wells; and

[0016] a third semiconductive layer having the second and fourth wells and a wall thereon.

[0017] According to one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0018] According to one embodiment, the second and fourth wells are separated by a first conductive wall.

[0019] According to one embodiment, the stack of layers covers the first wall.

[0020] According to one embodiment, the third layer is separated from the fourth well by a second conductivity type doped semiconductive well.

[0021] According to one embodiment, the second and fourth wells are separated by a second insulating wall.

[0022] According to one embodiment, the stack of layers covers the second wall.

[0023] Another embodiment provides a memory comprising an array of memory cells as previously described, wherein each column of the array comprises a second semiconductive layer and a first wall common to the cells of the column.

[0024] In another embodiment, a method for controlling a memory cell such as previously described, comprises a programming step during which:

[0025] the second, third and fourth wells and the third layer are at a first reference potential;

[0026] the first well is set to a second positive potential greater than the first reference potential;

[0027] the second layer is set to a third positive potential greater than the second positive potential; and

[0028] the first wall is set to a fourth potential equal to a threshold voltage of a transistor equivalent to the first, second and third wells and the stack of layers.

[0029] According to one embodiment, the first reference potential is ground, the second positive potential is substantially equal to 5V, the third potential is substantially equal to 12V and the fourth potential is in the range from 0.5V to 1.5V.

[0030] Another embodiment provides a method of controlling a memory cell as previously described, comprising a readout step, during which:

[0031] The second, third and fourth wells and the second and third semiconductor layers are at a fifth reference potential;

[0032] The first well is set to a sixth positive potential greater than the fifth reference potential;

[0033] The first wall is set to a seventh positive potential greater than the sixth positive potential.

[0034] According to one embodiment, the fifth reference potential is ground, the sixth positive potential is substantially equal to 0.7 V and the seventh positive potential is substantially equal to 3 V.

[0035] In yet another embodiment, a method for controlling a memory cell as previously described, comprising an erase step, during which:

[0036] The first, second and third wells and the third layer are at an eighth reference potential;

[0037] The fourth well is set to a ninth potential less than the eighth reference potential; the second semiconductor layer is set to a tenth potential less than the ninth potential; and

[0038] The first wall is set to an eleventh potential equal to the threshold voltage of a transistor equivalent to the stack of the second, third and fourth wells and the layer.

[0039] According to one embodiment, the eighth reference potential is ground, the ninth potential is substantially equal to -5 V, the tenth potential is substantially equal to -10 V and the eleventh potential is in the range from -1.5 V to -0.5 V.

[0040] According to one embodiment, the eighth reference potential is substantially equal to 10 V, the ninth potential is substantially equal to 5 V, the tenth potential is ground and the eleventh potential is in the range from 5 V to 15 V.

[0041] According to one embodiment, the eighth reference potential is substantially equal to 5 V, the ninth potential is ground, the tenth potential is substantially equal to -5 V and the eleventh potential is in the range from 0 V to 10 V.

[0042] According to one embodiment, the programming step and the erase step have substantially the same duration.

[0043] In some embodiments, a method for manufacturing a memory cell such as previously described comprises:

[0044] a. forming a third semiconductor layer by implanting dopants into a semiconductor substrate;

[0045] b. forming a second well by implanting dopants in the substrate;

[0046] c. forming a fourth well by implanting dopants in the substrate;

[0047] d. forming a first wall between the second well and the third well;

[0048] e. forming a stack on a portion of the second well and the fourth well and on the first wall;

[0049] f. forming a first well by implanting dopants into the second well; and

[0050] g. forming a third well by implanting dopants in the fourth well.

[0051] Another embodiment provides a method of fabricating a first memory cell such as previously described and a second memory cell of the eSTM type, wherein the first memory cell is formed by steps a, b, c, d, e, f, and g of the method such as previously described, and the second memory cell is formed by steps a, b, d, e, f.

[0052] Another embodiment provides a method of fabricating a first memory cell such as previously described and a transistor, wherein the first cell is formed by the method previously described, and the gate of the transistor is formed by step e, and the drain and source regions are formed by step f or G.

[0053] Another embodiment provides a method of fabricating a first memory cell such as previously described, a transistor, and a second memory cell of the eSTM type, wherein the first cell is formed by the method previously described, the second cell is formed by the method previously described, and the transistor is formed by the method previously described. BRIEF DESCRIPTION OF DRAWINGS

[0054] The above features and advantages and other will be described in detail below with reference to specific embodiments given by way of illustration and not limitation, in which:

[0055] Figure 1 Views A, B, C, and D showing embodiments of memory cells;

[0056] Figure 2 Steps of programming a cell of Figure 1 are illustrated;

[0057] Figure 3 Steps of reading from a cell of Figure 1 are illustrated;

[0058] Figure 4 Views A, B, and C showing different examples of erase steps for a cell of Figure 1 are illustrated;

[0059] Figure 5Another embodiment of a memory cell is shown;

[0060] Figure 6 Views A, B, C and D of another embodiment of a memory cell are shown;

[0061] Figure 7 Steps of a method for manufacturing an embodiment of Figure 1 are shown;

[0062] Figure 8 Another step of a method for manufacturing an embodiment of Figure 1 are shown;

[0063] Figure 9 Another step of a method for manufacturing an embodiment of Figure 1 are shown;

[0064] Figure 10 Another step of a method for manufacturing an embodiment of Figure 1 are shown; and

[0065] Figure 11 Another step of a method for manufacturing an embodiment of Figure 1 are shown. DETAILED DESCRIPTION

[0066] In different figures, the same features have been designated by the same references. In particular, structural and / or functional features common to the various embodiments can have the same references and can be provided with the same structural, dimensional and material properties.

[0067] For the sake of clarity, only the steps and elements useful for the understanding of the embodiments described herein have been specified and described in detail.

[0068] Unless otherwise stated, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, while when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled through one or more other elements.

[0069] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as the terms "front", "back", "upper", "lower", "left", "right", etc., or relative position qualifiers, such as the terms "upward", "downward", "upper portion", "lower portion", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., the orientation shown in the figures is intended.

[0070] Unless otherwise stated, "about", "approximately", "substantially" and "around" mean within 10%, preferably within 5%.

[0071] Figure 1Views A, B, C and D showing an embodiment of the memory cell 10. More precisely, Figure 1 comprises:

[0072] Cross-sectional view A along the plane A-A of view B and view C;

[0073] Top view B along the plane B-B of view A and view D;

[0074] Top view C along the plane C-C of view A and view D; and

[0075] Cross-sectional view D along the plane D-D of view B and view C.

[0076] The planes B-B and C-C are parallel to each other and orthogonal to the planes A-A and D-D. The plane A-A is orthogonal to the planes B-B, C-C and D-D. Similarly, the plane D-D is orthogonal to the planes A-A, B-B and C-C. The plane A-A corresponds to the direction of the bit lines of the array of identical or similar elementary cells. The plane D-D corresponds to the direction of the word lines of the array.

[0077] The memory cell 10 comprises a well 12. The well 12 is made of a semiconductor material, for example silicon. The well 12 is p-type doped. The well 12 is for example boron doped. The doping concentration in the well 12 ranges for example from 10 14 to 5xl0 15 at.cm"3.

[0078] The cell 10 further comprises a well 14. The well 14 is made of a semiconductor material, for example silicon. The well 14 is N-type doped. The well 14 is for example phosphorous doped. The doping concentration in the well 14 ranges for example from 10 14 to 5xl0 15 at.cm"3.

[0079] The cell 10 further comprises a wall 16 separating the well 12 and the well 14. The wall 16 comprises for example a core 16a, for example made of a metallic or semiconductor material, preferably polysilicon, and an insulating sheath 16b, for example made of silicon oxide, surrounding the core 16a. In particular, the insulating sheath 16b separates the core 16a from the well 12 and the well 14. The wall 16 is for example made of polysilicon. Preferably, the well 12 and the well 14 are completely separated by the wall 16. The wall 16 extends preferably at least along the entire height of the well 12 and the well 14. Thus, the well 12 and the well 14 are preferably not in contact with each other. The well 12 and the well 14 are preferably in contact with the wall 16.

[0080] Preferably, the wells 12 and 14 and the wall 16 have lower surfaces that are coplanar with each other. Preferably, the cell 10 includes a layer 18 having the lower surfaces of the wells 12 and 14 and the lower surface of the wall 16 located thereon. In this example, the lower surfaces of the wells 12 and 14 and the wall 16 are in contact with an upper surface of the layer 18. The layer 18 is preferably made of a semiconductor material, such as silicon, for example N-type doped silicon. The layer 18 is located on a P-type doped substrate 20. The substrate 20 is made of a semiconductor material, such as boron doped, for example.

[0081] The cell 10 includes a well 22 located on an upper portion of the well 12. The well 22 is made of a semiconductor material, such as silicon. The well 22 is N-type doped (N+). The well 22 is, for example, phosphorus doped. The doping concentration in the well 22 is greater than the doping concentration in the well 14. The doping concentration in the well 22 is in the range of 10 18 ~ 1020 at.cm^(-3), for example.

[0082] The well 22 is separated from the wall 16 by a portion of the well 12. In other words, a portion of the well 12 is located between the well 22 and the wall 16. Thus, the wall 16 and the well 22 are not in contact with each other. The well 22 extends from an upper surface of the well 12. The upper surface of the well 22 is preferably coplanar with the upper surface of the wall 16 and the upper surface of the portion of the well 12 located between the well 22 and the wall 16.

[0083] Similarly, the cell 10 includes a well 24 located on an upper portion of the well 14. The well 24 is made of a semiconductor material, such as silicon. The well 24 is P-type doped (P+). The well 24 is, for example, boron doped. The doping concentration in the well 24 is greater than the doping concentration in the well 12. The doping concentration in the well 24 is in the range of 10 18 ~ 10 20 at.cm^(-3), for example.

[0084] The well 24 is separated from the wall 16 by a portion of the well 14. In other words, a portion of the well 14 is located between the well 24 and the wall 16. Thus, the wall 16 and the well 24 are not in contact with each other. The well 24 extends from an upper surface of the well 14. The upper surface of the well 24 is preferably coplanar with the upper surface of the wall 16 and the upper surface of the portion of the well 14 located between the well 24 and the wall 16.

[0085] The plane C-C of view C shows the upper surfaces of the wells 12, 14, 22, 24 and the wall 16. In the plane C-C, the cell includes, from left to right, the well 22, the well 12, the wall 16, the well 14 and the well 24.

[0086] The N or P doping type of the well 12 is the opposite type as the doping type of the well 14. Similarly, the doping type of the well 22 is the opposite type as the doping type of the well 24. Furthermore, the doping type of the well 22 is the opposite type as the doping type of the well 12. The doping type of the well 24 is the opposite type as the doping type of the well 14. Thus, the well 22 and the well 14 have the same N or P doping type, and the well 24 and the well 12 have the same doping type.

[0087] Preferably, the dimensions of the well 12 and the well 14 are substantially the same. Similarly, the dimensions of the well 22 and the well 24 are substantially the same.

[0088] The cell 10 is separated from adjacent cells belonging to a different line by an insulating wall 25. The insulating wall 25 is for example made of silicon oxide. The insulating wall 25 preferably extends from the plane of the upper surfaces of the well 22 and the well 24, i.e. the plane C-C. The wall 25 preferably extends along the cell in the row direction. Thus, the wall 25 extends along the wells 22, 24, 12 and 14. The wall 25 preferably intersects the wall 16. Preferably, the wall 25 extends along a height which is smaller than the height of the wall 16, i.e. smaller than the distance between the plane C-C and the layer 18. Thus, the wall 25 preferably does not extend along the entire height of the wells 12 and 14. This enables the electrical connection of the well 12 and the well 14 of the cell 10 to an adjacent cell 10. The wall 25 is preferably separated from the layer 18 by a portion of the well 12 or the well 14. Preferably, the wall 25 extends along a height which is larger than the height of the well 22 and the well 24.

[0089] The cell 10 further comprises a stack of an insulating layer 27, a layer 26 made of for example a metallic or semiconducting material, e.g. polysilicon, an insulating layer 29, and a layer 28 made of for example a metallic or semiconducting material, e.g. polysilicon. Preferably, the layers 27 and 29 are made of different materials. For example, the layer 27 is made of silicon oxide, and the layer 29 is a stack of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer. Preferably, the layers 26 and 28 are made of the same material, e.g. polysilicon.

[0090] A layer 27 is on the upper surface of the wells 12, 14, 22 and 24. A layer 26 is on the layer 27. Preferably, the horizontal dimensions of the layer 26 are smaller than the horizontal dimensions of the layer 27, i.e. the smaller dimensions in the bit line and word line directions. Preferably, the layer 27 extends continuously over the upper surface of the wells 12 and 14 and at least partially over the upper surface of the wells 22 and 24. The layer 27 extends across the entire width of the wells 22 and 24 in the column direction. Preferably, the layer 27 extends from one of the walls 25, preferably from a side surface of one of the walls 25, to the other wall 25 of the cell, preferably all the way to a side surface of the other wall 25. The layer 27 preferably extends from the wall 16 in the array row direction. The layer 27 separates the layer 26 from the wells 12 and 14 and from the wall 16. Preferably, the layer 26 extends continuously in front of the entire upper surface of the wells 12 and 14. The layer 26 extends across the entire width of the wells 22 and 24 in the column direction. Preferably, the layer 26 extends from one of the walls 25 to the other wall 25 of the cell. The layer 26 preferably extends from the well 22 to the well 24 in the array row direction. Preferably, the layer 26 extends horizontally from the contact area between the wells 12 and 22 to the contact area between the wells 14 and 24. Preferably, the layer 26 does not extend in front of the wells 22 and 24.

[0091] The layer 29 preferably covers the layer 26 completely. Preferably, the layer 29 covers the upper surface of the layer 26 and the side surfaces of the layer 26, e.g. the side surfaces of the layer 26 in the array column direction. Preferably, the dimension of the layer 29 in the array row direction is substantially equal to the dimension of the layer 26 in the row direction.

[0092] The layer 28 preferably covers the layer 29 completely. The layer 28 is separated from the layer 26 by the layer 29. Preferably, the dimension of the layer 28 in the row direction is substantially equal to the dimension of the layer 26 in the row direction.

[0093] Preferably, the dimension of the layer 28 in the column direction is larger than the dimension of the layer 26 in the column direction. Preferably, the layer 28 is common to a plurality of cells of the same column, preferably to all cells of a column. Thus, the layer 28 preferably covers the layer 26 of a plurality of cells of the same column and covers the walls 25 separating the cells.

[0094] The cell further comprises contact elements 30 and 32, e.g. conductive vias. The elements 30 and 32 are e.g. made of metal. The element 30 is in contact with the well 22 and the element 32 is in contact with the well 24. The elements 30 and 32 are not in contact with the layers 26 and 28. The element 30 is preferably not in contact with the well 12. The element 32 is preferably not in contact with the well 14. The elements 30 and 32 are each coupled to a connection element forming a bit line.

[0095] The cell 10 is formed by two assemblies of two MOSFET (metal oxide semiconductor field effect transistor) transistors in series. One assembly comprises an N-channel transistor formed by the layer 18, the well 12 and the well 22, the layers 26, 27, 28 and 29, where the layers 26, 27, 28 and 29 form the gate. The other assembly comprises a P-channel transistor formed by the well 12, the well 14 and the well 24, the layers 26, 27, 28 and 29, where the layers 26, 27, 28 and 29 form the gate.

[0096] The layer 18 is preferably common to all memory cells of the type of the cell 10 in the same array of cells.

[0097] The wall 16 is preferably common to all cells of an array column. The wall 16 extends from one cell to the adjacent cell by crossing the insulating wall 25.

[0098] For example, a row of the array of cells comprises adjacent cells which are symmetrical to each other according to a symmetry plane parallel to the plane D-D, and which are for example located left of the view A. The well 12 and the well 22 then extend left in the view A to form a shape similar to the shape shown. Figure 1 Similarly, for example the well 24 and the well 14 are common to adjacent cells of the same row of the array which are located right of the view A.

[0099] Preferably, the wells 22 of the same row of the array are coupled together via the element 30 and possibly other connection elements (not shown). Similarly, the wells 24 of the same row of the array are coupled together via the element 32 and possibly other connection elements (not shown).

[0100] Furthermore, the well 12 and the well 14 are preferably common to all cells of an array column. The well 12 and the well 14 extend under the wall 25. For example, the well 12 and the well 14 are each coupled to a node for applying a voltage by an end-of-line contact.

[0101] Figure 2 A step of programming a cell of the type Figure 1 is shown. This is thus a step in which the memory cell is to be switched from a first binary value, for example the value 0, to a second binary value, for example the value 1.

[0102] During the programming of the cell 10, the well 12, the well 14 and the well 24 are set to the same reference potential GND, for example ground, i.e. a 0 V potential. The layer 18 is likewise set to the reference potential GND. The well 22 is set to a potential greater than the potential to which the layer 18 is set. The well 22 is preferably set to a positive potential, for example a potential in the range from 3 V to 10 V, for example substantially equal to 5 V. Furthermore, the layer 28 is set to a potential greater than the potential to which the well 22 is set. For example, the layer 28 is set to a potential in the range from 10 V to 15 V, for example substantially equal to 12 V.

[0103] The wall 16 is set to a potential substantially equal to the threshold voltage V TN of the transistor (i.e. P-channel transistor) formed by the well 12 and the well 22 and the layers 18, 26 and 28. The wall 16 is set to a potential capable of turning off the P-channel transistor of the cell. Thus, the wall 16 is set to a potential preferably in the range from 0.5 V to 1.5 V, preferably substantially equal to 1 V.

[0104] More generally, the different parts of the cell are set to potentials such that, during the programming of the cell 10, a current I1 is able to be formed between the layer 18 and the well 22 along the wall 16 and the layer 26, as shown by the arrow in Figure 2 The potentials of the well 22, the layer 28 and the layer 18 and the wall 16 are such that a hot carrier injection phenomenon occurs. Thus, the carriers, here the electrons e-, pass through the layer 27 into the layer 26 and remain trapped therein. This is shown by the arrow in Figure 2

[0105] Figure 3 The step of reading from the cell of Figure 1 is shown.

[0106] During this readout step, the well 12, the well 14 and the well 24 are set to the same reference potential GND, for example ground. The layer 18 is likewise set to the reference potential GND. The well 22 is set to a potential greater than the potential to which the layer 18 is set. The well 22 is preferably set to a positive potential, for example a potential in the range from 0 V to 1 V, for example substantially equal to 0.7 V. Furthermore, the layer 28 is set to a potential less than the potential to which the well 22 is set, preferably to the reference potential GND. The wall 16 is set to a potential greater than the potential to which the well 22 is set. For example, the wall 16 is set to a potential in the range from 1 V to 5 V.

[0107] More generally, during the readout step, the different parts of the cell are set such that:

[0108] If the programming step of trapping the carriers, here the electrons, in the layer 26 is not performed, and thus there are no carriers, here electrons, in the layer 26, a current I2 is formed between the layer 18 and the well 22, as shown by the arrow in Figure 3 ​as indicated by the arrow in the figure; and

[0109] If a carrier, here an electron, is trapped in the layer 26, no current is formed between the layer 18 and the well 22.

[0110] The binary data can thus be read. If a current is generated between the layer 18 and the well 22 during said reading step, the memory cell contains a first binary value, for example the value 0, and if no current is generated between the layer 18 and the well 22, the memory cell contains a second binary value, for example the value 1.

[0111] Figure 4 The views A, B and C are shown, illustrating different examples of steps of erasing Figure 1 a cell.

[0112] View A shows a first example of an erasing step of the cell 10. In this step, the well 12, the well 14 and the well 22 and the layer 18 are set to the reference potential GND. In addition, the layer 28 is set to a negative potential, substantially equal to -10 V. The well 24 is set to a negative potential, substantially equal to -5 V. The wall 16 is set to a potential, preferably in the range from -0.5 V to -1.5 V, preferably substantially equal to -1 V.

[0113] View B shows a second example of an erasing step of the cell 10. In this step, the well 12, the well 14 and the well 22 and the layer 18 are set to a positive potential, substantially equal to 10 V. In addition, the layer 28 is set to the reference potential GND. The well 24 is set to a positive potential, substantially equal to 5 V. The wall 16 is set to a potential, preferably in the range from 5 V to 15 V, preferably substantially equal to 9 V.

[0114] View C shows a third example of an erasing step of the cell 10. In this step, the well 12, the well 14 and the well 22 and the layer 18 are set to a positive potential, substantially equal to 5 V. In addition, the layer 28 is set to a negative potential, substantially equal to -5 V. The well 24 is set to the reference potential GND. The wall 16 is set to a potential, preferably in the range from 0 V to 10 V, preferably substantially equal to 4 V.

[0115] More generally, during an erasing step of the cell 10, the well 12, the well 14 and the well 22 and the layer 18 are set to a potential substantially equal to each other. The well 12, the well 14 and the well 22 and the layer 18 are set to a first potential. In addition, the wall 16 is set to a potential substantially equal to the threshold voltage V TP of the transistor formed by the well 12, the well 14 and the well 24 and the layers 18, 26 and 28, i.e. a P-channel transistor.

[0116] Moreover, the well 24 is set to a second potential lower than the first potential. The layer 28 is set to a third potential lower than the second potential. Preferably, the difference between the first potential and the second potential is in the range of 2V to 7V, preferably substantially equal to 5V. Similarly, the difference between the second potential and the third potential is in the range of 2V to 7V, preferably substantially equal to 5V. The difference between the first potential and the second potential is preferably substantially equal to the difference between the second potential and the third potential.

[0117] More generally, the different parts of the cell are set to potentials such that, during the erasing step, a current I3 is able to pass through the layer 18 between the well 12 and the well 24 along the wall 16 and the layer 26, as illustrated by the arrow in figure 1. Figure 4 The potentials of the well 24, the well 12, the layer 28 and the layer 18, as well as the wall 16, are such that a hot carrier injection phenomenon occurs. Thus, carriers, here holes h+, pass through the layer 27, by tunnel effect, into the layer 26 and remain trapped therein. This is illustrated by the arrow in figure 1. Figure 4

[0118] During the programming step, the holes trapped in the layer 26 compensate for the electrons trapped in the layer 26. Thus, during the readout step following the erasing step and in the absence of a new programming step, the absence of electrons ensures that the current I2 will be formed.

[0119] Preferably, the number of holes generated and trapped in the layer 26 during the erasing step is substantially equal to the number of electrons trapped in the layer 26 during the preceding programming step, so that the holes compensate for the electrons. To this end, the duration of the erasing step is preferably substantially the same as the duration of the programming step.

[0120] In a memory array of cells such as the cell 10, the cells can be erased bit by bit. Indeed, to erase the cell 10, the layer 28 and the wall 16 of the column of cells 10 are set to the third potential and to the potential V TP Moreover, the well 24 coupled to the well 24 of the array row of cells 10 by a connection element (not shown) forming a bit line is set to the second potential. The other layer 28, the other wall 16 and the other well 24 are for example all set to the first potential, or each to a potential different from the potential corresponding to the erasing. Thus, the erasing is performed only in the cell.

[0121] Figure 5 Another embodiment of a memory cell 40 is illustrated.

[0122] The memory cell 40 differs from the cell 10 of figure 1 in that the well 14 is separated from the layer 18 by a well 42. The well 42 is made of a P-type doped semiconductor material, for example doped with boron atoms, i.e. a doping opposite to that of the well 14. For example, the doping concentration ranges from 1015to 1020atoms / cm3. Figure 1 The memory cell 40 differs from the cell 10 of figure 1 in that the well 14 is separated from the layer 18 by a well 42. The well 42 is made of a P-type doped semiconductor material, for example doped with boron atoms, i.e. a doping opposite to that of the well 14. For example, the doping concentration ranges from 1015to 1020atoms / cm3.​14 ~5×10 15 at.cm^(-3).

[0123] Preferably, the well 14 is completely separated from the layer 18 by the well 42. Therefore, the well 14 does not contact the layer 18.

[0124] Well 42 extends from layer 18. Well 42 preferably extends along a height less than the distance between layer 18 and well 24. Therefore, well 42 is preferably separated from well 24 by a portion of well 14. Furthermore, well 42 preferably extends along a height less than the distance between layer 18 and insulating wall 25. Figure 5 Not shown in the diagram. Therefore, the well 14 preferably extends along a height greater than the height of the wall 25. This makes it possible to interconnect the well 14 with the well 14 of adjacent cells. Thus, the well 14 includes a portion located below the wall 25, in such a way that the well 14 can be shared by multiple cells (preferably all cells) in a column.

[0125] Preferably, the trap 42 is shared between cells in the same column. For example, the trap 42 is shared between two adjacent cells in the same row of the array.

[0126] according to Figure 5 In one embodiment, unit 40 includes an N-channel MOSFET transistor formed by layers 18, 12 and 22, 26, 27, 28 and 29, wherein layers 26, 27, 28 and 29 form the gate. Unit 40 also includes a P-channel MOSFET transistor formed by layers 42, 14 and 24, 26, 27, 28 and 29, wherein layers 26, 27, 28 and 29 form the gate.

[0127] The operation of cell 40 is the same as that of cell 10, except that the potential of well 42 is set to the same potential as that of well 12, except that the current I3 is located between well 42 and well 24 instead of between well 12 and well 24 during the erasure step.

[0128] Figure 5 An advantage of this embodiment is that the effective length of the P-channel transistor can be selected by choosing the height of the well 42.

[0129] Figure 6 Views A, B, C, and D illustrate another embodiment of the memory unit 50.

[0130] More accurately, Figure 6 include:

[0131] Top view A along plane AA of views B and D;

[0132] Cross-sectional view B along plane BB of views A and C;

[0133] a top view C along the plane C-C of view B and view D; and

[0134] a cross-sectional view D along the plane D-D of view A and view C.

[0135] The plane A-A and the plane C-C are parallel to each other and orthogonal to the plane B-B and the plane D-D. The plane B-B is orthogonal to the plane A-A, the plane C-C and the plane D-D. Similarly, the plane D-D is orthogonal to the plane A-A, the plane B-B and the plane C-C. The plane B-B corresponds to the direction of the bit lines of the array of memory cells. The plane D-D corresponds to the direction of the columns of the array of memory cells.

[0136] The memory cell 50 comprises two semiconductor blocks 51a and 51b. The blocks 51a and 51b are preferably adjacent to each other. The blocks 51a and 51b are preferably identical to each other within the conductivity type.

[0137] The semiconductor block 51a comprises a well 52. The well 52 is similar to the well 12 in Figure 1 . Thus, the well 52 is made of a semiconductor material, for example silicon. The well 52 is P-type doped. The well 52 is for example boron doped. The doping concentration in the well 52 is for example within the range of 10 14 ~ 5 x 10 15 at.cm^(-3).

[0138] The semiconductor block 51a comprises a well 58 located in the well 52. The well 58 is similar to the well 22 in Figure 1 . Thus, the well 58 is made of a semiconductor material, for example silicon. The well 58 is N-type doped (N+). The well 58 is for example phosphorous doped. The doping concentration in the well 58 is greater than the doping concentration in the well 54. The doping concentration in the well 58 is for example within the range of 10 18 ~ 10 20 at.cm^(-3).

[0139] Preferably, the well 58 extends from the level of the upper surface of the well 52. The well 58 preferably extends along a height that is less than the height of the well 52. The well 58 preferably extends along a height that is less than the height of the wall 62. The well 58 preferably extends along a height that is less than the height of the wall 56.

[0140] The semiconductor block 51b comprises a well 54. The well 54 is similar to the well 14 in Figure 1 . Thus, the well 54 is made of a semiconductor material, for example silicon. The well 54 is N-type doped. The well 54 is for example phosphorous doped. The doping concentration in the well 54 is for example within the range of 10 14 ~ 5 x 10 15 at.cm^(-3).

[0141] Similarly, semiconductor block 51b includes well 60 located in well 54. Well 60 is similar to Figure 1 Well 24 is located in the well. Therefore, well 60 is made of a semiconductor material such as silicon. Well 60 is P-type doped (P+). Well 60 is, for example, boron doped. The doping concentration in well 60 is greater than the doping concentration in well 52. The doping concentration in well 60 is, for example, in the range of 10. 18 ~10 20 within at.cm^(-3).

[0142] Blocks 51 and 51b are positioned adjacent to each other in the column direction. Cell 50 includes an insulating wall 56, for example, made of silicon oxide. Wall 56 extends in the bit line direction. Wall 56 at least partially separates blocks 51a and 51b. Preferably, wall 56 extends along the entire length of cell 50, i.e., along the entire length of cell 50 in the bit line direction. Preferably, wall 56 extends from the upper surfaces of wells 52 and 54, wells 58 and 60 and along wells 52 and 54, wells 58 and 60. Preferably, wall 56 extends along wells 52 and 54, wells 58 and 60 at a height less than the height of wells 52 and 54. Wells 52 and 54 are in contact with each other, for example, below wall 64. Preferably, wall 56 extends along wells 52, 54, 58 and 60 at a height greater than the height of wells 58 and 60. Thus, wells 58 and 60 are completely separated from adjacent blocks 51a or 51b by wall 56.

[0143] Furthermore, blocks 51a and 51b are separated from adjacent cells in the word line direction (i.e., column direction) by insulating wall 62. Preferably, wall 62 is the same as wall 56. Thus, cell 50 includes wall 62, block 51a, wall 56, block 51b, and another wall 62 in the word line direction.

[0144] The memory column comprises multiple cells 50. Therefore, the column includes alternating semiconductor blocks 51a, 51b and insulating walls 56, 62 separating the semiconductor blocks. Each block 51a is adjacent to a block 51b, and blocks 51a and 51b form a cell 50, separated from the block 51b by a wall 56. Thus, each wall 62 separates block 51a or 51b from another cell's block 51a or 51b.

[0145] Unit 50 also includes a wall 64. Wall 64 preferably comprises a conductive or semiconductor core 64a and an insulating sheath 64b, preferably made of silicon oxide, the core being made of, for example, a metal or semiconductor material, preferably polycrystalline silicon. For example, wall 64 extends in a direction orthogonal to walls 56 and 62. Wall 64 preferably extends in a letterline direction. Wall 64 extends along wells 52 and 54. Wall 64 contacts wells 52 and 54. Preferably, wall 64 extends along the entire height of wells 52 and 54. Walls 56 and 62 preferably extend from wall 64.

[0146] For example, the wall 64 separates the blocks 51a and 51b of the cell 50 from the blocks 51a and 51b of the cell 50 located in another column. The wall 64 is preferably common to all cells in the column.

[0147] Preferably, the traps 52 and 54 and the wall 64 have lower surfaces that are coplanar with each other. Preferably, the cell 50 comprises a layer 66 having the lower surfaces of the traps 52 and 54 and the lower surface of the wall 64 located thereon. The layer 66 is preferably made of a semiconductor material, for example silicon (e.g. N-type doped silicon). The layer 66 is located on a substrate 70, for example made of a semiconductor material.

[0148] The layer 66 is preferably common to all memory cells of the same type of cell 50 in the same memory array.

[0149] The trap 58 is separated from the wall 64 by a portion of the trap 52. In other words, a portion of the trap 52 is located between the trap 58 and the wall 64. Thus, the wall 64 and the trap 58 do not contact. The trap 58 extends from the upper surface of the trap 52. The trap 58 extends along a height that is less than the height of the trap 52. The upper surface of the trap 58 is preferably coplanar with the upper surface of the wall 64 and the upper surface of the portion of the trap 52 located between the trap 58 and the wall 64.

[0150] The trap 60 is separated from the wall 64 by a portion of the trap 54. In other words, a portion of the trap 54 is located between the trap 60 and the wall 64. Thus, the wall 64 and the trap 60 do not contact. The trap 60 extends from the upper surface of the trap 54. The trap 60 extends along a height that is less than the height of the trap 54. The upper surface of the trap 60 is preferably coplanar with the upper surface of the wall 64 and the upper surface of the portion of the trap 54 located between the trap 60 and the wall 64.

[0151] The doping type of the trap 52 is the opposite type to the doping type of the trap 54. Similarly, the doping type of the trap 58 is the opposite type to the doping type of the trap 60. Furthermore, the doping type of the trap 58 is the opposite type to the doping type of the trap 52. The doping type of the trap 60 is the opposite type to the doping type of the trap 54. Thus, the trap 58 and the trap 54 have the same doping type, the trap 60 and the trap 52 have the same doping type.

[0152] Preferably, the traps 52 and 54 are substantially the same size. Similarly, the traps 58 and 60 are the same size.

[0153] The cell 50 further comprises a stack of an insulating layer 71, a semiconductor layer 72, an insulating layer 73 and a conductive or semiconductor layer 74.

[0154] A layer 71 is located on the upper surfaces of the wells 52 and 54. A layer 72 is located on the layer 71. Preferably, the layer 71 and the layer 72 have substantially the same shape and horizontal dimensions, i.e. dimensions in a plane parallel to the plane A-A. Preferably, the layer 72 completely covers the layer 71. Preferably, the layer 71 extends continuously over the entire upper surfaces of the wells 52 and 54 and the upper surface of the wall 56. The layer 71 extends across the entire width of the wells 58 and 60 in the word line direction. Preferably, the layer 71 extends from one of the walls 62 to the other wall 62. For example, the layer 71 at least partially covers each of the walls 62 adjacent the cell 50. The layer 71 preferably extends from the well 58 to the wall 64 in the bit line direction. Preferably, the layer 71 extends at the level of the contact area between the well 52 and the wall 64 from the level of the contact area between the well 52 and the well 58. Preferably, the layer 71 is not located on the wells 58 and 60. The layer 71 separates the layer 72 from the wells 52 and 54.

[0155] A layer 73 covers the layer 71 and the layer 72. Preferably, the layer 73 covers the upper surface of the layer 72 and the side surfaces of the layer 71 and the layer 72, for example, the side surfaces in the array column direction.

[0156] The layer 74 is made of, for example, polysilicon. The layer 74 preferably completely covers the layer 72. Preferably, the layer 74 has substantially the same dimensions in the bit line direction as the layer 72.

[0157] Preferably, the layer 74 has larger dimensions in the word line direction than the layer 72. Preferably, the layer 74 is common to a plurality of cells of the same column, preferably to all cells of the column. Thus, the layer 74 preferably covers the layer 72 of a plurality of cells of the same column and covers the walls 62 separating the cells and the walls 56 separating blocks of different cells.

[0158] The cell further comprises contact elements 76 and 78, for example, conductive vias. The elements 76 and 78 are, for example, made of metal. The element 76 is in contact with the well 58 and the element 78 is in contact with the well 60. The elements 76 and 78 are preferably not in contact with the layers 72 and 74. The element 76 is preferably not in contact with the well 52. The element 78 is preferably not in contact with the well 54.

[0159] The operation of the cell 50 is the same as the operation of the cell 10 of Figure 1 . In each of the operation steps previously described in Figure 2 , Figure 3 and Figure 4 :

[0160] - the potential of the well 52 corresponds to the potential of the well 12,

[0161] - the potential of the well 54 corresponds to the potential of the well 14,

[0162] - the potential of the well 58 corresponds to the potential of the well 22,

[0163] - the potential of the well 60 corresponds to the potential of the well 24,

[0164] - the potential of the layer 74 corresponds to the potential of the layer 28,

[0165] - the potential of the layer 66 corresponds to the potential of the layer 18, and

[0166] - the potential of the wall 64 corresponds to the potential of the wall 16.

[0167] Figures 7 to 11 The steps, preferably successive steps, of a method of manufacturing a memory cell 10 according to an embodiment of the application are shown. Figure 1 The steps, preferably successive steps, of a method of manufacturing a memory cell 10 according to an embodiment of the application are shown. Figures 7 to 11 The steps, preferably successive steps, of a method of manufacturing a memory cell 10 according to an embodiment of the application are shown. Figures 7 to 11 The steps, preferably successive steps, of a method of manufacturing a memory cell 10 according to an embodiment of the application are shown. Figure 1 The steps, preferably successive steps, of a method of manufacturing a memory cell 10 according to an embodiment of the application are shown.

[0168] Figures 7 to 11 Each of the figures A1, B1, C1, A2, B2 and C2 comprises a view in the direction of the bit lines. The views A1, B1 and C1 are cross-sectional views in the direction of the bit lines. The views A2, B2 and C2 are cross-sectional views in the direction of the word lines. More precisely, the view A1 is a cross-sectional view in the direction of the bit lines along the plane AA of the view A2, showing the manufacturing of an eSTM cell. The view A2 is a cross-sectional view in the direction of the word lines along the plane DD of the structure of the view A1 of the same figure. The view B1 is a cross-sectional view in the direction of the bit lines along the plane BB of the view B2, showing the manufacturing of a cell according to an embodiment of the application. The view B2 is a cross-sectional view in the direction of the word lines along the plane EE of the structure of the view B1 of the same figure. The view C1 is a cross-sectional view in the direction of the bit lines along the plane CC of the view C2, showing the manufacturing of a MOSFET transistor. The view C2 is a cross-sectional view in the direction of the word lines along the plane FF of the structure of the view C1 of the same figure. Figure 1

[0169] The views A1, B1 and C1, the respective views A2, B2 and C2, are shown separately, but in principle can be adjacent to each other.

[0170] The views A2 and B2 each show the formation of two adjacent cells in the direction of the word lines. The view A1 shows the formation of two adjacent cells in the direction of the bit lines.

[0171] The views A2 and B2 each show the formation of two adjacent cells in the direction of the word lines. The view A1 shows the formation of two adjacent cells in the direction of the bit lines.Figure 7 The method of manufacturing an embodiment of the eSTM cell 10 is illustrated. Figure 1 The steps of the method of manufacturing an embodiment of the eSTM cell 10 are illustrated.

[0172] In this step, insulating walls 80 are formed in the semiconductor substrate 82. The insulating walls are preferably of the shallow trench isolation or STI type. The trenches 80 extend in the direction of the bit lines, other trenches 80 extend in the direction of the word lines to enclose the locations where the eSTM cell, the cell 10 and the MOSFET transistors are formed. The walls 80 thus define locations 81a, 81b and 81c where the eSTM cell, the cell 10 and the MOSFET transistors are formed, respectively. The walls 80 of the view B1 and the view B2 correspond to the walls 25 of the eSTM cell 10 of Figure 1 .

[0173] Preferably, the walls 80 protrude from the substrate 82. In other words, the walls 80 extend perpendicularly from the level of the upper surface of the substrate 82 and out of the substrate. Preferably, the walls 80 do not extend along the entire height of the substrate. For example, the walls 80 protrude from the substrate along a height substantially equal to 10 nm. For example, the walls 80 extend in the substrate 82 along a height substantially equal to 350 nm.

[0174] Furthermore, in this step, an insulating layer 84 is formed on the upper surface of the substrate. The layer 84 is for example made of silicon oxide. The layer 84 is for example formed simultaneously in the locations 81a, 81b and 81c by growth on the substrate. The thickness of the layer 84 is preferably less than the height by which the walls 80 protrude from the substrate. Thus, at the level of the eSTM cell, the cell 10 and the transistors, the layer 84 is enclosed by the walls 80.

[0175] This step also comprises forming the layer 18a by implanting dopants into the substrate. The layer 18 is preferably made of a semiconductor material, for example silicon, for example N-type doped silicon. Each location 81a, 81b and 81c comprises a layer 18a. The layers 18a of the different locations are for example formed during the same implantation.

[0176] The layer 18a is formed below the level of the lower surface of the walls 80. Thus, with respect to the upper surface of the substrate, the layer 18a is located deeper in the substrate than the walls 80. For example, the thickness of the layer 18a ranges from 1 pm to 10 pm. For example, the layer 18a is spaced from the level of the lower surface of the walls 80 by a distance ranging from 0.5 pm to 1 pm.

[0177] The implantation of dopants is for example performed in the locations 81a, 81b and 81c between the walls 80.

[0178] The layer 18a preferably extends in front of the entire upper surface of the substrate in the locations 81a, 81b, 81c.

[0179] For example, as shown in view A2, two adjacent eSTM cells in the word line direction can share the same layer 18a. Therefore, layer 18a extends under the wall 80 located between the two eSTM cells. Similarly, as shown in view B2, two adjacent cells 10 in the word line direction can share the same layer 18a. Therefore, layer 18a extends under the wall 80 located between the two cells 10. More generally, for example, layer 18 extends under the wall 80 located between memory cells including a common semiconductor well (which is subsequently formed), but not under the wall 80 separating the cells from elements (e.g., cells or transistors) that do not share a semiconductor well.

[0180] This step also includes forming a well 86 in position 81c. More precisely, the formation of well 86 corresponds to the doping of substrate 82 in position 81c. Well 86 is, for example, p-type doped, for example, at a concentration of 10. 14 ~5×10 15 The well 86 is preferably within the range of at.cm^(-3). The well 86 preferably extends from layer 84 to layer 18a at location 81c. Therefore, the well 86 preferably extends from the upper surface of the substrate to the upper surface of layer 18a at location 81c. For example, locations 81a and 81b are covered with a protective mask during the formation of the well 86, and this mask is removed after the formation of the well 86.

[0181] Figure 8 Manufacturing process is shown Figure 1 The steps of the method in the embodiment.

[0182] This step includes forming layer 18b at locations 81a and 81b. Layer 18b is located on top of layer 18a. Preferably, layer 18b completely covers layer 18a at locations 81a and 81b. Preferably, layer 18b is in contact with layer 18a at locations 81a and 81b. Layer 18b is made of N-type doped silicon. Layer 18b is, for example, doped with the same dopant as layer 18a and at the same order of magnitude doping concentration.

[0183] Layer 18b is located horizontally between the lower surface of wall 80 and layer 18a. Therefore, layer 18b is located deeper than the lower end of wall 80. Preferably, each layer 18b is spaced from the upper surface at a distance substantially equal to 500 nm.

[0184] The stacking of layers 18a and 18b corresponds to layer 18 at position 81b.

[0185] The manufacturing step also includes forming well 88 and well 90. Well 88 is located at position 81a, and well 90 is located at position 81b. Well 88 and well 90 are formed simultaneously, for example, during the same injection step.

[0186] The well 88 preferably extends from the layer 18b to the layer 84, in other words from the upper surface of the layer 18 to the upper surface of the substrate 82. Preferably, the entire area of the substrate 82 in the location 81a above the layers 18a and 18b is doped to form the well 88.

[0187] The well 88 is for example P-type doped, for example boron doped. For example, the doping concentration is 10 14 ~ 5 x 10 15 at.cm"1.

[0188] In case some eSTM cells share the same layer 18a, as illustrated in view Al and view A2, the layer 18b extends under the walls 80 located between said cells, and the substrate area between said walls 80 and the layer 18b is doped when forming the well. Thus, the well 88 extends between the layer 18b and the walls 80 located between said eSTM cells.

[0189] The well 90 is in the location 81b, preferably extending from the layer 18b to the layer 84, in other words from the upper surface of the layer 18 to the upper surface of the substrate 82. Preferably, the entire area of the substrate 82 in the location 81b above the layers 18a and 18b is doped to form the well 90.

[0190] The well 90 is for example P-type doped, for example boron doped. For example, the doping concentration is 10 14 ~ 5 x 10 15 at.cm"1. For example, the doping concentration is substantially equal to the doping concentration in the well 88. The doping concentration is preferably equal to the concentration of the well 12 of Figure 1 .

[0191] In case some cells 10 share the same layer 18a, as illustrated in view Bl and view B2, the layer 18b extends under the walls 80 located between said cells, and the substrate area between said walls 80 and the layer 18b is doped when forming the well 90. Thus, the well 90 extends between the layer 18b and the walls 80 located between said cells 10.

[0192] This step also comprises forming a well 92 in the well 90 of the location 81b. For example, the well 92 extends along the same height as the well 90, i.e. from the layer 18b to the upper surface of the substrate. The well 92 also extends in the plane of view Bl (i.e. in the bit line direction), from one wall 80 to the other. Preferably, the well 92 occupies half the lateral extension of the well 90.

[0193] The well 92 corresponds to the well 14 in Figure 1 , while the part of the well 90 not replaced by the well 92 corresponds to the well 12.

[0194] Figure 9 The fabrication of a memory cell 10 is illustrated. Figure 1The steps of the method in the embodiment.

[0195] In this step, layer 84 is removed from locations 81a, 81b, and 81c. Additionally, wall 94 is formed in locations 81a and 81b.

[0196] Each wall 94 extends from layer 18b along the height direction to the upper surface of the substrate. In other words, each wall 94 extends along the entire height of well 88 or well 90. Each wall extends in the word line direction. Preferably, each wall 94 is common to multiple eSTM cells or cells 10. Thus, each wall 94 passes through the wall 80 located between adjacent cells in the word line direction. Thus, the two eSTM cells in view A2 have a common wall 94 that passes through the wall 80 separating the cells. Similarly, the two cells 10 in view B2 have a common wall 94 that passes through the wall 80 separating the cells.

[0197] Each wall 94 is substantially located in the middle of the plane of views A1 and B1 of its location 81a or 81b. Therefore, each wall 84 is substantially at the same distance from the two opposing walls 80 surrounding location 81a or 81b, which are parallel to each other and parallel to wall 94.

[0198] The wall 94 located in position 81a divides the trap 88 into two traps of substantially the same size separated by the wall 94, each of the two traps extending in the word line direction.

[0199] Wall 94 at position 81b corresponds to Figure 1 Wall 16 separates trap 90 and trap 92, corresponding to Figure 1 Trap 12 and trap 14.

[0200] The walls 94 are preferably formed simultaneously. The walls 94 are preferably identical to each other. Each wall 94 includes, for example, a conductive or semiconductor core made of polycrystalline silicon, and an insulating sheath made of, for example, silicon oxide.

[0201] This step also includes forming an insulating layer 96 at locations 81b and 81c. Layer 96 is made of silicon oxide, for example. Layer 96 preferably extends over the entire upper surface of the substrate at locations 81a and 81b. Thus, at location 81c, layer 96 extends between walls 80 to cover well 86. At location 81b, layer 96 extends between walls 80 to cover well 90, well 92, and wall 94.

[0202] This step also comprises forming an insulating layer 98 in locations 81a and 81b. Layer 98 is for example made of silicon oxide. Layer 98 preferably extends in front of the entire upper surface of the substrate in locations 81a and 81b. Thus, in location 81a, layer 96 extends between walls 80 to cover well 88 and wall 94. In location 81b, layer 96 extends between walls 80 to completely cover layer 96 and thus extends in front of well 90, well 92 and wall 94.

[0203] The thickness of layer 96 is for example in the range 7 to 8 nm. The thickness of layer 98 is for example in the range 7 to 8 nm. More generally, the thickness of layers 96 and 98 is such that the stack of layers 96 and 98 does not protrude outside the walls.

[0204] This step also comprises forming a semiconductor layer, which is preferably made of polysilicon. Said layer is for example formed over the entire structure, in particular in locations 81a, 81b and 81c and on walls 80. Said layer is for example smoothed by chemical mechanical polishing (CMP) so that the upper surface of said layer is planar. Said layer is then etched to form a strip 102 in location 81a, a strip 104 in location 81b and a strip 106 in location 81c. Strips 102, 104 and 106 are preferably formed simultaneously during the same etching step.

[0205] Each strip 102 or 104 completely covers the location 81a, 81b in which it is located. In addition, strips 102 and 104 partially cover walls 80 delimiting locations 81a and 81b. Preferably, strips 102, 104 and 106 are not in contact with other strips 102, 104 or 106.

[0206] In case eSTM cells and cells 10 are adjacent to each other, i.e. if locations 81a and 81b are adjacent to each other, the layers 102 and 104 of adjacent cells can be common.

[0207] Strip 106 is formed to form a transistor gate. Thus, strip 106 of location 81c extends along the entire length of location 81c (i.e. the dimension in the word line direction) and at least partially on walls 80 delimiting location 81c in the word line direction. Strip 106 of location 81c extends partially over the width of location 81c (i.e. the dimension in the bit line direction), preferably at the center of location 81c. A part of well 86 is not in front of strip 106. More precisely, the areas corresponding to the source and drain regions of the transistor are not opposite strip 106.

[0208] Figure 10 The steps of a method of manufacturing an embodiment of Figure 1 are shown.

[0209] In this step, an insulating layer 108 is formed over the entire structure. The layer 108 is preferably a stack of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer. A semiconductor layer 110, preferably made of polysilicon, is formed, for example, over the entire structure, in particular at the locations 81a, 81b and 81c and on the wall 80. The layer thus covers the layer 108. The layer 110 is smoothed, for example by chemical mechanical polishing (CMP), such that the upper surface of the layer 110 is planar.

[0210] In the case where the eSTM cell and the cell 10 are adjacent to each other, i.e. if the locations 81a and 81b are adjacent to each other, the layers 108 and 110 of the adjacent cells can be common.

[0211] The layers 108 and 110 are then preferably etched simultaneously. The layers 108 and 110 are then etched completely from the location 81c.

[0212] Figure 11 The steps of the method of manufacturing an embodiment of the Figure 1 are shown.

[0213] In this step, the stack of the layer 102, the layer 108 and the layer 110 in the location 81a and the stack of the layer 104, the layer 108 and the layer 110 in the location 81b are etched. More precisely, the stack of the layer 104, the layer 108 and the layer 110 in the location 81b is etched to form a layer 26, a layer 29 and a layer 28 stack of the Figure 1 . Thus, the layer 96 and the layer 98 of the location 81b correspond to the layer 27 of the Figure 1 , the layer 104 of the location 81b corresponds to the layer 26 of the Figure 1 , the layer 108 of the location 81b corresponds to the layer 29 of the Figure 1 , and the layer 110 of the location 81b corresponds to the layer 28 of the Figure 1 .

[0214] The stack of layer 102, layer 108 and layer 110 in location 81a is etched to form two stacks, preferably identical, comprising layer 102, layer 108 and layer 110. Thus, each eSTM cell, i.e. each location 81a, comprises a stack of layer 102, layer 108 and layer 110. Said stack of each eSTM cell extends in the word line direction, i.e. in the plane of view A2, from the wall 80 defining the location 81a to the opposite wall 80 defining the location 81a. Said stack of each eSTM cell extends in the bit line direction, i.e. in the plane of view Al, partly on the upper surface of the well 88, on one side of the wall 94. Thus, two stacks are shown in view Al, one on each side of the wall 94, on layer 98. Each stack extends in the bit line direction from the wall 94 to the wall 80. Each stack extends in the bit line direction partly opposite to the portion of the well 88 on the same side of the wall 94. Thus, on each side of the wall 94, a portion of the well 88 is not in front of the stack, said portion being preferably separated from the wall 94 by a portion of the well 88 covered by the stack. Preferably, the stacks are not located opposite to the wall 94.

[0215] The layer 102 of each cell is independent from the layer 102 of the other cells. In particular, the layer 102 is separated from each other by the layer 108. Each layer 110 is shared with the adjacent cells, for example in the word line direction.

[0216] This step also comprises a step of implanting a more heavily doped well in the surface of the substrate. More precisely, this step comprises implanting N-type dopants:

[0217] - in location 81a, forming a well 112 in the surface of the well 88 in an area not located in front of the stack of layer 102, layer 108 and layer 110;

[0218] - in location 81b, forming a well 22 in the well 90, i.e. a well 22 in the well 12 Figure 1 ); and

[0219] - in location 81c, forming source and drain regions 114 in an area of the well 86 not covered by the layer 106.

[0220] The well 112, the well 22, the well 24 and the well 114 are preferably formed simultaneously during the same implantation step. Thus, the well 112, the well 22, the well 24 and the well 114 preferably have the same doping concentration.

[0221] In addition, this step also comprises implanting P-type dopants in location 81b to form a well 24 in the well 92, i.e. a well 14 Figure 1 ).

[0222] By Figures 7 to 11The method described forms a cell 10 with the advantage that the thickness of the insulating layer 27( Figure 9 ) corresponding to the stack of the layer 96 and the layer 98( Figure 1 ) is thicker than the thickness of the oxide layer of known eSTM cells, which produces better reliability.

[0223] The advantage of the embodiments described previously is that each cell can be erased independently of the other cells of the row of the array and of the column of the array.

[0224] Another advantage of the embodiments described is that the potentials used during the erasing step can be adapted to the device. Thus, only positive potentials can be used, only negative potentials can be used, or positive and negative potentials, but relatively close.

[0225] Another advantage of the embodiments described is that, because of the oxide thickness, they are more reliable than known eSTM memories.

[0226] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these various embodiments and variants can be combined and that other variants will occur to the person skilled in the art. In particular, the transistors formed by the method Figures 7 to 11 of the manufacturing method differ in that the well 86 is N-type doped, whereas the well 114 is P-type doped and is formed at the time of implantation of the P-type dopant forming the well 24.

[0227] Finally, the practical implementation of the embodiments and variants described is within the capabilities of the person skilled in the art, based on the functional indications given above.

Claims

1. A memory cell, comprising: A first doped well of a first conductivity type is in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type; The third doped well of the second conductivity type is in contact with the fourth doped well of the first conductivity type; A first wall is in contact with the second doped well and the fourth doped well, and the first wall includes a conductive core or a semiconductor core and an insulating sheath. The stack of layers includes a first insulating layer, a first semiconductor layer, a second insulating layer, and a second semiconductor layer that at least partially cover the second doped well and the fourth doped well; as well as The third semiconductor layer is located below the second doped well, the fourth doped well, and the first wall.

2. The unit according to claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

3. The unit according to claim 1, wherein the second doped well and the fourth doped well are separated by the first wall.

4. The unit of claim 3, wherein the stack of layers covers the first wall.

5. The unit according to claim 1, wherein the third semiconductor layer is separated from the fourth doped well by a doped semiconductor well of the second conductivity type.

6. The unit according to claim 1, wherein the second doped well and the fourth doped well are separated by a second insulating wall.

7. The unit of claim 6, wherein the stack of layers covers the second insulating wall.

8. A memory comprising: The array of memory cells according to claim 1, Each column of the array includes a corresponding second semiconductor layer and a corresponding first wall shared by the cells of the column.

9. A method for controlling a memory cell according to claim 1, the method comprising: The second doped well, the third doped well, the fourth doped well, and the third semiconductor layer are set to a first reference potential; The first doped well is set to a second positive potential, which is greater than the first reference potential; The second semiconductor layer is set to a third positive potential, wherein the third positive potential is greater than the second positive potential; as well as The first wall is set to a fourth potential, which is equal to the threshold voltage of the transistor. The transistor includes a first doped well, a second doped well, a third doped well, and a stack of the layers. Control includes programming.

10. The method of claim 9, wherein the first reference potential is ground, the second positive potential is substantially equal to 5V, the third positive potential is substantially equal to 12V, and the fourth potential is in the range of 0.5V to 1.5V.

11. A method for controlling a memory cell according to claim 1, the method comprising: The second doped well, the third doped well, and the fourth doped well, as well as the second semiconductor layer and the third semiconductor layer, are set to a fifth reference potential; The first doped well is set to a sixth positive potential, which is greater than the fifth reference potential; as well as The first wall is set to a seventh positive potential, which is greater than the sixth positive potential. Control includes reading.

12. The method of claim 11, wherein the fifth reference potential is ground, the sixth positive potential is substantially equal to 0.7V, and the seventh positive potential is substantially equal to 3V.

13. A method for controlling a memory cell according to claim 1, the method comprising: The first doped well, the second doped well, the third doped well, and the third semiconductor layer are set to the eighth reference potential; The fourth doped well is set to the ninth potential, which is less than the eighth reference potential; The second semiconductor layer is set to a tenth potential, which is less than the ninth potential; as well as The first wall is set to an eleventh potential, which is equal to the threshold voltage of the transistor. The transistor includes a second doped well, a third doped well, a fourth doped well, and a stack of the layers. The control includes erasure.

14. The method of claim 13, wherein the eighth reference potential is ground, the ninth potential is substantially equal to -5V, the tenth potential is substantially equal to -10V, and the eleventh potential is in the range of -1.5V to -0.5V.

15. The method of claim 13, wherein the eighth reference potential is substantially equal to 10V, the ninth potential is substantially equal to 5V, the tenth potential is grounded, and the eleventh potential is in the range of 5V to 15V.

16. The method of claim 13, wherein the eighth reference potential is substantially equal to 5V, the ninth potential is ground, the tenth potential is substantially equal to -5V, and the eleventh potential is in the range of 0V to 15V.

17. A method for manufacturing a memory cell according to claim 1, the method comprising: a. The third semiconductor layer is formed by implanting a layer dopant into a semiconductor substrate; b. The second doped well is formed by implanting a second dopant into the substrate; c. The fourth doped well is formed by implanting a fourth dopant into the substrate; d. Form the first wall between the second doped well and the third doped well; e. A stack of the layers is formed on a portion of the second doped well and the fourth doped well, and on the first wall; f. The first doped well is formed by injecting a first dopant into the second doped well; as well as g. The third doped well is formed by injecting a dopant into the fourth doped well.

18. The method of claim 17, wherein the first memory cell is formed by a, b, c, d, e, f and g, and wherein the second memory cell is formed by a, b, d, e and f.

19. The method of claim 17, wherein the first memory cell is formed by a, b, c, d, e, f, wherein the gate of the transistor is formed by e, and wherein the drain region and the source region are formed by f or g.

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