semiconductor structure

Abstract

This invention relates to a semiconductor structure comprising: multiple memory modules, each memory module including: a first memory cell; a second memory cell located on one side of the first memory cell; a third memory cell located on the other side of the first memory cell; a first transistor, with its first terminal electrically connected to the input terminal of the first memory cell; a second transistor, with its first terminal also electrically connected to the input terminal of the first memory cell; a third transistor, with its first terminal electrically connected to the input terminal of the second memory cell, and the channel width of the third transistor being greater than the channel widths of both the first and second transistors; and a fourth transistor, with its first terminal electrically connected to the input terminal of the third memory cell, and the channel width of the fourth transistor being greater than the channel widths of both the first and second transistors. This application can effectively improve the drive current of the memory cell.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Technology

[0002] With the advancement of semiconductor technology, storage devices are increasingly demanding miniaturization and integration.

[0003] Magnetic Random Access Memory (MARM) is an integration based on silicon-based complementary oxide semiconductor (CMOS) and magnetic tunnel junction (MTJ) technology. It typically consists of a fixed layer, a tunneling layer, and a free layer. During normal operation, the magnetization direction of the free layer can change, while the magnetization direction of the fixed layer remains constant. The resistance of the MARM is related to the relative magnetization directions of the free and fixed layers. When the magnetization direction of the free layer changes relative to the magnetization direction of the fixed layer, the resistance of the MARM changes accordingly, corresponding to different stored information.

[0004] However, due to limitations in the arrangement of memory cells and the connection method between magnetic tunnel junctions and transistors, the memory cell density of existing magnetic random access memories (MRAM) is relatively low, failing to meet the demands of high-density development. This restricts further improvement in the overall performance of MRAM and thus limits its widespread application. Furthermore, since MRAM requires a larger drive current for transistor operation compared to dynamic random access memories (DRAM), applying the buried word line (BWL) structure of DRAM to MRAM is limited because the required drive current is relatively small.

[0005] Therefore, how to design the structure of MRAM and improve its structural density and overall performance is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] Therefore, it is necessary to provide a semiconductor structure that can improve the drive current of memory cells, addressing the problems in the existing technology.

[0007] To achieve the above objectives, the present invention provides a semiconductor structure comprising: a plurality of memory modules, wherein the memory modules include:

[0008] First storage unit;

[0009] The second storage unit is located on one side of the first storage unit;

[0010] The third storage unit is located on the other side of the first storage unit;

[0011] A first transistor, wherein a first terminal of the first transistor is electrically connected to the input terminal of the first memory cell;

[0012] The second transistor, the first terminal of which is also electrically connected to the input terminal of the first memory cell;

[0013] The third transistor has its first terminal electrically connected to the input terminal of the second memory cell, and the channel width of the third transistor is greater than the channel width of the first transistor and the channel width of the second transistor.

[0014] A fourth transistor, the first terminal of which is electrically connected to the input terminal of the third memory cell, and the channel width of the fourth transistor is greater than the channel width of the first transistor and the channel width of the second transistor.

[0015] In one embodiment, the second terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor are electrically connected together.

[0016] In one embodiment, the first terminal is the drain terminal and the second terminal is the source terminal; or, the first terminal is the source terminal and the second terminal is the drain terminal.

[0017] In one embodiment, the storage module includes a first active region and a second active region, wherein the first transistor and the third transistor are formed in the first active region, and the second transistor and the fourth transistor are formed in the second active region.

[0018] In one embodiment, the first active region includes a first sub-region and a third sub-region that are interconnected, the width of the third sub-region being greater than the width of the first sub-region, the first transistor being formed in the first sub-region, and the third transistor being formed in the third sub-region.

[0019] In one embodiment, the second active region includes a second sub-region and a fourth sub-region that are interconnected, the width of the fourth sub-region being greater than the width of the second sub-region, the second transistor being formed in the second sub-region, and the fourth transistor being formed in the fourth sub-region.

[0020] In one embodiment, the storage module further includes a metal layer, one side of which is electrically connected to the first sub-region and the second sub-region via interconnect vias, and the other side of which is electrically connected to the first storage cell via interconnect vias.

[0021] In one embodiment, the semiconductor structure includes multiple word lines, including a first word line, a second word line, a third word line, and a fourth word line, wherein the gate of the first transistor is located on the first word line, the gate of the second transistor is located on the second word line, the gate of the third transistor is located on the third word line, and the gate of the fourth transistor is located on the fourth word line.

[0022] The first character line, the second character line, the third character line, and the fourth character line are all embedded character lines.

[0023] In one embodiment, both the first active region and the second active region extend along a first direction, and the first sub-region of the first active region and the second sub-region of the second active region are arranged adjacent to each other.

[0024] In one embodiment, the extension direction of the character line is a second direction, which is perpendicular to the first direction.

[0025] In one embodiment, the first active region and the second active region are arranged alternately in the first direction, and the first end of the first transistor, the first end of the second transistor, the first end of the third transistor and the first end of the fourth transistor all extend along the first direction, and the first end of the first transistor and the first end of the second transistor are electrically connected in the first direction through the metal layer.

[0026] In one embodiment, in the first direction, the first active region and the second active region are arranged alternately, the first end of the first transistor, the first end of the second transistor, the first end of the third transistor and the first end of the fourth transistor all extend along the first direction, and the first end of the first transistor and the first end of the second transistor are electrically connected in the second direction through the metal layer.

[0027] In one embodiment, the extension direction of the character line is a third direction, which is tilted at a preset angle relative to the first direction.

[0028] In one embodiment, in the first direction, the first active region and the second active region are arranged alternately, the first end of the first transistor, the first end of the second transistor, the first end of the third transistor and the first end of the fourth transistor all extend along the first direction, and the first end of the first transistor and the first end of the second transistor are electrically connected in the third direction through the metal layer.

[0029] In one embodiment, in the first direction, the centerline of the fourth sub-region coincides with the centerline of the third sub-region, and the centerline of the second sub-region is parallel to and intersects the centerline of the first sub-region.

[0030] In one embodiment, in the first direction, the centerline of the fourth sub-region coincides with the centerline of the third sub-region, and the centerline of the second sub-region coincides with the centerline of the first sub-region.

[0031] In one embodiment, the width of the third sub-region is 0.8 to 1.2 times the sum of the widths of the first and second sub-regions, and the width of the fourth sub-region is 0.8 to 1.2 times the sum of the widths of the first and second sub-regions.

[0032] In one embodiment, the width of the first sub-region is the same as the width of the second sub-region, both being W, and the width of the third sub-region is the same as the width of the fourth sub-region, both being 2W.

[0033] In the aforementioned semiconductor structure, the first memory cell is driven by both the first transistor and the second transistor, which can effectively increase the driving current and thus ensure that the first memory cell can be driven normally.

[0034] The channel width of the third transistor is greater than that of both the first and second transistors. Since the channel width is proportional to the drive current, the third transistor can effectively increase the drive current of the second memory cell by increasing its channel width, thereby ensuring that the second memory cell can be driven normally.

[0035] Meanwhile, the channel width of the fourth transistor is greater than that of both the first and second transistors. Therefore, the increased channel width of the fourth transistor can effectively increase the drive current of the third memory cell, thereby ensuring that the third memory cell can be driven normally.

[0036] Meanwhile, this application combines increasing the number of transistors driving the memory cells with increasing the channel width of the driving transistors, so that four transistors (first transistor, second transistor, third transistor, and fourth transistor) drive three memory cells (first memory cell, second memory cell, and third memory cell), thereby effectively ensuring that the memory cells have a high density. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a circuit diagram of a semiconductor structure provided in one embodiment;

[0039] Figures 2 to 6 This is a schematic diagram of the planar arrangement of the semiconductor structure provided in different embodiments. Detailed Implementation

[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0045] Embodiments of the invention are described herein with reference to a cross-sectional view illustrating an ideal embodiment (and intermediate structure) of the invention, thus allowing for the anticipation of variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shape of the area shown herein, but rather include shape deviations due to, for example, manufacturing techniques.

[0046] In one embodiment, see Figure 1 A semiconductor structure is provided, including multiple memory modules. Each memory module includes: a first memory cell 100, a second memory cell 200, a third memory cell 300, a first transistor 400, a second transistor 500, a third transistor 600, and a fourth transistor 700.

[0047] The first storage unit 100, the second storage unit 200, and the third storage unit 300 may be, but are not limited to, magnetic storage units.

[0048] The second storage unit 200 is located on one side of the first storage unit 100, and the third storage unit 300 is located on the other side of the first storage unit 100, that is, the second storage unit 200 and the third storage unit 300 are located on both sides of the first storage unit 100 respectively.

[0049] The first terminal of the first transistor 400 and the first terminal of the second transistor 500 are both electrically connected to the input terminal of the first memory cell 100, thereby driving the first memory cell 100.

[0050] The first terminal of the third transistor 600 is electrically connected to the input terminal of the second memory cell 200, thereby driving the second memory cell 200.

[0051] The first terminal of the fourth transistor 700 is electrically connected to the input terminal of the third memory cell 300, thereby driving the third memory cell 300.

[0052] It is understandable that the "first end" here can be either the drain extreme or the source extreme.

[0053] In this embodiment, the first storage cell 100 is driven by the first transistor 400 and the second transistor 500 simultaneously, which can effectively increase the driving current and thus ensure that the first storage cell 100 can be driven normally.

[0054] The channel width of the third transistor 600 is greater than that of the first transistor 400 and the second transistor 500. Since the channel width is proportional to the drive current, the third transistor 600 can effectively increase the drive current of the second memory cell 200 by increasing the channel width, thereby ensuring that the second memory cell 200 can be driven normally.

[0055] Meanwhile, the channel width of the fourth transistor 700 is greater than that of the first transistor 400 and the second transistor 500. Therefore, the fourth transistor 700 can effectively increase the drive current of the third memory cell 300 by increasing the channel width, thereby ensuring that the third memory cell 300 can be driven normally.

[0056] Meanwhile, this embodiment combines increasing the number of transistors driving the memory cells with increasing the channel width of the driving transistors, so that four transistors (first transistor 400, second transistor 500, third transistor 600 and fourth transistor 700) drive three memory cells (first memory cell 100, second memory cell 200 and third memory cell 300), thereby effectively ensuring that the memory cells have a high density.

[0057] In one embodiment, the second terminals of the first transistor 400, the second transistor 500, the third transistor 600, and the fourth transistor 700 are electrically connected together.

[0058] At this time, the second terminals of the first transistor 400, the second transistor 500, the third transistor 600, and the fourth transistor 700 can all be connected to the source line SL simultaneously. Therefore, this embodiment can effectively simplify the circuit structure.

[0059] It is understandable that the "second end" here can be either the source extreme or the drain extreme.

[0060] As an example, the first end can be set as the drain endpoint and the second end as the source endpoint. Alternatively, the first end can be set as the source endpoint and the second end as the drain endpoint. This application does not impose any restrictions on this.

[0061] In one embodiment, see Figures 2 to 6 In any of the diagrams, the storage module includes a first active region A1 and a second active region A2. A first transistor 400 and a third transistor 600 are formed in the first active region A1. A second transistor 500 and a fourth transistor 700 are formed in the second active region A2.

[0062] Specifically, the semiconductor structure may include a semiconductor substrate. A shallow trench isolation structure may be formed within the semiconductor substrate. The shallow trench isolation structure can isolate the semiconductor substrate to form multiple active regions. These multiple active regions specifically include multiple first active regions A1 and multiple second active regions A2.

[0063] The active regions (first active region A1 and second active region A2) of the semiconductor substrate can form the conductive channel of the transistor and the source and drain terminals located on both sides of the conductive channel.

[0064] Specifically, when forming a transistor, a gate insulating layer can first be formed on the active region. Then, the gate is formed on the gate insulating layer. The semiconductor substrates on both sides of the gate are heavily doped to form the source and drain terminals.

[0065] In this embodiment, the first transistor 400 driving the first memory cell 100 and the third transistor 600 driving the second memory cell 200 are formed in the same active region, and the second transistor 500 driving the first memory cell 100 and the fourth transistor 700 driving the third memory cell 300 are formed in the same active region, thereby making it easier to process and form the active region.

[0066] Meanwhile, the first transistor 400 and the second transistor 500 that drive the first storage cell 100 are respectively formed in the first active region A1 and the second active region A2, thereby making the position setting of the first transistor 400 and the second transistor 500 more flexible.

[0067] Of course, in other embodiments, the arrangement of the first transistor 400, the second transistor 500, the third transistor 600, and the fourth transistor 700 can also be different. For example, the first transistor 400, the second transistor 500, the third transistor 600, and the fourth transistor 700 can all be located in the same active region. Alternatively, the first transistor 400, the second transistor 500, the third transistor 600, and the fourth transistor 700 can be located in four different active regions, and this application does not limit either of these options.

[0068] In one embodiment, see Figures 2 to 6 In any of the diagrams, the first active region A1 includes a first sub-region A11 and a third sub-region A13 that are interconnected. The width of the third sub-region A13 is greater than the width of the first sub-region A11. A first transistor 400 is formed in the first sub-region A11, and a third transistor 600 is formed in the third sub-region A13.

[0069] At this point, it is possible to effectively achieve a channel width of the third transistor 600 that is greater than the channel width of the first transistor 400.

[0070] In one embodiment, see Figures 2 to 6 In any of the diagrams, the second active region A2 includes a second sub-region A22 and a fourth sub-region A24 that are interconnected. The width of the fourth sub-region A24 is greater than the width of the second sub-region A22. The second transistor 500 is formed in the second sub-region A11, and the fourth transistor 700 is formed in the fourth sub-region A24.

[0071] At this point, it is possible to effectively achieve a channel width of the fourth transistor 700 that is greater than the channel width of the second transistor 500.

[0072] In one embodiment, see Figures 2 to 6 In any of the diagrams shown, the storage module also includes a metal layer 800. One side of the metal layer 800 is electrically connected to the first sub-region A11 and the second sub-region A22 via interconnect vias. The other side of the metal layer 800 is electrically connected to the first storage cell 100 via interconnect vias.

[0073] The metal layer 800 has good conductivity. The metal layer 800 is electrically connected to the first sub-region A11 and the second sub-region A22 through interconnecting vias, so that the driving current input by the first transistor 400 and the second transistor 500 can be effectively and reliably transmitted to the first memory cell 100.

[0074] In one embodiment, see Figures 2 to 6 In any of the diagrams, the semiconductor structure includes multiple word lines 900.

[0075] The character line 900 includes the first character line, the second character line, the third character line, and the fourth character line.

[0076] The gate of the first transistor 400 is located on the first word line. The gate of the second transistor 500 is located on the second word line. The gate of the third transistor 600 is located on the third word line. The gate of the fourth transistor 700 is located on the fourth word line.

[0077] The first, second, third, and fourth character lines are all embedded character lines, which effectively reduces the size of the device.

[0078] It is understandable that the same word line may belong to the first word line, the second word line, the third word line, or the fourth word line for different transistors.

[0079] Specifically, multiple trenches can be formed within the active regions (first active region A1 and second active region A2). Then, a gate insulating layer is formed on the sidewalls of each trench. Subsequently, multiple word lines filling each trench are formed on the surface of the gate insulating layer.

[0080] In one embodiment, see Figures 2 to 6 In any of the diagrams, the first active region A1 and the second active region A2 both extend along the first direction, which facilitates the layout design of the active regions.

[0081] The first sub-region A11 of the first active region A1 and the second sub-region A22 of the second active region A2 are arranged adjacent to each other, thereby facilitating the electrical connection of the first transistor 400 formed in the first active region A1 and the second transistor 500 formed in the second active region A2 through the metal layer 800.

[0082] In one embodiment, see Figure 2 or Figure 3 or Figure 4 The extension direction of the word line 900 is the second direction. Referring to the figure, the second direction is perpendicular to the first direction. That is, in this embodiment, the extension direction of the word line 900 is perpendicular to the extension direction of the active areas (first active area A1 and second active area A2), thereby simplifying the setting of the word line 900 and the active areas.

[0083] In one embodiment, see Figure 2 In the first direction, the first active region A1 and the second active region A2 are arranged alternately. The first terminal of the first transistor 400, the first terminal of the second transistor 500, the first terminal of the third transistor 600 and the first terminal of the fourth transistor 700 all extend along the first direction.

[0084] At this time, the first end of the first transistor 400 is located at the right end of the first active region A1, and the second end of the second transistor 500 is located at the left end of the second active region A2, and the two are adjacent to each other and opposite each other.

[0085] The first terminal of the first transistor 400 and the first terminal of the second transistor 500 are electrically connected in a first direction through a metal layer 800.

[0086] Furthermore, in the first direction, the center line of the fourth sub-region A24 can be set to coincide with the center line of the third sub-region A13, and the center line of the second sub-region A22 can coincide with the center line of the first sub-region A11. This facilitates the design and formation of the active region.

[0087] In one embodiment, see Figure 3 In the first direction, the first active region A1 and the second active region A2 are arranged alternately. The first terminal of the first transistor 400, the first terminal of the second transistor 500, the first terminal of the third transistor 600 and the first terminal of the fourth transistor 700 all extend along the first direction.

[0088] At this time, the first end of the first transistor 400 is located at the right end of the first active region A1, and the second end of the second transistor 500 is located at the left end of the second active region A2, and the two are adjacent to each other and opposite each other.

[0089] The first terminal of the first transistor 400 and the first terminal of the second transistor 500 are electrically connected in a second direction through a metal layer 800.

[0090] Further, please refer to Figure 4 Alternatively, the center line of the fourth sub-region A24 of the second active region A2 in the first direction can be set to coincide with the center line of the third sub-region A13 of the first active region A1. At the same time, the center line of the second sub-region A22 of the second active region A2 in the first direction is parallel to and intersects with the center line of the first sub-region A11 of the first active region A1.

[0091] At this point, the space occupied by a pair of first active regions A1 and second active regions A2 located in the same storage module can be effectively reduced, thereby effectively increasing the storage cell density.

[0092] In one embodiment, see Figure 5 or Figure 6 The extension direction of the character line 900 is a third direction. The third direction is tilted at a preset angle relative to the first direction.

[0093] At this time, the extension direction of word line 900 is tilted at a preset angle to the extension direction of active region (first active region A1 and second active region A2), so that more active regions can be formed in semiconductor substrate of the same size, thereby effectively improving the storage cell density.

[0094] In one embodiment, see Figure 5In the first direction, the first active region A1 and the second active region A2 are arranged alternately. The first terminal of the first transistor 400, the first terminal of the second transistor 500, the first terminal of the third transistor 600 and the first terminal of the fourth transistor 700 all extend along the first direction.

[0095] At this time, the first end of the first transistor 400 is located at the lower left end of the first active region A1, and the second end of the second transistor 500 is located at the upper right end of the second active region A2. The two transistors are adjacent and opposite each other in a direction perpendicular to the first direction.

[0096] The first terminal of the first transistor 400 and the first terminal of the second transistor 500 are electrically connected in the third direction through the metal layer 800.

[0097] Further, please refer to Figure 6 Alternatively, the center line of the fourth sub-region A24 of the second active region A2 in the first direction can be set to coincide with the center line of the third sub-region A13 of the first active region A1. At the same time, the center line of the second sub-region A22 of the second active region A2 in the first direction is parallel to and intersects with the center line of the first sub-region A11 of the first active region A1.

[0098] At this point, the space occupied by a pair of first active regions A1 and second active regions A2 located in the same storage module can be effectively reduced, thereby further increasing the storage cell density.

[0099] In one embodiment, the width of the third sub-region A13 of the first active region A1 is 0.8 to 1.2 times the sum of the widths of the first sub-region A11 of the first active region A1 and the second sub-region A22 of the second active region A2.

[0100] The width of the fourth sub-region A24 of the second active region A2 is 0.8 to 1.2 times the sum of the widths of the first sub-region A11 of the first active region A1 and the second sub-region A22 of the second active region A2.

[0101] Ignoring process errors, the width of the first sub-region A11 is the channel width of the first transistor 400. The width of the second sub-region A22 is the channel width of the second transistor 500. The width of the third sub-region A13 is the channel width of the third transistor 600. The width of the fourth sub-region A24 is the channel width of the fourth transistor 700.

[0102] Therefore, the channel width of the third transistor 600 is equivalent to the sum of the widths of the first transistor 400 and the second transistor 500. And the channel width of the fourth transistor 700 is equivalent to the sum of the widths of the first transistor 400 and the second transistor 500.

[0103] Therefore, this embodiment can make the drive current of the first storage unit 100, the second storage unit 200 and the third storage unit 300 more consistent, thereby making the performance of each storage unit more uniform.

[0104] Furthermore, the width of the first sub-area A11 can be set to be the same as the width of the second sub-area A22, both being W. Meanwhile, the width of the third sub-area A13 and the fourth sub-area A24 can be the same, both being 2W.

[0105] At this time, the drive currents of the first storage unit 100, the second storage unit 200 and the third storage unit 300 can be more consistent, thereby making the performance of each storage unit more uniform.

[0106] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0107] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple storage modules, the storage modules including: First storage unit; The second storage unit is located on one side of the first storage unit; The third storage unit is located on the other side of the first storage unit; the first storage unit, the second storage unit, and the third storage unit are all magnetic storage units. A first transistor, wherein a first terminal of the first transistor is electrically connected to the input terminal of the first memory cell; The second transistor, the first terminal of which is also electrically connected to the input terminal of the first memory cell; The third transistor has its first terminal electrically connected to the input terminal of the second memory cell, and the channel width of the third transistor is greater than the channel width of the first transistor and the channel width of the second transistor. A fourth transistor, the first terminal of which is electrically connected to the input terminal of the third memory cell, and the channel width of the fourth transistor is greater than the channel width of the first transistor and the channel width of the second transistor. The semiconductor structure also includes multiple buried word lines, with the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor respectively disposed on different buried word lines.

2. The semiconductor structure according to claim 1, characterized in that, The second terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor are electrically connected together.

3. The semiconductor structure according to claim 2, characterized in that, The first terminal is the drain terminal, and the second terminal is the source terminal; or, the first terminal is the source terminal, and the second terminal is the drain terminal.

4. The semiconductor structure according to claim 1, characterized in that, The storage module includes a first active region and a second active region, wherein the first transistor and the third transistor are formed in the first active region, and the second transistor and the fourth transistor are formed in the second active region.

5. The semiconductor structure according to claim 4, characterized in that, The first active region includes a first sub-region and a third sub-region that are interconnected. The width of the third sub-region is greater than the width of the first sub-region. The first transistor is formed in the first sub-region, and the third transistor is formed in the third sub-region.

6. The semiconductor structure according to claim 5, characterized in that, The second active region includes a second sub-region and a fourth sub-region that are interconnected. The width of the fourth sub-region is greater than the width of the second sub-region. The second transistor is formed in the second sub-region, and the fourth transistor is formed in the fourth sub-region.

7. The semiconductor structure according to claim 6, characterized in that, The storage module further includes a metal layer, one side of which is electrically connected to the first sub-region and the second sub-region through interconnect vias, and the other side of which is electrically connected to the first storage cell through interconnect vias.

8. The semiconductor structure according to claim 7, characterized in that, The multiple embedded word lines include a first word line, a second word line, a third word line, and a fourth word line. The gate of the first transistor is located on the first word line, the gate of the second transistor is located on the second word line, the gate of the third transistor is located on the third word line, and the gate of the fourth transistor is located on the fourth word line.

9. The semiconductor structure according to claim 8, characterized in that, Both the first active region and the second active region extend along the first direction, and the first sub-region of the first active region and the second sub-region of the second active region are arranged adjacent to each other.

10. The semiconductor structure according to claim 9, characterized in that, The extension direction of the character line is a second direction, which is perpendicular to the first direction.

11. The semiconductor structure according to claim 10, characterized in that, In the first direction, the first active region and the second active region are arranged alternately. The first end of the first transistor, the first end of the second transistor, the first end of the third transistor and the first end of the fourth transistor all extend along the first direction, and the first end of the first transistor and the first end of the second transistor are electrically connected in the first direction through the metal layer.

12. The semiconductor structure according to claim 10, characterized in that, In the first direction, the first active region and the second active region are arranged alternately. The first end of the first transistor, the first end of the second transistor, the first end of the third transistor and the first end of the fourth transistor all extend along the first direction, and the first end of the first transistor and the first end of the second transistor are electrically connected in the second direction through the metal layer.

13. The semiconductor structure according to claim 9, characterized in that, The extension direction of the character line is a third direction, which is tilted at a preset angle relative to the first direction.

14. The semiconductor structure according to claim 13, characterized in that, In the first direction, the first active region and the second active region are arranged alternately. The first end of the first transistor, the first end of the second transistor, the first end of the third transistor and the first end of the fourth transistor all extend along the first direction, and the first end of the first transistor and the first end of the second transistor are electrically connected in the third direction through the metal layer.

15. The semiconductor structure according to claim 12 or 14, characterized in that, In the first direction, the center line of the fourth sub-region coincides with the center line of the third sub-region, and the center line of the second sub-region is parallel to and intersects the center line of the first sub-region.

16. The semiconductor structure according to claim 11, characterized in that, In the first direction, the centerline of the fourth sub-region coincides with the centerline of the third sub-region, and the centerline of the second sub-region coincides with the centerline of the first sub-region.

17. The semiconductor structure according to claim 6, characterized in that, The width of the third sub-region is 0.8 to 1.2 times the sum of the widths of the first and second sub-regions, and the width of the fourth sub-region is 0.8 to 1.2 times the sum of the widths of the first and second sub-regions.

18. The semiconductor structure according to claim 17, characterized in that, The width of the first sub-region is the same as the width of the second sub-region, and both are W. The width of the third sub-region is the same as the width of the fourth sub-region, and both are 2W.

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