Display Panel

Abstract

The display panel provided in the present application insulates the first wiring portion and the second wiring portion from each other in an overlapping manner in a non-display area through a first insulating portion, so that during the evaporation process of the cathode layer, even if there is a certain degree of evaporation deviation, the cathode layer will only flow through the first opening to the side of the second wiring portion away from the substrate, and will not contact the first wiring portion, thereby effectively avoiding the short circuit problem caused by the cathode evaporation deviation.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] Compared with traditional liquid crystal display (LCD) panels, OLED display panels are easy to be flexible and are the key technology for wearable and foldable products. With the development of organic light emitting diode (OLED) display panel technology, narrow frame technology has become a differentiated technology to attract user groups.

[0003] In order to achieve narrow frame technology, the lower frame of the OLED display panel is greatly compressed, so that the power supply wiring is closer to the display area (Active area, AA area). Since the cathode layer of the light-emitting device is connected to the negative power supply (VSS) wiring in the plane to achieve conduction, this process needs to be achieved through the metal film layer. During the cathode evaporation process, there is a certain degree of evaporation deviation, especially the current narrow frame design makes the evaporation area close to the positive power supply (VDD) wiring, which is prone to short circuit problems caused by cathode layer evaporation deviation. Summary of the invention

[0004] In view of the above-mentioned defects and deficiencies in the prior art, it is desired to provide a display panel to solve the short circuit problem caused by the cathode layer evaporation deviation.

[0005] To this end, the present application provides a display panel, including:

[0006] A substrate, the substrate comprising a display area and a non-display area located outside the display area;

[0007] A first wiring layer, the first wiring layer is arranged on the substrate, the first wiring layer comprises a first wiring portion, and the first wiring portion is located in the non-display area;

[0008] A first insulating layer, the first insulating layer is provided on a side of the first wiring layer away from the substrate, and the first insulating layer comprises a first insulating portion, and the first insulating portion covers the first wiring portion;

[0009] A second routing layer, the second routing layer is arranged on a side of the first insulating layer away from the substrate, the second routing layer comprises a second routing portion, and the second routing portion is arranged on a side of the first insulating portion away from the substrate;

[0010] The second insulating layer is disposed on a side of the second wiring layer away from the substrate, and the second insulating layer is provided with a first opening, and the first opening is disposed corresponding to the second wiring portion.

[0011] In the display panel provided in the present application, a second opening is provided in the first insulating layer in a region close to the display area, and a portion of the first wiring portion is exposed through the second opening.

[0012] In the display panel provided in the present application, the second wiring layer further includes a third wiring portion;

[0013] The third wiring portion is disposed in the second opening, and the third wiring portion is insulated from the second wiring portion.

[0014] In the display panel provided in the present application, the second wiring layer further includes a fourth wiring portion;

[0015] The fourth routing portion is connected to the third routing portion, overlaps the side wall of the second opening and extends to a side of the first insulating portion away from the substrate, and a gap is left between the second routing portion and the fourth routing portion.

[0016] In the display panel provided in the present application, the second insulating layer includes a second insulating portion, and the second insulating portion covers the third wiring portion, the fourth wiring portion, the gap, and a portion of the second wiring portion close to the gap.

[0017] In the display panel provided in the present application, the first wiring layer further includes a fifth wiring portion;

[0018] The fifth wiring portion and the first wiring portion are arranged with an interval along a direction parallel to an edge of the display area close to the non-display area.

[0019] In the display panel provided in the present application, the first insulating portion is provided with a third opening in a region corresponding to the fifth wiring portion, and a portion of the fifth wiring portion is exposed through the third opening.

[0020] In the display panel provided in the present application, the second routing portion extends in a direction parallel to an edge of the display area close to the non-display area, and the second routing portion overlaps a side of the fifth routing portion away from the substrate through the third opening.

[0021] In the display panel provided in the present application, the second insulating layer includes a third insulating portion, the third insulating portion is arranged on a side of the first opening away from the display area, and the third insulating portion covers the side of the second wiring portion, the side of the first insulating portion and the side of the first wiring portion.

[0022] In the display panel provided in the present application, the second insulating layer is further provided with a fourth opening, the fourth opening is located on a side of the first opening away from the display area, and a portion of the second wiring portion is exposed through the fourth opening.

[0023] The display panel provided by the present application has the first wiring portion and the second wiring portion overlappedly arranged, that is, through the first insulating portion, the first wiring portion and the second wiring portion are insulated and overlapped, so that during the evaporation process of the cathode layer, even if there is a certain degree of evaporation deviation, the cathode layer will flow through the first opening to the side of the second wiring portion away from the substrate, so as not to contact the first wiring portion, thereby avoiding the short circuit problem caused by the cathode evaporation deviation; in addition, the display panel provided by the present application can also omit the setting of the passivation layer, thereby saving a process and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a structure of a display panel in the prior art;

[0025] Figure 2 for Figure 1 A schematic structural diagram of a non-display area of ​​a display panel shown;

[0026] Figure 3 for Figure 2 Enlarged view of middle area F;

[0027] Figure 4 for Figure 3 Sectional view in the AA direction;

[0028] Figure 5 for Figure 3 Cross-sectional view in the BB direction;

[0029] Figure 6 A first cross-sectional view of the display panel provided in an embodiment of the present application along the AA direction in region F;

[0030] Figure 7 A second cross-sectional view of the display panel provided in an embodiment of the present application along the AA direction in region F;

[0031] Figure 8 A third cross-sectional view of the display panel provided in an embodiment of the present application along the AA direction in region F;

[0032] Fig. 9 A fourth cross-sectional view of the display panel provided in an embodiment of the present application along the AA direction in region F;

[0033] Fig.10 A fifth cross-sectional view of the display panel provided in the embodiment of the present application along the AA direction in region F;

[0034] Fig.11 A cross-sectional view of the display panel provided in an embodiment of the present application in area F along direction BB. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0036] In the present application, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore includes the state where the angle is greater than 85° and less than 95°.

[0037] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, the embodiments of the present application are not necessarily limited to such dimensions, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0038] In addition, the terms "first", "second", etc. in the specification and claims of the present application are used to distinguish different objects rather than to describe a specific order. The terms "include", "have" and any variations thereof are intended to cover non-exclusive inclusions.

[0039] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a structure of a display panel in the prior art. Figure 1 As shown, the display panel includes: a display area 100 and a non-display area located outside the display area 100. The non-display area includes a binding area 200 located on one side of the display area 100 and a peripheral area 300 located between the display area 100 and the binding area 200.

[0040] Next, see Figure 2 , Figure 2 for Figure 1 The schematic diagram of the structure of the non-display area of ​​the display panel is shown in FIG. Figure 2As shown, the peripheral area 300 includes a first fan-out area 301, a bending area 302, a second fan-out area 303, an electrostatic protection area 304, and a driver chip area 305, which are sequentially arranged in a direction away from the display area 100. Among them, the first fan-out area 301 includes a first power line 310 and a second power line 320. The first power line 310 is located in the middle area of ​​the first fan-out area 301, and the second power line 320 is located on both sides of the first power line 310.

[0041] Among them, the first fan-out area 301 is used to connect the VDD line and the VSS line of the display area 100 through the first power line 310 and the second power line 320 respectively. The bending area 302 is used to bend the binding area 200 to the back of the display area 100. The second fan-out area 303 leads out multiple data connection lines to the driver chip area 305. The electrostatic protection area 304 includes an electrostatic protection circuit for preventing static electricity from damaging the display panel. The driver chip area 305 includes an integrated circuit chip for connecting to multiple data connection lines. The binding area 200 includes multiple binding pads for binding and connecting with a flexible circuit board.

[0042] Next, see Figure 3 , Figure 3 for Figure 2 A magnified view of area F in the middle. Figure 3 As shown, the display panel includes a display area 100 and a non-display area disposed outside the display area 100, and the non-display area includes a bending area 302 and a first fan-out area 301 located between the display area 100 and the bending area 302. The first fan-out area 301 includes a first power line 310 and a second power line 320. The first power line 310 is connected to the display area 100 and is used to transmit a VDD signal to the display area 100. The second power line 320 is connected to the display area 100 and is used to transmit a VSS signal to the display area 100.

[0043] Combination Figures 1 to 3 It can be seen that in order to achieve a narrow frame in the existing display panel, the first power line 310 and the second power line 320 are distributed closer to the display area 100. Therefore, when evaporating the cathode layer, a certain degree of evaporation deviation can easily lead to a large-area short circuit between the cathode layer and the first power line 310 as the VDD line, which is very risky. Although the prior art proposes to add a passivation layer to separate the cathode layer from the first power line 310, this design still has the problem that after the passivation layer is over-etched, the cathode layer contacts the first power line 310, thereby causing a short circuit. In addition, adding a passivation layer also requires adding a mask, which increases the time cost, labor cost and economic cost of preparing a display panel with a narrow frame.

[0044] Specifically, the existing display panel at least includes a substrate, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a first wiring layer, a passivation layer, a first insulating layer, a second wiring layer, a second insulating layer and a pixel definition layer stacked in sequence. Figure 3 as well as Figure 4 , Figure 4 for Figure 3 Schematic diagram of the cross section along the AA direction. Figure 4 As shown, the first fan-out area 301 of the non-display area may include: a substrate 10, a first wiring layer 20 arranged on the substrate 10, a passivation layer 30 arranged on the side of the first wiring layer 20 away from the substrate 10, a first insulating layer 40 arranged on the side of the passivation layer 30 away from the substrate 10, a second wiring layer 50 arranged on the side of the first insulating layer 40 away from the substrate 10, a second insulating layer 60 arranged on the side of the second wiring layer 50 away from the substrate 10, and a pixel definition layer 70 arranged on the side of the second insulating layer 60 away from the substrate 10. Next, a cathode layer is arranged on the entire surface of the side of the pixel definition layer 70 away from the substrate. It should be noted that the cathode layer is not Figure 4 Shown in.

[0045] The first wiring layer 20 includes a first wiring portion 21, which is connected to the display area 100 and is used to transmit a VDD signal to the display area 100. The passivation layer 30 and the first insulating layer 40 are provided with openings in the area corresponding to the first wiring portion 21, so that part of the first wiring layer 20 is exposed through the openings. The second wiring layer 50 includes a second wiring portion 51, which is provided through the openings in the area corresponding to the first wiring portion 21 of the passivation layer 30, so that the second wiring portion 51 is provided on the side of the first wiring portion 21 away from the substrate 10, so that the second wiring portion 51 is connected to the display area 100 and is used to transmit a VDD signal to the display area 100. Then, the second insulating layer 60 covers the first insulating layer 40, the second wiring portion 51, and the passivation layer 30, and the second insulating layer 60 is also provided with openings in the area corresponding to the passivation layer 30 to form a leveling area of ​​the cathode layer in the non-display area.

[0046] Therefore, in the prior art, a passivation layer 30 made of an inorganic material is added to separate the cathode layer from the first wiring layer 20 along the AA direction to prevent the cathode layer from contacting the first wiring layer 20 and causing a short circuit. However, this design still has the problem that after the passivation layer 30 is over-etched in the subsequent process, the cathode layer contacts the first wiring layer 20 due to the evaporation deviation, thereby causing a short circuit.

[0047] Next, see Figure 3 as well as Figure 5 , Figure 5 for Figure 3 Schematic diagram of the cross section along the BB direction. Figure 5As shown, in the first wiring layer 20, a third wiring portion 22 is provided on a side away from the first wiring portion 21 along the BB direction. The passivation layer 30 is provided on a side of the first wiring layer 20 away from the substrate 10, and the passivation layer 30 is provided with an opening in a region corresponding to the third wiring portion 22. It should be noted that along the BB direction, the first insulating layer 40 is dug, so Figure 5 The first insulating layer 40 is not shown. Then the second wiring layer 50 also includes a fourth wiring portion 52, which is arranged in the opening of the passivation layer 30 in the area corresponding to the third wiring portion 22, so that the third wiring portion 22 is connected to the fourth wiring portion 52. Therefore, the third wiring portion 22 is connected to the display area 100 for transmitting a VSS signal to the display area 100; the fourth wiring portion 52 is connected to the display area 100 for transmitting a VSS signal to the display area 100. It should be noted that along the BB direction, the second insulating layer 60 is dug up, so Figure 5 The second insulating layer 60 is not shown.

[0048] Therefore, in the prior art, along the BB direction, the cathode layer is separated from the first wiring layer 20 by the passivation layer 30 and the fourth wiring portion 52. Since the fourth wiring portion 52 and the third wiring portion 22 transmit VSS signals, there is no problem of short circuit caused by the overlap of the cathode layer and the fourth wiring portion 52. Therefore, in the process of evaporating the cathode layer, even if there is an evaporation deviation, causing the cathode layer to contact the fourth wiring portion 52, there will be no risk of short circuit. In addition, the passivation layer 30 separates the first wiring portion 21 from the cathode layer to achieve the purpose of avoiding the cathode layer from contacting the first wiring portion 21 and causing a short circuit. However, this design still has the problem that after the passivation layer 30 is over-etched in the subsequent process, the cathode layer contacts the first wiring portion 21 based on the evaporation deviation. Since the first wiring portion 21 transmits the VDD signal, the cathode layer contacts the first wiring portion 21 and a short circuit occurs.

[0049] Therefore, in view of the defects and deficiencies in the aforementioned prior art, the present application provides a display panel to solve the short circuit problem caused by the cathode layer evaporation deviation.

[0050] In some embodiments provided in this application, please refer to Figures 1 to 3 as well as Figure 6 , Figure 6 This is a first cross-sectional view of a display panel provided in an embodiment of the present application along the AA direction in region F. Figures 1 to 3 as well as Figure 6 As shown, the display panel provided by the embodiment of the present application includes a display area 100 and a non-display area located outside the display area. The non-display area includes a binding area 200 located on one side of the display area 100 and a peripheral area 300 located between the display area 100 and the binding area 200.

[0051] Among them, the display area 100 includes a plurality of gate lines (not shown in the figure), a plurality of data lines (not shown in the figure) and a plurality of pixel units (not shown in the figure) defined by the gate lines and data lines that cross each other vertically and horizontally, and one pixel unit includes three sub-pixel units, and the three sub-pixel units are respectively a red sub-pixel, a blue sub-pixel and a green sub-pixel. One pixel unit may also include four sub-pixel units, and the four sub-pixel units are respectively a red sub-pixel, a blue sub-pixel, a green sub-pixel and a white sub-pixel. And the gate line of the display area 100 is connected to the GOA signal line (not shown in the figure) of the non-display area, and the data line of the display area is connected to the Data signal line (not shown in the figure) of the non-display area.

[0052] The peripheral area 300 of the non-display area includes a first fan-out area 301 , a bending area 302 , a second fan-out area 303 , an electrostatic protection area 304 and a driver chip area 305 which are sequentially arranged in a direction away from the display area 100 .

[0053] The first fan-out area 301 includes a first power line 310 and a second power line 320. The first power line 310 is located in the middle area of ​​the first fan-out area 301, and the second power line 320 is located on both sides of the first power line 310. The first fan-out area 301 is used to output a VDD signal and a VSS signal to the display area 100 through the first power line 310 and the second power line 320 respectively.

[0054] The bending area 302 is used to bend the binding area 200 to the back of the display area 100. The second fan-out area 303 leads multiple data connection lines to the driver chip area 305. The electrostatic protection area 304 includes an electrostatic protection circuit for preventing static electricity from damaging the display panel. The driver chip area 305 includes an integrated circuit chip for connecting to multiple data connection lines. The binding area 200 includes multiple binding pads for binding and connecting with a flexible circuit board.

[0055] along Figure 6 In the AA direction shown, the display panel includes: a substrate 10 , a first wiring layer 20 , a first insulating layer 40 , a second wiring layer 50 , and a second insulating layer 60 .

[0056] The substrate 10 includes a display area 100 and a non-display area located outside the display area 100. The substrate 10 may be a flexible substrate. The flexible substrate may be a multi-layer structure stacked in layers, such as a flexible material including polyimide (PI), polyethylene terephthalate (PET), etc.

[0057] The first wiring layer 20 is disposed on the substrate 10. Furthermore, the first wiring layer 20 includes a first wiring portion 21, and the first wiring portion 21 is located in the non-display area. Specifically, Figure 6It is shown that the first wiring portion 21 of this embodiment is located in the first fan-out area 301 of the non-display area.

[0058] It should be noted that a composite insulating layer ( Figure 6 The composite insulating layer includes a buffer layer, a gate insulating layer, and an interlayer dielectric layer arranged in sequence away from the substrate 10. The buffer layer is used to provide the substrate 10 with water and oxygen resistance, the gate insulating layer is used to separate the active layer and the gate layer, and the interlayer insulating layer is used to separate the gate layer and the source and drain layer.

[0059] The first insulating layer 40 is disposed on a side of the first wiring layer 20 away from the substrate 10, and the first insulating layer 40 includes a first insulating portion 41, and the first insulating portion 41 covers the first wiring portion 21. Thus, in the display panel provided in the embodiment of the present application, the first wiring portion 21 and the second wiring portion 51 are insulated and spaced apart by the first insulating portion 41.

[0060] The second wiring layer 50 is disposed on a side of the first insulating layer 40 away from the substrate 10, and the second wiring layer 50 includes a second wiring portion 51, and the second wiring portion 51 is disposed on a side of the first insulating portion 41 away from the substrate 10. Therefore, in the display panel provided in the embodiment of the present application, the second wiring portion 51 is stacked on the first wiring portion 21 through the first insulating portion 41.

[0061] It is worth mentioning that the first wiring portion 21 is connected to the display area 100 for transmitting a VDD signal to the display area 100 ; the second wiring portion 51 is connected to the display area 100 for transmitting a VSS signal to the display area 100 .

[0062] The second insulating layer 60 is disposed on a side of the second wiring layer 50 away from the substrate 10, and the second insulating layer 60 is provided with a first opening 601, and the first opening 601 is provided corresponding to the second wiring portion 51. Therefore, in the display panel provided in the embodiment of the present application, based on the provision of the first opening 601, during the process of evaporating the cathode layer, even if there is an evaporation deviation and the cathode layer overlaps in the first opening 601, there will be no problem of short circuit between the cathode layer and the first wiring portion 21.

[0063] Furthermore, if there is an over-etching problem of the first opening 601 during the subsequent preparation of the display panel, which causes the first insulating portion 41 to be thinned, the risk of isolation failure is also greatly reduced based on the fact that the first insulating layer 40 is a planarization layer and the planarization layer has a thickness greater than 1.5um. In addition, in the display panel provided in the embodiment of the present application, the second wiring portion 51 is stacked on the first wiring portion 21, thereby eliminating the provision of a passivation layer in the prior art, which can save a process compared to the prior art and thereby reduce production costs. On the other hand, the stacking design of the second wiring portion 51 and the first wiring portion 21 enables the first power wiring 310 and the second power wiring 320 to be stacked, thereby saving wiring space and being conducive to meeting the requirements of a narrow-frame display panel.

[0064] In some embodiments provided in this application, please refer to Figure 7 , Figure 7 This is a second cross-sectional view of the display panel provided in the embodiment of the present application along the AA direction in the region F. Figure 7 As shown, the difference between this embodiment and the previous embodiment is that the first insulating layer 40 is provided with a second opening 401 in a region close to the display area 100 , so that a portion of the first wiring portion 21 is exposed through the second opening 401 .

[0065] Next, see Figure 8 , Figure 8 This is a third cross-sectional view of the display panel provided in the embodiment of the present application along the AA direction in the region F. Figure 8 As shown, the second wiring layer 50 further includes a third wiring portion 52 , and the third wiring portion 52 is disposed in the second opening 401 , and the third wiring portion 52 is insulated from the second wiring portion 51 .

[0066] It is worth mentioning that in this embodiment, the second wiring portion 51 and the third wiring portion 52 are spaced apart from each other, that is, the second wiring portion 51 does not contact the third wiring portion 52 , thereby achieving insulation between the second wiring portion 51 and the third wiring portion 52 .

[0067] Therefore, in this embodiment, by setting the second opening 401 in the area of ​​the first insulating layer 40 close to the display area 100, the third wiring portion 52 of the second wiring layer 50 is set in the second opening 401, so that the third wiring portion 52 is set on the side of the first wiring portion 21 away from the substrate 10. Therefore, the third wiring portion 52 is connected to the first wiring portion 21, so the third wiring portion 52 is also connected to the display area 100, and is used to transmit the VDD signal to the display area 100. Therefore, in this embodiment, the first power wiring 310 is set in a double layer through the first wiring portion 21 and the third wiring portion 52, which reduces the load of the first power wiring 310 to a certain extent.

[0068] In some embodiments provided in this application, please refer to Fig. 9 , Fig. 9 This is a fourth cross-sectional view of the display panel provided in the embodiment of the present application along the AA direction in region F. Fig. 9 As shown, the difference between this embodiment and the above-mentioned embodiment is that the second wiring layer 50 also includes a fourth wiring portion 53. Among them, the fourth wiring portion 53 is connected to the third wiring portion 52, the fourth wiring portion 53 is overlapped on the side wall of the second opening 401, and the fourth wiring portion 53 extends to the side of the first insulating portion 41 away from the substrate 10. It should be noted that there is still a gap between the fourth wiring portion 53 and the second wiring portion 51, so that the fourth wiring portion 53 is insulated from the second wiring portion 51. Therefore, the fourth wiring portion 53 and the third wiring portion 52 are connected to the first wiring portion 21, so the fourth wiring portion 53 is also connected to the display area 100, and is used to transmit the VDD signal to the display area 100. Therefore, in this embodiment, the first power wiring 310 is double-layered through the first wiring portion 21, the third wiring portion 52 and the fourth wiring portion 53, which further reduces the load of the first power wiring 310.

[0069] In some embodiments provided in this application, please continue to refer to Fig. 9 ,like Fig. 9 As shown, the second insulating layer 60 further includes a second insulating portion 61, which covers the third routing portion 52, the fourth routing portion 53, the gap between the fourth routing portion 53 and the second routing portion 51, and a portion of the second routing portion 51 close to the gap.

[0070] In this embodiment, a second insulating portion 61 is provided to cover the side of the second wiring portion 51 near the gap, thereby preventing the side of the second wiring portion 51 from precipitating metal due to contact with water vapor. At the same time, the second insulating portion 61 also serves to separate the cathode layer from the third wiring portion 52 and the fourth wiring portion 53 to prevent the cathode layer from contacting the third wiring portion 52 and the fourth wiring portion 53 and causing a short circuit.

[0071] In some embodiments provided in this application, please continue to refer to Fig. 9 .like Fig. 9 As shown, the difference between this embodiment and the previous embodiment is that the second insulating layer 60 further includes a third insulating portion 62. The third insulating portion 62 is disposed on a side of the first opening 601 away from the display area 100, and the third insulating portion 62 covers a side of the second wiring portion 51 away from the display area 100, a side of the first insulating portion 41 away from the display area 100, and a side of the first wiring portion 21 away from the display area 100.

[0072] This embodiment is based on the provision of the third insulating portion 62 , so as to prevent the sides of the first wiring portion 21 and the second wiring portion 51 from precipitating metal due to contact with water vapor.

[0073] In some embodiments provided in this application, please refer to Fig.10 , Fig.10 The fifth cross-sectional view of the display panel provided in the embodiment of the application in the area F along the AA direction. Fig.10 As shown, the difference between this embodiment and the previous embodiment is that the second insulating layer 60 is further provided with a fourth opening 602. The fourth opening 602 is located on a side of the first opening 601 away from the display area 100, and a portion of the second wiring portion 51 is exposed through the fourth opening 602. Fig.10 The display panel provided in this embodiment further includes a pixel definition layer 70 and a cathode layer 80. The pixel definition layer 70 is disposed on a side of the second insulating layer 60 away from the substrate 10, and the cathode layer 80 is disposed on a side of the pixel definition layer 70 away from the substrate 10.

[0074] In this embodiment, based on the arrangement of the fourth opening 602 and the first opening 601 , the overflow risk caused by the inkjet printing process used to prepare pixels in the display area 100 is intercepted.

[0075] In some embodiments provided in this application, please refer to Fig.11 , Fig.11 A cross-sectional view of a display panel along the BB direction in region F provided in an embodiment of the application. Fig.11 As shown, the difference between this embodiment and the previous embodiment is that the first wiring layer 20 also includes a fifth wiring portion 22. The fifth wiring portion 22 and the first wiring portion 21 are arranged in a direction parallel to the edge of the display area 100 close to the non-display area. Therefore, the fifth wiring portion 22 arranged in the same layer as the first wiring portion 21 can also be connected to the display area 100, and the fifth wiring portion 22 is used to output a VSS signal to the display area. Figure 3 , Figures 6 to 11 It can be seen that in this embodiment, the second power line 320 is configured in a double layer through the fifth line portion 22 and the second line portion 51 , which reduces the load of the second power line 320 to a certain extent.

[0076] For further information, please refer to Fig.11, the first insulating portion 41 is provided with a third opening 402 in the area corresponding to the fifth wiring portion 22, so that part of the fifth wiring portion 22 is exposed through the third opening 402. Then, the second wiring portion 51 extends in a direction parallel to the edge of the display area 100 close to the non-display area, that is, the second wiring portion 51 extends in a direction parallel to the edge of the display area 100 close to the first fan-out area 301, so that the second wiring portion 51 overlaps the side of the fifth wiring portion 22 away from the substrate 10 through the third opening 402. Therefore, in this embodiment, the second wiring portion 51 overlaps the fifth wiring portion 22 through the third opening 402, which increases the area of ​​the second wiring portion 51 and further reduces the load of the second power wiring 320. In addition, this embodiment increases the overlapping area of ​​the orthographic projection of the second wiring portion 51 and the first wiring portion 21 on the substrate 10, so as to further reduce the problem of short circuit of the first wiring portion 21 caused by the cathode layer evaporation deviation.

[0077] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display panel, characterized in that: include: A substrate, the substrate comprising a display area and a non-display area located outside the display area; A first wiring layer, the first wiring layer is arranged on the substrate, the first wiring layer comprises a first wiring portion, and the first wiring portion is located in the non-display area; A first insulating layer, the first insulating layer is provided on a side of the first wiring layer away from the substrate, and the first insulating layer comprises a first insulating portion, and the first insulating portion covers the first wiring portion; A second routing layer, the second routing layer is arranged on a side of the first insulating layer away from the substrate, the second routing layer comprises a second routing portion, and the second routing portion is arranged on a side of the first insulating portion away from the substrate; A second insulating layer, wherein the second insulating layer is disposed on a side of the second wiring layer away from the substrate, and the second insulating layer is provided with a first opening, and the first opening is disposed corresponding to the second wiring portion; The first routing layer further includes a fifth routing portion; The fifth wiring portion and the first wiring portion are arranged in a direction parallel to the edge of the display area close to the non-display area. The first insulating portion is provided with a third opening in a region corresponding to the fifth wiring portion, and a portion of the fifth wiring portion is exposed through the third opening; The second wiring portion extends in a direction parallel to an edge of the display area close to the non-display area, and the second wiring portion is overlapped on a side of the fifth wiring portion away from the substrate through the third opening.

2. The display panel according to claim 1, characterized in that: The first insulating layer is provided with a second opening in a region close to the display area, and a portion of the first wiring portion is exposed through the second opening.

3. The display panel according to claim 2, characterized in that: The second routing layer also includes a third routing portion; The third wiring portion is disposed in the second opening, and the third wiring portion is insulated from the second wiring portion.

4. The display panel according to claim 3, characterized in that: The second routing layer further includes a fourth routing portion; The fourth routing portion is connected to the third routing portion, overlaps the side wall of the second opening and extends to a side of the first insulating portion away from the substrate, and a gap is left between the second routing portion and the fourth routing portion.

5. The display panel according to claim 4, characterized in that: The second insulating layer includes a second insulating portion, and the second insulating portion covers the third routing portion, the fourth routing portion, the gap, and a portion of the second routing portion close to the gap.

6. The display panel according to claim 1, characterized in that: The second insulating layer includes a third insulating portion, which is disposed on a side of the first opening away from the display area and covers a side edge of the second wiring portion, a side edge of the first insulating portion, and a side edge of the first wiring portion.

7. The display panel according to claim 1, characterized in that: The second insulating layer is further provided with a fourth opening, and the fourth opening is located at a side of the first opening away from the display area, and a portion of the second wiring portion is exposed through the fourth opening.

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