Semiconductor device and semiconductor device control method

Abstract

The present invention relates to a semiconductor device and a control method thereof. The semiconductor device comprises a first electrode, a second electrode, first to fifth semiconductor regions, and first and second gate electrodes. The first semiconductor region is arranged between the first electrode and the second electrode. The second semiconductor region is arranged between the first semiconductor region and the second electrode. The third semiconductor region is arranged between the first semiconductor region and the first electrode. The first gate electrode is opposite to the second semiconductor region via a first insulating film. The second gate electrode is opposite to the second semiconductor region via a second insulating film, and is opposite to the second electrode via a third insulating film that is in contact with the second insulating film. The fifth semiconductor region is arranged between the second semiconductor region and the second electrode, and is adjacent to the second gate electrode via a second or third insulating film, and has a boundary portion that is in electrical contact with the second electrode. The distance between the upper surface of the fourth semiconductor region and the first electrode is greater than the distance between the boundary portion and the first electrode.

Description

[0001] Related Application

[0002] This application claims priority from Japanese Patent Application No. 2021-66177 (filing date: April 9, 2021) and Japanese Patent Application No. 2021-120186 (filing date: July 21, 2021) as basic applications, and this application incorporates the entire contents of these basic applications by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for controlling the semiconductor device. Background Art

[0004] Semiconductor devices such as insulated gate bipolar transistors (IGBTs) are used as switching elements. To reduce the on-resistance of an IGBT, it is effective to increase the carrier concentration in the drift region when it is on. However, if the discharge of carriers from the drift region slows when the IGBT is turned off, the turn-off time becomes longer and switching losses increase.

[0005] Semiconductor devices are required to suppress element breakdown, reduce on-resistance, reduce switching loss, and the like. Summary of the Invention

[0006] Embodiments of the present invention provide a semiconductor device and a method for controlling the semiconductor device that can reduce switching loss and suppress element damage.

[0007] A semiconductor device according to an embodiment includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, a first gate electrode, and a second gate electrode. The second electrode is disposed in a first direction, spaced apart from the first electrode. A first semiconductor region of a first conductivity type is disposed between the first and second electrodes in the first direction. A second semiconductor region of a second conductivity type is disposed between the first semiconductor region and the second electrode. A third semiconductor region of a second conductivity type is disposed between the first semiconductor region and the first electrode and is electrically connected to the first electrode. A plurality of first gate electrodes are disposed opposite the second semiconductor region via a first insulating film in a second direction intersecting the first direction, and opposite the second electrode via a third insulating film in contact with the first insulating film. A plurality of second gate electrodes are disposed opposite the second semiconductor region via a second insulating film in a second direction, and opposite the second electrode via a third insulating film in contact with the second insulating film, and are applied with a different voltage than the first gate electrodes. A fourth semiconductor region of a first conductivity type is disposed between the second semiconductor region and the second electrode, and is adjacent to the first gate electrode via the first insulating film or the third insulating film. A fifth semiconductor region of the second conductivity type is disposed between the second semiconductor region and the second electrode, is adjacent to the second gate electrode via the second insulating film or the third insulating film, and has a boundary portion that is in electrical contact with the second electrode. A distance between an upper surface of the fourth semiconductor region and the first electrode is greater than a distance between the boundary portion and the first electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A It is a top view of the semiconductor device 100 according to the first embodiment. Figure 1B yes Figure 1A The cross-sectional view at line AA' is shown. Figure 1C It is a partial top view of the semiconductor device 100 according to the first embodiment. Figure 1D This is a schematic diagram of a semiconductor device circuit according to the first embodiment.

[0009] Figure 2 It is a diagram for explaining a driving method of the semiconductor device 100 according to the first embodiment.

[0010] Figure 3 is a cross-sectional view of a semiconductor device 500 according to a comparative example.

[0011] Figure 4 It is a cross-sectional view of a semiconductor device 101 according to a modified example of the first embodiment.

[0012] Figure 5 It is a cross-sectional view of a semiconductor device 200 according to a modification of the second embodiment.

[0013] Figure 6It is a cross-sectional view of a semiconductor device 201 according to a modified example of the second embodiment.

[0014] Figure 7 It is a cross-sectional view of a semiconductor device 300 according to the third embodiment.

[0015] Figure 8 It is a cross-sectional view of a semiconductor device 400 according to a fourth embodiment.

[0016] Figure 9 It is a top view of a semiconductor device 400 according to a fourth embodiment.

[0017] Figure 10 It is a cross-sectional view of the semiconductor device 100 according to the first embodiment.

[0018] Figure 11 It is a cross-sectional view of the semiconductor device 100 according to the first embodiment. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In this description, common reference numerals are used for common parts in all the drawings. Furthermore, the dimensional ratios in the drawings are not limited to those shown. Furthermore, this embodiment does not limit the present invention.

[0020] [First embodiment]

[0021] (Structure of Semiconductor Device 100)

[0022] Regarding the semiconductor device 100 of the first embodiment, refer to Figures 1A to 1D Provide explanation. Figure 1A is a top view of the semiconductor device 100 according to the first embodiment. Figure 1B yes Figure 1A The cross-sectional view of the line AA' is shown. Figure 1C is a partial top view of the semiconductor device 100 according to the first embodiment. Figure 1D This is a schematic diagram of a semiconductor device circuit according to the first embodiment.

[0023] The semiconductor device of the first embodiment is a trench gate IGBT having a gate electrode formed in a trench formed in a semiconductor layer. The semiconductor device 100 of the first embodiment is an IGBT capable of dual gate drive. The following description takes the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. In the following description, n + 、n、n - and p + ,p,p - The mark indicates the relative high and low of the impurity concentration in each conductivity type. +Compared with n, the n-type impurity concentration is relatively high. - Indicates that the impurity concentration of n-type is relatively low compared to n. + Compared with p type, the impurity concentration of p type is relatively high. - Indicates that the p-type impurity concentration is relatively low compared to the p-type. + Type, n - Type is referred to as n-type, p-type + Type, p - Type is referred to as p-type.

[0024] The semiconductor device 100 of the first embodiment includes a collector electrode (first electrode) 11, an emitter electrode (second electrode) 12, a first gate electrode 13, a second gate electrode 14, a first gate electrode pad 21, a second gate electrode pad 22, and a first gate electrode pad 23. - p-type drift region (first semiconductor region) 31, p-type base region (second semiconductor region) 32, p-type collector region (third semiconductor region) 33, n + n-type emitter region (fourth semiconductor region) 34, n-type buffer region 35, p + type contact region (fifth semiconductor region) 36, a first gate insulating film (first insulating film) 51, a second gate insulating film (second insulating film) 52, and an interlayer insulating film (third insulating film) 53.

[0025] In semiconductor device 100 , the direction from collector electrode 11 toward emitter electrode 12 is referred to as Z direction (first direction), the direction perpendicular to Z direction is referred to as X direction (second direction), and the direction perpendicular to X and Z directions is referred to as Y direction. Figure 1A 、 Figure 1C and Figure 1D The semiconductor device 100 shown is a top view taken along the XY plane. Figure 1B The semiconductor device 100 shown is a cross-sectional view taken along the XZ plane. While the X, Y, and Z directions are shown as being orthogonal in this embodiment, they are not limited to being orthogonal; any intersecting directions are acceptable. For purposes of illustration, the direction from the collector electrode 11 toward the emitter electrode 12 is referred to as "up," and the opposite direction is referred to as "down."

[0026] The collector electrode 11 is provided apart from the emitter electrode 12 in the Z direction. A collector voltage is applied to the collector electrode 11. The collector voltage is, for example, 200 V or more and 6500 V or less.

[0027] An emitter voltage is applied to the emitter electrode 12. The emitter voltage is 0V, for example.

[0028] The collector electrode 11 and the emitter electrode 12 can be made of, for example, aluminum (Al).

[0029] The collector region 33 is a p-type semiconductor region provided in the Z direction between the collector electrode 11 and the emitter electrode 12. The collector region 33 is in contact with and electrically connected to the collector electrode 11. The collector region 33 serves as a source of holes when the semiconductor device 100 is in the on state.

[0030] The drift region 31 is provided between the collector region 33 and the emitter electrode 12. - The drift region 31 serves as a path for conducting current when the semiconductor device 100 is in the on state. When the semiconductor device 100 is in the off state, the drift region 31 is depleted by a depletion layer extending from the interface with the base region 32, thereby maintaining the breakdown voltage of the semiconductor device 100.

[0031] The base region 32 is a p-type semiconductor region provided between the drift region 31 and the emitter electrode 12. The base region 32 forms an inversion layer when the semiconductor device 100 is in the on state, and functions as a channel region of the transistor.

[0032] The buffer region 35 is an n-type semiconductor region provided between the collector region 33 and the drift region 31. The buffer region 35 has the function of suppressing the extension of the depletion layer extending from the base region 32 to the drift region 31 when the semiconductor device 100 is in the off state. In this embodiment, a configuration without the buffer region 35 may also be employed.

[0033] The contact region 36 is provided between the base region 32 and the emitter electrode 12. + The contact region 36 is in contact with the second gate insulating film 52 and separated from the first gate insulating film 51 as described later. The contact region 36 is in contact with the emitter electrode 12 and is electrically connected to the emitter electrode 12.

[0034] The first gate trench 41 penetrates the base region 32 and reaches the drift region 31. A first gate insulating film 51 is provided at the bottom and sides of the first gate trench 41. The first gate insulating film 51 is in contact with the drift region 31, the base region 32, and the emitter region 34. The first gate insulating film 51 is made of silicon oxide, for example.

[0035] The first gate electrode 13 is provided in the first gate insulating film 51 and is opposed to the base region 32 at least through the first gate insulating film 51. The first gate electrode 13 is electrically connected to the first gate electrode pad 21 described later. The first gate electrode 13 is, for example, polysilicon containing impurities. Figure 1A and Figure 1CAs shown, the first gate electrode 13 has a stripe shape extending in the Y direction and provided in plurality in the X direction. The first gate electrode 13 is, for example, polysilicon containing impurities.

[0036] The second gate trench 42 penetrates the base region 32 and reaches the drift region 31. The second gate trench 42 is provided between adjacent first gate trenches 41 in the X direction. A second gate insulating film 52 is provided at the bottom and sides of the second gate trench 42. The second gate insulating film 52 contacts the drift region 31, the base region 32, and the contact region 36. The second gate insulating film 52 is made of silicon oxide, for example.

[0037] The second gate electrode 14 is provided in the second gate insulating film 52. The second gate electrode 14 is provided in a manner not adjacent to the emitter region 34 in the X direction. The second gate electrode 14 is electrically connected to the second gate electrode pad 22. As with the first gate insulating film 51, Figure 1A and Figure 1C As shown, the second gate electrode 14 has a stripe shape extending in the Y direction and provided in plurality in the X direction. The second gate electrode 14 is, for example, polysilicon containing impurities.

[0038] The interlayer insulating film 53 is provided between the base region 32 and the emitter electrode 12 , between the first gate electrode 13 and the emitter electrode 12 , and between the second gate electrode 14 and the emitter electrode 12 .

[0039] The emitter region 34 is provided between the base region 32 and the interlayer insulating film 53. + type semiconductor region. In addition, Figure 1B In FIG. 5 , an interlayer insulating film 53 is provided between the entire upper surface of the emitter region 34 and the emitter electrode 12. However, Figure 10 、 Figure 11 As shown, the entire or a portion of the upper surface of the emitter region 34 is provided in direct contact with the emitter electrode 12. A portion of the emitter region 34 is in contact with and electrically connected to the emitter electrode 12. The emitter region 34 is in contact with the first gate insulating film 51 and is separated from the second gate insulating film 52. The emitter region 34 serves as a source of electrons when the transistor having the first gate electrode 13 is in the on state.

[0040] The distance from the collector electrode 11 along the Z direction to the boundary where the contact region 36 and the emitter electrode 12 contact each other is referred to as distance 1 (L1). The distance from the collector electrode 11 along the Z direction to the upper surface of the emitter region 34 is referred to as distance 2 (L2). In the semiconductor device 100 of this embodiment, distance 1 is smaller than distance 2. That is, the interlayer insulating film 53 provided in the first gate trench 41 is located closer to the emitter electrode 12 than the interlayer insulating film 53 provided in the second gate trench 42.

[0041] Furthermore, the interface between the emitter electrode 12 and the contact region 36 is located closer to the collector electrode 11 than the interface between the emitter region 34 and the interlayer insulating film 53 . Therefore, the side portion of the emitter region 34 is in contact with the emitter electrode 12 .

[0042] The drift region 31 , the base region 32 , the collector region 33 , the emitter region 34 , the buffer region 35 , and the contact region 36 are made of, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

[0043] In addition, instead of providing one first gate electrode 13 and one second gate electrode 14 alternately in the X direction as shown in FIG. 1 , a plurality of first gate electrodes 13 and second gate electrodes 14 may be arranged alternately.

[0044] Here, if Figure 1A As shown in FIG, the region where the channel of the IGBT is formed, that is, the region where the current flows, is defined as a cell region 60. Figure 1A In FIG, the cell region 60 is the region surrounded by a dot-dashed line. The region surrounding the cell region 60, where no channel is formed, is defined as the end region 61. In the X direction, the portion of the cell region 60 that is closest to the end region 61 is defined as the cell end portion of the cell region 60, while the portion of the cell region 60 that is closest to the end region 61 is defined as the cell center portion.

[0045] The first gate electrode pad 21 is provided in the terminal region of the semiconductor device 100 and is provided on the emitter electrode 12 side in the Z direction. A first gate voltage (Vg1) is applied to the first gate electrode pad 21 and the first gate electrode 13 .

[0046] The second gate electrode pad 22 is provided in the terminal region of the semiconductor device 100 and is provided on the emitter electrode 12 side in the Z direction. The second gate electrode pad 22 is provided separately from the first gate electrode pad 21. A second gate voltage (Vg2) is applied to the second gate electrode pad 22 and the second gate electrode 14.

[0047] like Figure 1DAs shown, the first gate electrode pad 21 and the second gate electrode pad 22 are electrically connected to the gate driver 70. The gate driver 70 controls the voltage applied to the first gate electrode pad 21 and the second gate electrode pad 22. The gate driver 70 applies a first gate voltage (Vg1) to the first gate electrode pad 21 and a second gate voltage (Vg2) to the second gate electrode pad 22.

[0048] (Operation of Semiconductor Device 100)

[0049] The operation of the semiconductor device 100 will be described.

[0050] Figure 2 2 is a timing chart of a first gate voltage ( Vg1 ) applied to the first gate electrode pad 21 and a second gate voltage ( Vg2 ) applied to the second gate electrode pad 22 . Figure 2 The vertical axis represents the voltage applied to the first gate voltage (Vg1) and the second gate voltage (Vg2). Figure 2 The horizontal axis represents time, and time passes in the order of time t0, time t1 (first timing), time t2 (second timing), time t3 (third timing), and time t4.

[0051] In the off state of the semiconductor device 100 , an emitter voltage is applied to the emitter electrode 12 . The emitter voltage is, for example, 0 V. A collector voltage is applied to the collector electrode 11 . The collector voltage is, for example, 200 V or more and 6500 V or less.

[0052] From time t0 to time t1, semiconductor device 100 is in the off state. When semiconductor device 100 is in the off state, an off voltage (Voff) is applied to first gate electrode pad 21. That is, from time t0 to time t1, first gate voltage (Vg1) is the off voltage (Voff). The off voltage (Voff) is a voltage lower than the threshold voltage (Vth) at which an n-type inversion layer forms in base region 32 in contact with first gate insulating film 51, and is, for example, 0V or a negative voltage.

[0053] An initial voltage (V0) is applied to the second gate electrode pad 22. That is, from time t0 to time t1, the second gate voltage (Vg2) is the initial voltage (V0). The initial voltage (V0) is a voltage at which no p-type inversion layer is formed in the drift region 31 in contact with the second gate insulating film 52, and is, for example, 0V or a positive voltage.

[0054] At time t1, semiconductor device 100 turns on. At time t1, an on-voltage (Von) is applied to first gate electrode pad 21, turning semiconductor device 100 on. The on-voltage (Von) is a positive voltage exceeding the threshold voltage (Vth), for example, 15V. That is, at time t1, first gate voltage (Vg1) reaches the on-voltage (Von). At this point, an n-type inversion layer forms in base region 32 in contact with first gate insulating film 51, turning semiconductor device 100 on.

[0055] From time t1 to time t3, semiconductor device 100 is in the on-state. That is, during the period from time t1 to time t3, the first gate voltage (Vg1) becomes the on-state voltage (Von). In the on-state, electrons are injected from emitter region 34 into base region 32 (n-type inversion layer), and then flow through drift region 31, buffer region 35, collector region 33, and collector electrode 11 in this order. Meanwhile, holes are injected from collector region 33 into buffer region 35, and then flow through drift region 31, base region 32, emitter region 34 or contact region 36, and emitter electrode 12 in this order.

[0056] At time t1, a first voltage (V1) is applied to the second gate electrode pad 22. The first voltage (V1) is, for example, 0V or a positive voltage. That is, at time t1, the second gate voltage (Vg2) becomes the first voltage (V1). The first voltage (V1) may also be the same as the initial voltage (V0).

[0057] At time t3, semiconductor device 100 is turned off. At time t3, an off-voltage (Voff) is applied to first gate electrode pad 21, and semiconductor device 100 enters an off-state. That is, after time t3, first gate voltage (Vg1) becomes the off-voltage (Voff).

[0058] Time t2 is the timing before the voltage of the first gate electrode pad 21 changes from the on-voltage (Von) to the off-voltage (Voff), that is, before time t3. At time t2, the second gate voltage (Vg2) switches from the first voltage (V1) to the second voltage (V2). The second voltage (V2) is a negative voltage, for example, greater than -15V and less than 0V. As a result, a p-type inversion layer is formed in the drift region 31 in contact with the second gate insulating film 52. Holes in the drift region 31 are discharged toward the emitter electrode 12 through the p-type inversion layer.

[0059] The time between time t2 and time t3 is, for example, 0.1 microseconds to 10 microseconds.

[0060] Finally, at time t4 , the second gate voltage ( Vg2 ) is set to the initial voltage ( V0 ).

[0061] (Effects of the First Embodiment)

[0062] Regarding the effects of the semiconductor device 100 according to the first embodiment, Figure 3 A semiconductor device 500 according to the comparative example shown will be described.

[0063] Figure 3 A cross-sectional view of a semiconductor device 500 according to a comparative example is shown. Components identical to those of the semiconductor device 100 according to the first embodiment are denoted by the same reference numerals.

[0064] The semiconductor device 500 of the comparative example differs from the semiconductor device 100 of the first embodiment in that the distance 1 ( L1 ) and the distance 2 ( L2 ) are the same.

[0065] In the semiconductor device 100 of the first embodiment and the semiconductor device 500 of the comparative example, the second gate voltage (Vg2) is changed from the first voltage (V1) to the second voltage (V2) at time t2. At this time, a p-type inversion layer is formed in the drift region 31 in contact with the second gate insulating film 52. From time t2 to time t3, holes pass through the drift region 31 and the p-type inversion layer and are discharged toward the emitter electrode 12.

[0066] Here, in the semiconductor device 100 of the first embodiment, distance 1 is smaller than distance 2. Therefore, the distance holes travel through the drift region 31 and the p-type inversion layer between time t2 and time t3 is smaller than that of the semiconductor device 500 of the comparative example. In other words, in the semiconductor device 100 of the first embodiment, the resistance of the path through which holes travel through the drift region 31 and the p-type inversion layer is reduced. Therefore, the semiconductor device 100 of the first embodiment can efficiently discharge holes to the emitter electrode 12, thereby reducing switching losses during turn-off.

[0067] Furthermore, in the semiconductor device 100 of the first embodiment and the semiconductor device 500 of the comparative example, holes tend to concentrate in the drift region 31, which contacts the bottom of the second gate trench 42. These concentrated holes can cause a dynamic avalanche phenomenon, which reduces the breakdown voltage and can damage the semiconductor device. In the semiconductor device 100 of the first embodiment, the concentrated holes are more effectively discharged through the contact region than in the semiconductor device 500. Consequently, the breakdown resistance of the semiconductor device is improved.

[0068] As described above, according to the semiconductor device 100 of the first embodiment, it is possible to achieve reduction in switching loss and improvement in breakdown resistance.

[0069] [Modification of the First Embodiment]

[0070] Regarding the semiconductor device 101 according to the modified example of the first embodiment, refer to Figure 4 Provide explanation. Figure 4 A cross-sectional view of a semiconductor device 101 according to a modification of the first embodiment is shown. Detailed descriptions of points that overlap with those of the first embodiment are omitted.

[0071] Semiconductor device 101 differs from semiconductor device 100 in that the length of second gate electrode 14 in the Z direction is the same as the length of first gate electrode 13. However, in semiconductor device 101, as in semiconductor device 100, distance 1 is smaller than distance 2. Therefore, the distance holes travel in drift region 31 and p-type inversion layer between time t2 and time t3 is smaller than that in semiconductor device 500. Therefore, semiconductor device 101 can achieve the same effects as semiconductor device 100.

[0072] [Second embodiment]

[0073] Regarding the semiconductor device 200 of the second embodiment, refer to Figure 5 Provide explanation. Figure 5 A cross-sectional view of a semiconductor device 200 according to a second embodiment is shown.

[0074] The semiconductor device 200 of the second embodiment differs from the semiconductor device 100 in that at least one of the plurality of first gate electrodes 13 provided in the semiconductor device 100 is replaced with a dummy electrode 15. In the semiconductor device 200, the base region 32 provided between the second gate electrode 14 and the dummy electrode 15 is insulated from the emitter electrode 12 by an interlayer insulating film 53 provided on the base region 32. In other words, in the semiconductor device 200, only the second gate insulating film 52, the drift region 31, and the base region 32 are formed between the second gate electrode 14 and the dummy electrode 15. Details overlapping with the first embodiment are omitted here.

[0075] The dummy electrode 15 is electrically connected to, for example, the emitter electrode 12. That is, the dummy electrode 15 and the emitter electrode 12 have the same potential.

[0076] The dummy electrodes 15 do not function as gate electrodes. Therefore, by varying the number of dummy electrodes 15, the semiconductor device 200 can adjust the channel density. Changing the channel density is related to adjusting the on-state voltage and off-state loss. Therefore, by varying the number of dummy electrodes 15, the semiconductor device 200 can appropriately adjust the on-state voltage and off-state loss.

[0077] Furthermore, the dummy electrode 15 of semiconductor device 200 is connected to the emitter electrode 12. Even when the dummy electrode 15 is floating, the channel density can be adjusted. However, when the dummy electrode 15 is floating, potential instability of the dummy electrode 15 may cause malfunction and heat generation in semiconductor device 200. On the other hand, when the dummy electrode 15 is at the emitter potential, malfunction and heat generation in semiconductor device 200 can be suppressed. Therefore, degradation of device characteristics in semiconductor device 200 can be suppressed.

[0078] Furthermore, the dummy electrode 15 can adjust the channel density even at the gate potential. While the dummy electrode 15 at the gate potential may reduce switching speed due to increased gate capacitance, it can suppress voltage and current variations between the collector electrode 11 and the emitter electrode 12. Consequently, the semiconductor device 200 with the dummy electrode 15 at the gate potential can suppress surge voltage and surge current.

[0079] Furthermore, in the semiconductor device 200, the drift region 31 and the base region 32 located between the second gate electrode 14 and the dummy electrode 15 are insulated from the emitter electrode 12 by the interlayer insulating film 53. Therefore, holes are not discharged from the drift region 31 and the base region 32 located between the second gate electrode 14 and the dummy electrode 15 but are accumulated. As a result, the semiconductor device 200 can reduce the on-state voltage.

[0080] The semiconductor device 200 of the second embodiment is similar to the semiconductor device 100 of the first embodiment, except for the points described above. Distance 1 is smaller than distance 2. Therefore, holes are efficiently discharged to the emitter electrode 12, reducing switching losses during turn-off. Furthermore, as with the semiconductor device 100 of the first embodiment, damage to the semiconductor element caused by holes generated by dynamic avalanche can be suppressed.

[0081] In addition, Figure 5 In FIG. 1 , one dummy electrode 15 is shown as being sandwiched between the second gate electrodes 14 , but a plurality of dummy electrodes 15 may be provided.

[0082] In addition, Figure 5 In the embodiment, there are two base regions 32 provided between the second gate electrode 14 and the dummy electrode 15, and these are insulated from the emitter electrode 12 by the interlayer insulating film 53 provided on the base regions 32. However, any one of the multiple base regions 32 provided between the second gate electrode 14 and the dummy electrode 15 may be connected to the emitter electrode 12 that penetrates the interlayer insulating film 53. In this case, the effects described above can be adjusted by varying the contact area with the emitter electrode 12.

[0083] [Modification of the Second Embodiment]

[0084] Regarding the semiconductor device 201 according to the modified example of the second embodiment, refer to Figure 6 Provide explanation. Figure 6 A cross-sectional view of a semiconductor device 201 according to a modification of the second embodiment is shown. Detailed descriptions of points that overlap with those of the second embodiment are omitted.

[0085] In a semiconductor device 201 according to a modified example of the second embodiment, at least one of the plurality of second gate electrodes 14 provided in the first embodiment is replaced with a dummy electrode 15. In semiconductor device 201, the base region 32 provided between the first gate electrode 13 and the dummy electrode 15 is insulated from the emitter electrode 12 by an interlayer insulating film 53 provided on the base region 32. In other words, in semiconductor device 201, only the first gate insulating film 51, the drift region 31, and the base region 32 are formed between the first gate electrode 13 and the dummy electrode 15. Details overlapping with those in the first embodiment are omitted here.

[0086] Semiconductor device 201, like semiconductor device 200 of the second embodiment, has dummy electrodes 15 that do not function as gate electrodes. Therefore, semiconductor device 200 can appropriately adjust the on-state voltage and off-state loss by adjusting the number of dummy electrodes 15. Furthermore, semiconductor device 200 can suppress degradation of device characteristics. Furthermore, semiconductor device 200 can reduce the on-state voltage.

[0087] Furthermore, as with the semiconductor device 100 of the first embodiment, distance 1 is smaller than distance 2. Therefore, holes in the semiconductor device 200 are efficiently discharged to the emitter electrode 12, reducing switching losses during turn-off. Furthermore, the semiconductor device 200 improves the breakdown resistance of the semiconductor element due to dynamic avalanche.

[0088] [Third embodiment]

[0089] Regarding the semiconductor device 300 of the third embodiment, refer to Figure 7 Provide explanation. Figure 7 A cross-sectional view of a cell region 60 near a terminal region 61 of a semiconductor device 300 according to the third embodiment is shown. Figure 7 The configuration of the device region is shown, with the left side of the drawing indicating the end region 61. Details overlapping with those in the second embodiment are omitted.

[0090] The semiconductor device 300 of the third embodiment has a dummy electrode 15 provided in the cell region 60 near the terminal region 61 in the second embodiment. In the semiconductor device 300, the base region 32 provided between the second gate electrode 14 and the dummy electrode 15 is insulated from the emitter electrode 12 by the interlayer insulating film 53 provided on the base region 32. That is, in the semiconductor device 300, only the second gate insulating film 52, the drift region 31, and the base region 32 are formed between the second gate electrode 14 and the dummy electrode 15. Details overlapping with those in the first embodiment are omitted here. Furthermore, the second gate electrode 14 adjacent to the dummy electrode 15 is adjacent to the contact region 36 in the X direction via the second gate insulating film 52 and is electrically connected to the emitter electrode 12, which penetrates the interlayer insulating film 53.

[0091] In the termination region 61 , holes expand during the on-state. During the off-state, holes gather near the second gate electrode 14 in the termination region 61 and are discharged, causing a local increase in current density. This can potentially damage the semiconductor device.

[0092] On the other hand, the semiconductor device 300 of the third embodiment includes a dummy electrode 15 in the cell region 60 near the terminal region 61. Furthermore, the second gate electrode 14 adjacent to the dummy electrode 15 is adjacent to the contact region 36 in the X direction via the second gate insulating film 52, and is electrically connected to the emitter electrode 12 that penetrates the interlayer insulating film 53. Therefore, holes in the terminal region 61 are easily discharged during shutdown.

[0093] Furthermore, the drift region 31 and the base region 32 located between the second gate electrode 14 and the dummy electrode 15 are insulated from the emitter electrode 12 by the interlayer insulating film 53. Therefore, holes are not discharged from the drift region 31 and the base region 32 located between the second gate electrode 14 and the dummy electrode 15 but are accumulated. As a result, the semiconductor device 300 can not only reduce the on-state voltage but also suppress the concentration of holes on the second gate electrode 14 near the terminal region 61 during the off state.

[0094] In semiconductor device 300, similar to semiconductor device 200 of the second embodiment, dummy electrodes 15 do not function as gate electrodes. Therefore, semiconductor device 300 can appropriately adjust the on-state voltage and off-state loss by adjusting the number of dummy electrodes 15. Furthermore, semiconductor device 300 can suppress degradation of device characteristics. Furthermore, semiconductor device 300 can reduce the on-state voltage.

[0095] Furthermore, as with the semiconductor device 100 of the first embodiment, distance 1 is smaller than distance 2. Therefore, holes in the semiconductor device 300 are efficiently discharged to the emitter electrode 12, reducing switching losses during turn-off. Furthermore, the semiconductor device 300 improves the breakdown resistance of the semiconductor element due to dynamic avalanche.

[0096] [Fourth embodiment]

[0097] Regarding the semiconductor device 400 of the fourth embodiment, refer to Figure 8 Provide explanation. Figure 8 A cross-sectional view of a cell region 60 near a terminal region 61 of a semiconductor device 400 according to the fourth embodiment is shown. Figure 8 The structure of the device region is shown, and the left side of the paper is the end region 61 side. Figure 9 It is a top view of a semiconductor device 400 according to a fourth embodiment. Figure 9 Only the outer edge of the semiconductor device 400 and the second gate electrode 14 are schematically shown, and other components are omitted. In addition, the second gate electrode 14 is shown in gray for easier viewing. Here, the points that overlap with the first embodiment are omitted.

[0098] The semiconductor device 400 of the fourth embodiment differs from the semiconductor device 100 of the first embodiment in that a plurality of second gate electrodes 14 are formed in the cell region 60 near the terminal region 61. Specifically, in the semiconductor device 400, a higher proportion of the second gate electrodes 14 are formed in the cell region 60 near the terminal region 61 than in the central region of the cell region 60.

[0099] As described above, the semiconductor device 400 includes a cell region 60 and a termination region 61. The termination region 61 surrounds the cell region 60. The first gate electrode 13 and the second gate electrode 14 are arranged in the cell region 60. Furthermore, in the cell region 60, the second gate electrodes 14 are arranged at a higher density in the regions at both ends in the X direction (second direction) than in the region in the center in the X direction.

[0100] Therefore, if the distance between the first second gate electrode 14a, which is closest to the terminal region 61 in the X direction (second direction) among the plurality of second gate electrodes 14 arranged in the cell region 60, and the second second gate electrode 14b arranged next to the first second gate electrode 14a is defined as a first distance D1, and the distance between the third second gate electrode 14c, which is arranged closer to the center of the cell region 60 than the second second gate electrode 14b, and the fourth second gate electrode 14d arranged next to the third second gate electrode 14c is defined as a second distance D2, then the first distance D1 is shorter than the second distance D2. Furthermore, when the cell region 60 is rectangular in shape when viewed from the Z direction, the center of the cell region 60 is the intersection of the diagonals of the cell region 60, and, for example, substantially coincides with the intersection of the diagonals of the semiconductor device 400.

[0101] The semiconductor device 400 of the fourth embodiment has multiple second gate electrodes 14 formed on the cell region 60 side. This facilitates the discharge of holes present in the terminal region 61 during shutdown, further preventing an increase in current density. Consequently, the semiconductor device 400 can suppress damage to the semiconductor element.

[0102] The semiconductor device 400 of the fourth embodiment is similar to the semiconductor device 100 of the first embodiment, except for the points described above. Distance 1 is smaller than distance 2. Therefore, holes in the semiconductor device 400 are efficiently discharged to the emitter electrode 12, reducing switching losses during turn-off. Furthermore, the semiconductor device 400 improves the breakdown resistance of the semiconductor element due to dynamic avalanche.

[0103] According to the embodiments, a semiconductor device and a method for controlling the semiconductor device can be provided, which can reduce switching loss and suppress element destruction.

[0104] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention and are within the scope of the invention set forth in the claims and their equivalents.

Claims

1. A semiconductor device comprising: a first electrode; a second electrode disposed in a first direction and separated from the first electrode; a first semiconductor region of a first conductivity type, disposed between the first electrode and the second electrode in the first direction; a second semiconductor region of a second conductivity type, disposed between the first semiconductor region and the second electrode; a third semiconductor region of the second conductivity type, disposed between the first semiconductor region and the first electrode and electrically connected to the first electrode; a plurality of first gate electrodes, facing the second semiconductor region via a first insulating film in a second direction intersecting the first direction, and facing the second electrode via a third insulating film in contact with the first insulating film; a plurality of second gate electrodes, opposed to the second semiconductor region via a second insulating film in the second direction, and opposed to the second electrode via a third insulating film in contact with the second insulating film, wherein a different voltage is applied to the plurality of second gate electrodes than to the first gate electrode; a fourth semiconductor region of the first conductivity type, provided between the second semiconductor region and the second electrode, and adjacent to the first gate electrode via the first insulating film or the third insulating film; as well as a fifth semiconductor region of the second conductivity type, provided between the second semiconductor region and the second electrode, adjacent to the second gate electrode via the second insulating film or the third insulating film, and having a boundary portion electrically in contact with the second electrode; A distance between an upper surface of the fourth semiconductor region and the first electrode is greater than a distance between the boundary portion and the first electrode.

2. The semiconductor device according to claim 1, wherein The second conductivity type impurity concentration of the fifth semiconductor region is higher than the second conductivity type impurity concentration of the second semiconductor region.

3. The semiconductor device according to claim 1, wherein Also features: a first gate electrode pad electrically connected to the first gate electrode; and The second gate electrode pad is electrically connected to the second gate electrode.

4. The semiconductor device according to claim 1, wherein The area in which the fifth semiconductor region contacts the second electrode, which is located between the first first gate electrode and the first gate electrode or the second gate electrode adjacent to the first first gate electrode, is different from the area in which the fifth semiconductor region contacts the second electrode, which is located between the second first gate electrode and the first gate electrode or the second gate electrode adjacent to the second first gate electrode.

5. The semiconductor device according to claim 1, wherein The second semiconductor region located between the first gate electrode and the first gate electrode or the second gate electrode adjacent to the first gate electrode is electrically insulated from the second electrode. The semiconductor device according to claim 1 , wherein: At least one of the plurality of first gate electrodes is electrically connected to the second electrode.

7. The semiconductor device according to claim 1, wherein have: a cell region having the first gate electrode and the second gate electrode; and The terminal region, surrounding the unit region, The first gate electrode provided on the end region side in the second direction is connected to the second electrode, The second gate electrode, which is adjacent to the first gate electrode connected to the second electrode, is adjacent to the fifth semiconductor region via the second insulating film.

8. The semiconductor device according to claim 1, wherein have: a cell region having the first gate electrode and the second gate electrode; and The terminal region, surrounding the unit region, A first distance between a first second gate electrode, which is closest to the end region in the second direction, among the plurality of second gate electrodes arranged in the unit region, and a second second gate electrode arranged next to the first second gate electrode is shorter than a second distance between a third second gate electrode, which is arranged closer to the center side of the unit region than the second second gate electrode, and a fourth second gate electrode arranged next to the third second gate electrode.

9. The semiconductor device according to claim 7, wherein The cell region having a smaller distance from the terminal region in the second direction is provided with more second gate electrodes than the cell region having a larger distance from the terminal region in the second direction.

10. A method for controlling a semiconductor device, the method for controlling a semiconductor device according to claim 1, At a first timing, changing a first gate voltage applied to the first gate electrode from a voltage lower than a threshold voltage to a voltage higher than the threshold voltage; At a second timing immediately following the first timing, changing a second gate voltage applied to the second gate electrode from the first voltage to a second voltage; At a third timing immediately following the second timing, the first gate voltage is changed from a voltage equal to or higher than the threshold voltage to a voltage lower than the threshold voltage.

11. The method for controlling a semiconductor device according to claim 10, wherein: When the first conductivity type is an n-type, the second voltage is a negative voltage. When the first conductivity type is a p-type, the second voltage is a positive voltage.

12. The method for controlling a semiconductor device according to claim 10, wherein: By applying the second voltage to the second gate electrode, an inversion layer is formed in the first semiconductor region in contact with the second insulating film.

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