Semiconductor device

Abstract

The present application provides a semiconductor device, comprising: a substrate; a first deep well disposed in the substrate; a first well disposed in the first deep well; a second well disposed in the substrate adjacent to the first well with a non-zero distance; a third well disposed in the substrate, the second well disposed between the first well and the third well; a fourth well disposed in the substrate; a source region and a drain region disposed in the fourth well and the first well, respectively; a body region disposed in the third well; a gate structure disposed on the substrate between the source region and the drain region; a first isolation structure disposed on the first deep well between the gate structure and the drain region; a second isolation structure disposed on the fourth well between the gate structure and the source region; and a top doped region disposed in the first deep well below the first isolation structure. The present application can reduce the electric field between the edge of the gate structure and the source region, and improve the breakdown voltage.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a high-voltage semiconductor device. Background Technology

[0002] High-voltage semiconductor devices must have a high breakdown voltage to operate. However, current high-voltage semiconductor devices cannot effectively improve the breakdown voltage because the electric field between the edge of the gate structure and the source region is much greater than that in other parts of the device. Summary of the Invention

[0003] This invention relates to a method that can reduce the electric field between the edge of the gate structure and the source region, thereby improving the breakdown voltage of semiconductor devices.

[0004] According to an embodiment of the present invention, a semiconductor device includes: a substrate having a first conductivity type; a first deep well having a second conductivity type and disposed in the substrate; a first well having the second conductivity type and disposed in the first deep well; a second well having the first conductivity type and disposed in the substrate, adjacent to the first well at a non-zero distance; a third well having the first conductivity type and disposed in the substrate, wherein the second well is disposed between the first well and the third well; a fourth well having the second conductivity type and disposed in the substrate, disposed between the second well and the third well and adjacent to the second well and the third well; a source region and a drain region having the second conductivity type, wherein the drain region is disposed... The source region is disposed in the first well, and the source region is disposed in the fourth well; the substrate region, having the first conductivity type, is disposed in the third well; the gate structure is disposed on the fourth well, the second well, the substrate, and the first deep well between the source region and the drain region; the first isolation structure is disposed on the first deep well between the gate structure and the drain region; the second isolation structure is disposed on the fourth well between the gate structure and the source region, wherein the gate structure covers a portion of the first isolation structure and extends to the covered portion of the second isolation structure; and the top-doped region is disposed in the first deep well below the first isolation structure and has the first conductivity type.

[0005] According to an embodiment of the present invention, a semiconductor device includes: a substrate having a first conductivity type; a first well having a second conductivity type and disposed in the substrate; a second well and a third well having the first conductivity type and disposed in the substrate, wherein the second well is located between the first well and the third well; a fourth well having the second conductivity type and disposed in the substrate, disposed between the second well and the third well and adjacent to the second well and the third well; a source region and a drain region having the second conductivity type, the drain region being disposed in the first well and the source region being disposed in the fourth well; a substrate region having the first conductivity type and disposed in the third well; and a gate structure disposed on the substrate between the source region and the drain region, wherein the gate structure includes a gate dielectric layer, a gate conductive layer located on the gate dielectric layer, and a plurality of spacers located on the sidewalls of the gate conductive layer, wherein the spacers closer to the source region are separated from the source region by a non-zero distance.

[0006] Based on the above, the semiconductor device of the present invention sets the source region and drain region in a well having the same conductivity type and sets an isolation structure between the gate structure and the source region, which can reduce the electric field between the gate structure and the source region and transfer the weakness to the interface between the well where the source region is located and the well where the substrate region is located, thereby improving the breakdown voltage of the semiconductor device. Attached Figure Description

[0007] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0008] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0009] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0010] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention. Detailed Implementation

[0011] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0012] In the following embodiments, the first conductivity type is P-type and the second conductivity type is N-type; however, the invention is not limited thereto. In other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type. The P-type doping is, for example, boron, and the N-type doping is, for example, phosphorus or arsenic.

[0013] The schematic diagrams in this document are merely illustrative of embodiments of some parts of the invention. Therefore, the shape, number, and scale of the various devices shown in the schematic diagrams should not be used to limit the invention.

[0014] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to the first embodiment of the present invention.

[0015] Please refer to Figure 1 In this embodiment, the semiconductor device 100A is, for example, a high-voltage device, whose operating voltage can be above 40V, for example, 40V to 50V. In one embodiment, the semiconductor device 100A includes a substrate 10, a first deep well 12, a first well 20, a second well 22, a third well 24, a fourth well 26, a top-doped region 30, a drain region 32, a source region 34, a substrate region 36, a gate structure 40, and an isolation structure 50.

[0016] Substrate 10 is, for example, a semiconductor substrate having a first conductivity type. For instance, in this embodiment, substrate 10 is a P-type substrate, and the material of substrate 10 may be, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. In another embodiment, substrate 10 may also be a silicon-on-insulator (SOI) substrate. In yet another embodiment, substrate 10 may be a P-type epitaxial (P-epi) wafer. In yet another embodiment, substrate 10 may also be an epitaxial layer.

[0017] A first deep well 12, having a second conductivity type, is disposed in a substrate 10. A first well 20, having a second conductivity type, is disposed in the first deep well 12. A second well 22, having the first conductivity type, is disposed in the substrate 10 and is adjacent to the first deep well 12 at a non-zero distance d1. A third well 24, having a first conductivity type, is disposed in the substrate 10, wherein the second well 22 is located between the first deep well 12 and the third well 26. A fourth well 26, having the second conductivity type, is disposed in the substrate 10 and is located between the second well 22 and the third well 24, with its sidewalls adjacent to and in contact with the second well 22 and the third well 24, respectively. In some embodiments, the first deep well 12 is, for example, an N-type deep well; the first well 20 and the fourth well 26 are, for example, N-type wells; and the second well 22 and the third well 24 are, for example, P-type wells. The first deep well 12 can be formed by a patterned mask and an ion implantation process.

[0018] The first well 20 and the fourth well 26 can be formed simultaneously in the first deep well 12 and the substrate 10 using patterned masks and ion implantation processes, respectively. The second well 22 and the third well 24 can be formed simultaneously in the substrate 10 using patterned masks and ion implantation processes.

[0019] An isolation structure 50 is disposed on the substrate 10. The isolation structure 50 is, for example, a field oxidation isolation structure. The isolation structure 50 includes isolation structures 50a, 50b, 50c, 50d, and 50e. Isolation structure 50a is located on the first well 20, the first deep well 12, and the substrate 10. Isolation structure 50b is located on the first well 20 and extends to the first deep well 12. Isolation structure 50c is located on the fourth well 26. Isolation structure 50d is located on the third well 24 and extends to the fourth well 26. Isolation structure 50e is located on the third well 24 and extends to the substrate 10. Isolation structures 50a, 50b, 50c, 50d, and 50e can be formed simultaneously by a field oxidation isolation process.

[0020] Source region 34 and drain region 32 have a second conductivity type. Source region 34 and drain region 32 are, for example, N-type doped regions. In this embodiment, drain region 32 is located in first well 20. Source region 34 is located in fourth well 26. That is, source region 34 and drain region 32, as well as the first well 20 and fourth well 26 in which they are located, all have the same conductivity type, namely, the second conductivity type. Drain region 32 is located between isolation structures 50a and 50b. Source region 34 is located between isolation structures 50c and 50d. Source region 34 and drain region 32 can be simultaneously formed in first well 20 and fourth well 26 using patterned masks and ion implantation processes, respectively.

[0021] The substrate region 36 has a first conductivity type. The substrate region 36 is, for example, a p-type doped region. The substrate region 36 is located within the third well 24. That is, both the substrate region 36 and the third well 24 it contains have the same conductivity type, namely the first conductivity type. The substrate region 36 is also located between the isolation structures 50d and 50e. The substrate region 36 can be formed using a patterned mask and ion implantation processes.

[0022] A gate structure 40 is disposed on a fourth well 26, a second well 22, a substrate 10, a first deep well 12, and a first well 20 between a source region 34 and a drain region 32. The gate structure 40 includes a gate dielectric layer 42, a gate conductive layer 44, and spacers 46. The gate conductive layer 44 is located on the gate dielectric layer 42 and extends to cover a portion of the isolation structure 50b and a portion of the isolation structure 50c. The spacers 46 include spacers 46a and 46b, respectively located on the sidewalls of the gate conductive layer 44 and on the isolation structure 50b and a portion of the isolation structure 50c. The materials of the gate dielectric layer 42 and the spacers 46 are, for example, silicon oxide, silicon nitride, or combinations thereof. The material of the gate conductive layer 44 is, for example, a metal or its alloy, polysilicon, or a combination thereof. The gate structure 40 can be formed by first forming a gate dielectric material layer and a blanket-type gate conductive material layer on the substrate 10, and then patterning the gate dielectric layer 42 and the gate conductive layer 44 using photolithography and etching processes. Next, a blanket-like spacer material layer is formed, and then an anisotropic etching process is used to form spacer 46.

[0023] The top-doped region 30 has the first conductivity type. The top-doped region 30 is, for example, a P-type top-doped region. The top-doped region 30 is disposed in a first deep well 12 below the isolation structure 50b. In some embodiments, the sidewalls of the top-doped region 30 may be adjacent to and in contact with the sidewalls of the first well 20. In other embodiments, the top-doped region 30 may partially overlap with the first well 20 laterally. The top-doped region 30 may be formed in the first deep well 12 prior to the formation of the isolation structure 50 by a patterned mask and ion implantation process.

[0024] The drain region 32, source region 34, substrate region 36, and gate conductive layer 44 can be electrically connected via contacts 62, 64, 66, 68 and metal lines 72, 74, 76, 78 of metal layer 70, respectively. Contacts 62, 64, 66, 68 and metal layer 70 can be formed by any known metallization process.

[0025] In embodiments of the present invention, the source region 34 and the spacer 46a are separated by a non-zero distance d2 through the isolation structure 50c. Furthermore, the source region 34 is disposed within a fourth well 26 having the same conductivity type. Therefore, the electric field between the gate structure 40 and the source region 34 can be reduced, improving channel leakage current. Moreover, the weak point can be shifted to the interface between the fourth well 26 and the third well 24, where interface failure occurs, thus enabling a depletion-type device. In some embodiments, the breakdown voltage can be increased to above 40V, for example, 53V, through the isolation structure 50c and the fourth well 26.

[0026] Please refer to Figure 2 and Figure 3 In this embodiment, semiconductor devices 100B and 100C are, for example, high-voltage devices, with an operating voltage of 40V or higher, such as 40V to 50V. The constituent components of semiconductor devices 100B and 100C are similar to those of semiconductor device 100A, the difference being that the fourth well 26 includes multiple sub-wells. The fourth well 26 may include a first sub-well 26a and a second sub-well 26b, such as... Figure 2 As shown. The fourth well 26 may include a first sub-well 26a, a second sub-well 26b, and a third sub-well 26c, as follows. Figure 3 As shown. However, the fourth well 26 of the present invention is not limited thereto, and may include more sub-wells.

[0027] Please refer to Figure 2The fourth well 26 may include a first sub-well 26a and a second sub-well 26b. The sidewall of the first sub-well 26a is adjacent to and in contact with the sidewall of the second well 26b. The sidewall of the second sub-well 26b is adjacent to and in contact with the sidewall of the third well 24. The first sub-well 26a and the second sub-well 26b are separated by a slot. That is, the first sub-well 26a and the second sub-well 26b are separated from each other by a non-zero distance d3. The distance d3 is, for example, 0.3 micrometers to 4 micrometers. The source region 34 is located in the second sub-well 26b and extends continuously into the substrate 10 between the first sub-well 26a and the second sub-well 26b. An isolation structure 50c is disposed on the first sub-well 26a and extends continuously into the substrate 10 between the first sub-well 26a and the second sub-well 26b. An isolation structure 50d is disposed on the second sub-well 26b and the third well 24. The gate structure 40 covers the isolation structure 50c, the first sub-well 26a, the second well 22, the substrate 10, the first deep well 12, and the isolation structure 50b.

[0028] Please refer to Figure 3 The fourth well 26 may include a first sub-well 26a, a second sub-well 26b, and a third sub-well 26c. The first sub-well 26a, second sub-well 26b, and third sub-well 26c are separated from each other by slots. In some embodiments, the first sub-well 26a, second sub-well 26b, and third sub-well 26c are arranged in a grid pattern. The sidewall of the first sub-well 26a is adjacent to and in contact with the sidewall of the second well 22. The sidewall of the second sub-well 26b is adjacent to and in contact with the sidewall of the third well 24. The third sub-well 26c is located between the first sub-well 26a and the second sub-well 26b and is separated from each other by non-zero distances d4 and d5, respectively. Distances d4 and d5 may be equal or different. Distances d4 and d5 are, for example, 0.2 micrometers to 3 micrometers, respectively. The source region 34 is located in the second sub-well 26b and extends continuously into the third sub-well 26c. An isolation structure 50c is disposed on the first sub-well 26a and extends continuously into the substrate 10 between the first sub-well 26a and the third sub-well 26c. An isolation structure 50d is disposed on the second sub-well 26b and the third well 24. The gate structure 40 covers the isolation structure 50c, the first sub-well 26a, the second well 22, the substrate 10, the first deep well 12, and the isolation structure 50b.

[0029] In semiconductor devices 100B and 100C, the fourth well 26 is modified into multiple sub-wells (e.g., 26a, 26b, 26c) to further alter the breakdown voltage from the source region 34 to the substrate region 36 by generating an architecture alternating between P-type and N-type regions, i.e., NPN and NPNPN architectures. In some embodiments, the breakdown voltage from the source region 34 to the substrate region 36 can be adjusted by changing the distances d3, d4, and d5.

[0030] The method for forming multiple sub-wells (e.g., 26a, 26b, 26c) of semiconductor devices 100B and 100C is similar to that of the fourth well 26 of semiconductor device 100, which can change the patterning of the implantation mask and then be formed by ion implantation process.

[0031] Please refer to Figure 4 In this embodiment, the semiconductor device 100D is, for example, a high-voltage device, whose operating voltage can be above 40V, for example, 40V to 50V. The components of the semiconductor device 100D are similar to those of the semiconductor device 100A, the difference being that it also includes a second deep well 14, a fifth well 28, and a ground doped region 38.

[0032] The second deep well 14 has the second conductivity type. The second deep well 14 is, for example, an N-type deep well. The second deep well 14 is disposed in the substrate 10 and is adjacent to the first deep well 12 at a non-zero distance d6. The second well 22, the third well 24, and the fourth well 26 are located in the second deep well 14. The fifth well 28 has the first conductivity type. The fifth well 28 is, for example, a P-type well. The fifth well 28 is disposed in the substrate 10 and is adjacent to and in contact with the sidewall of the second deep well 14. The ground doped region 38 has the first conductivity type. The ground doped region 38 is, for example, a P-type doped region. The ground doped region 38 is located in the fifth well 28. The ground doped region 38 and the fifth well 28 both have the same conductivity type, namely the first conductivity type. The ground doped region 38 is electrically connected to the metal line 79 of the metal layer 70 through the contact 69.

[0033] In semiconductor device 100D, the presence of a second deep well 14 makes it an isochannel device; in semiconductor devices 100A, 100B, and 100C, the absence of a second deep well 14 makes them non-isochannel devices. The isochannel device 100D can have its breakdown voltage altered by controlling the distance d6 between the second deep well 14 and the first deep well 12. For example, the starting voltage V of the non-isochannel device 100A... th The initial voltage (Ion) of the semiconductor device 100D is 0.92V, and the breakdown voltage is 546V. When the isolation channel device distance d6 is controlled at 20 micrometers, the Ion channel device Ion of the semiconductor device 100D has an Ion voltage of 0.84V and a breakdown voltage of 303V. When the isolation channel device distance d6 of the semiconductor device 100D is controlled at 30 micrometers, the semiconductor device has an Ion voltage of 0.84V and a breakdown voltage of 546V. The results show that appropriately controlling the distance d6 between the second deep well 14 and the first deep well 12 can effectively improve the breakdown voltage of the semiconductor device.

[0034] In embodiments of the present invention, by providing an isolation structure between the source region and the spacer, the source region and the spacer can be separated by a non-zero distance. Furthermore, the source region is disposed in a fourth well having the same conductivity type. Therefore, the electric field between the gate structure and the source region can be reduced, improving the leakage current of the channel. Moreover, the weakness can be shifted to the interface between the fourth well and the third well, where interface failure occurs, thereby increasing the breakdown voltage of the semiconductor device.

[0035] Furthermore, by placing the source region and substrate region within a second deep well, an isolated channel device can be formed. By controlling the distance between the second deep well and the first deep well, the breakdown voltage of the semiconductor device can be effectively improved.

[0036] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, include: The substrate has a first conductivity type; A first deep well having a second conductivity type is disposed in the substrate; A first well, having the second conductivity type, is disposed within the first deep well; The second well has the first conductivity type and is disposed in the substrate, and is adjacent to the first well at a non-zero distance; A third well has the first conductivity type and is disposed in the substrate, wherein the second well is disposed between the first well and the third well; A fourth well, having the second conductivity type and disposed in the substrate, is disposed between the second well and the third well and is adjacent to the second well and the third well; The source region and the drain region have the second conductivity type, the drain region is disposed in the first well, and the source region is disposed in the fourth well; The substrate region, having the first conductivity type, is disposed in the third well; A gate structure is disposed on the fourth well, the second well, the substrate, and the first deep well between the source region and the drain region; A first isolation structure is disposed on the first deep well between the gate structure and the drain region; A second isolation structure is disposed on the fourth well between the gate structure and the source region, wherein the gate structure covers the first isolation structure and extends to the second isolation structure covering the second isolation structure. The top-doped region is disposed in the first deep well below the first isolation structure and has the first conductivity type; as well as A second deep well, having the second conductivity type and disposed in the substrate, is adjacent to the first deep well at a non-zero distance, wherein the second well, the third well, and the fourth well are disposed in the second deep well. The second deep well is in contact with the bottom of the second well, the third well, and the fourth well.

2. The semiconductor device according to claim 1, characterized in that, The fourth well comprises multiple sub-wells that are separate from each other.

3. The semiconductor device according to claim 2, characterized in that, The plurality of sub-wells includes: The first sub-well, adjacent to the second well; and The second sub-well is adjacent to the third sub-well and separate from the first sub-well. The source region is disposed in the second sub-well and extends into a portion of the substrate between the first sub-well and the second sub-well, and the second isolation structure is disposed on the first sub-well and extends into another portion of the substrate between the first sub-well and the second sub-well.

4. The semiconductor device according to claim 3, characterized in that, The plurality of sub-wells also includes a third sub-well disposed between the first sub-well and the second sub-well, wherein the first sub-well and the second sub-well are separated, and the source region extends into the third sub-well.

5. The semiconductor device according to claim 4, characterized in that, The first sub-well, the second sub-well, and the third sub-well are arranged in a grid pattern.

6. The semiconductor device according to claim 1, characterized in that, Also includes: The fifth well, having the first conductivity type, is disposed in the substrate and adjacent to the second deep well; as well as A grounded doped region, having the first conductivity type, is disposed in the fifth well.

7. A semiconductor device, characterized in that, include: The substrate has a first conductivity type; A first well, having a second conductivity type, is disposed in the substrate; A second well and a third well, having the first conductivity type, are disposed in the substrate, wherein the second well is located between the first well and the third well; A fourth well, having the second conductivity type and disposed in the substrate, is disposed between the second well and the third well and is adjacent to the second well and the third well; The source region and the drain region have the second conductivity type, the drain region is disposed in the first well, and the source region is disposed in the fourth well; The substrate region, having the first conductivity type, is disposed in the third well; A gate structure is disposed on the substrate between the source region and the drain region, wherein the gate structure includes a gate dielectric layer, a gate conductive layer located on the gate dielectric layer, and a plurality of spacers located on the sidewall of the gate conductive layer, wherein the spacers closer to the source region are separated from the source region by a non-zero distance. as well as A first deep well and a second deep well, adjacent to each other at a non-zero distance, have the second conductivity type and are disposed in the substrate. The first well is disposed in the first deep well. The second well, the third well, and the fourth well are disposed within the second deep well. The second deep well is in contact with the bottom of the second well, the third well, and the fourth well.

8. The semiconductor device according to claim 7, characterized in that, It also includes an isolation structure disposed between the source region, the gate conductive layer, and the spacer.

9. The semiconductor device according to claim 7, characterized in that, The fourth well comprises multiple sub-wells that are separate from each other.

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