An edge-emitting semiconductor laser and a method of manufacturing the same

Abstract

This invention provides a side-emitting semiconductor laser and its fabrication method. The side-emitting semiconductor laser includes: a semiconductor substrate layer; an active layer located on the semiconductor substrate layer; a first semiconductor cladding layer located on the active layer, the first semiconductor cladding layer including a ridge region; a plurality of first etching trenches located in the ridge region, the plurality of first etching trenches being arranged at intervals along the light emission direction; and a plurality of oxide layer groups located in the ridge region, each oxide layer group being arranged at intervals, each oxide layer group corresponding to one of the first etching trenches, each oxide layer group including at least one oxide layer located around the first etching trench, the sidewalls of the oxide layers arranged in the light emission direction protruding outwards, and the refractive index of the oxide layers being less than the refractive index of the ridge region between adjacent oxide layers in the light emission direction. The side-emitting semiconductor laser can amplify the fundamental mode and suppress higher-order modes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a side-emitting semiconductor laser and its fabrication method. Background Technology

[0002] An edge-emitting laser chip is a type of semiconductor laser. By applying a forward voltage to the chip and continuously injecting current (external excitation), electrons and holes recombine in the active region to generate stimulated emission photons. These stimulated emission photons oscillate repeatedly within the resonant cavity between the front and rear cavity surfaces, simultaneously exciting more stimulated emission photons, thus amplifying the light. When the photon gain exceeds a threshold, it can be emitted from the front cavity surface to form a laser beam. Due to stimulated emission, the optical properties of the photons are highly consistent, resulting in lasers exhibiting better monochromaticity and directionality, as well as higher brightness, compared to ordinary light sources (sunlight, incandescent lamps, LEDs, etc.). Because of their excellent optical characteristics, small size, low cost, and simple packaging, edge-emitting laser chips have been widely used in industrial processing, communications, sensing, and medical fields.

[0003] In the field of communications, long-distance core network transmission and transoceanic transmission require lasers as the information carrier. As the transmission distance increases, the laser signal gradually attenuates, necessitating an optical amplifier (EDFA) to amplify the signal under the action of a pump source. This pump source needs to provide single-mode laser (single transverse mode), with single-mode optical power typically in the hundreds of mW range. This pump source is generally a side-emitting laser chip. To achieve single-mode output, the stripewidth of the laser chip (i.e., the ridge waveguide width) needs to be narrowed to 3-4 micrometers, but this significantly limits the improvement of single-mode power. To increase optical power, the stripewidth of the laser chip needs to be expanded, but this leads to multimode generation, which cannot meet the requirements. Summary of the Invention

[0004] In view of this, the present invention provides a side-emitting semiconductor laser and its fabrication method to solve the problem in the prior art that it is impossible to simultaneously amplify the fundamental mode and suppress higher-order modes in a side-emitting semiconductor laser.

[0005] This invention provides a side-emitting semiconductor laser, comprising: a semiconductor substrate layer; an active layer located on the semiconductor substrate layer; a first semiconductor cladding layer located on the active layer, the first semiconductor cladding layer including a ridge region; a plurality of first etching trenches located in the ridge region, the plurality of first etching trenches being arranged at intervals along the light emission direction; and a plurality of oxide layer groups located in the ridge region, each oxide layer group being arranged at intervals, each oxide layer group corresponding to one of the first etching trenches, each oxide layer group including at least one oxide layer, the oxide layer being located around the first etching trenches, the sidewalls of the oxide layer arranged in the light emission direction protruding outwards, and the refractive index of the oxide layer being less than the refractive index of the ridge region between adjacent oxide layers in the light emission direction.

[0006] Optionally, each of the oxide layer groups includes a plurality of oxide layers spaced apart in a direction perpendicular to the surface of the semiconductor substrate.

[0007] Optionally, the projection pattern of the sidewalls of the first etching trench arranged in the light emission direction on the surface of the semiconductor substrate includes an ellipse or an olive shape.

[0008] Optionally, the first semiconductor cladding includes: an upper confinement layer and an upper waveguide layer, the upper waveguide layer being located between the upper confinement layer and the active layer; a first etch trench being located in the upper confinement layer and not extending into the upper waveguide layer, and the oxide layer being located in the upper confinement layer; or, the first etch trench being located in the upper confinement layer and the upper waveguide layer, and the oxide layer being located only in the upper confinement layer; or, the first etch trench being located in the upper confinement layer and the upper waveguide layer, with a portion of the oxide layer located in the upper confinement layer and a portion of the oxide layer located in the upper waveguide layer.

[0009] Optionally, the maximum width of the first etching groove in the light emission direction is 3 micrometers to 30 micrometers.

[0010] Optionally, it may also include a filling layer located in the first etching tank, the filling layer material including Si, Si3N4, SiO2, Al2O3, ZnSe or photosensitive benzocyclobutene.

[0011] Optionally, the thickness of each oxide layer is 0.01 micrometers to 0.05 micrometers.

[0012] Optionally, the projection of the sidewalls of the oxide layer arranged in the light-emitting direction onto the surface of the semiconductor substrate layer is arc-shaped.

[0013] Optionally, the maximum size of the ridge region between adjacent oxide layers in the light-emitting direction is 0.1 mm to 0.5 mm along the light-emitting direction.

[0014] Optionally, the difference between the width of the ridge region and the dimension of the first etching groove along the slow axis is greater than or equal to 10 micrometers.

[0015] Optionally, the dimension of the first etched groove along the slow axis direction is greater than or equal to 5 micrometers.

[0016] Optionally, the radius of curvature of the sidewalls of the oxide layer arranged in the light-emitting direction is 0.1 mm to 10 mm.

[0017] Optionally, the difference between the refractive index of the ridge region between adjacent oxide layers and the refractive index of the oxide layer is 0.003 to 0.01.

[0018] Optionally, the material of the oxide layer includes aluminum oxide.

[0019] Optionally, the width of the ridge region is 90um to 300um.

[0020] The present invention also provides a method for fabricating a side-emitting semiconductor laser, comprising: providing a semiconductor substrate layer; forming an active layer on the semiconductor substrate layer; forming a first semiconductor cladding layer on the side of the active layer away from the semiconductor substrate layer, the first semiconductor cladding layer including a ridge region; forming a plurality of first etching trenches spaced apart along the light emission direction in the ridge region; forming a plurality of oxide layer groups in the ridge region, each oxide layer group being spaced apart, the oxide layer group corresponding one-to-one with the first etching trenches, the step of forming any one of the oxide layer groups including forming at least one oxide layer, the oxide layer being located around the first etching trenches, the sidewalls of the oxide layer arranged in the light emission direction protruding outward, the refractive index of the oxide layer being less than the refractive index of the ridge region between adjacent oxide layers in the light emission direction.

[0021] Optionally, the step of forming the oxide layer group includes: forming a plurality of oxide layers spaced apart in a direction perpendicular to the surface of the semiconductor substrate layer.

[0022] Optionally, the first semiconductor cladding includes: an upper confinement layer and an upper waveguide layer, the upper waveguide layer being located between the upper confinement layer and the active layer; the step of forming a plurality of first etch trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etch trenches spaced apart along the light emission direction in the upper confinement layer; the step of forming at least one oxide layer includes: forming an oxide layer in the upper confinement layer; or, the step of forming a plurality of first etch trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etch trenches spaced apart along the light emission direction in the upper confinement layer and the upper waveguide layer; the step of forming at least one oxide layer includes: forming a plurality of first etch trenches spaced apart along the light emission direction in the upper confinement layer and the upper waveguide layer; The step of forming an oxide layer in the confinement layer; or, forming a plurality of first etched trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etched trenches spaced apart along the light emission direction in the upper confinement layer and the upper waveguide layer; the step of forming at least one oxide layer includes: forming an oxide layer in the upper waveguide layer; or, forming a plurality of first etched trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etched trenches spaced apart along the light emission direction in the upper confinement layer and the upper waveguide layer; the step of forming at least one oxide layer includes: forming a partial oxide layer in the upper confinement layer and forming a partial oxide layer in the upper waveguide layer.

[0023] The technical solution provided by this invention has the following effects:

[0024] The edge-emitting semiconductor laser provided by this invention uses a ridge region between adjacent oxide layers in the light-emitting direction as a first lens region. Multiple first lens regions are cascaded along the extension direction of the ridge region, and second lens regions are formed between adjacent front cavity surfaces and oxide layers, as well as between adjacent rear cavity surfaces and oxide layers. The presence of multiple first and second lens regions makes the resonant cavities of the front and rear cavity surfaces selective for light modes. These multiple first and second lens regions amplify and diverge the light in the resonant cavity. The angle between higher-order mode light and the optical axis in the resonant cavity is larger than the angle between the fundamental mode light and the optical axis. Under the action of multiple first and second lens regions, the angle between the higher-order mode light and the optical axis is further amplified, making the higher-order mode light prone to scattering and escaping, thus increasing the loss of the higher-order mode light. When the gain of the active layer is sufficiently large, the fundamental mode along the optical axis can be lased in the resonant cavity, while other higher-order modes cannot be lased due to excessive loss, thereby achieving the effect of amplifying the fundamental mode while suppressing higher-order modes.

[0025] Secondly, the combination of oxide layer and first etching tank reduces the requirements for process technology and minimizes process stability fluctuations, thereby improving yield and reliability. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a side-emitting semiconductor laser according to an embodiment of the present invention;

[0028] Figure 2 For along Figure 1 Cross-sectional view of the tangent line M-N;

[0029] Figure 3 For the corresponding Figure 2 Top view;

[0030] Figures 4 to 9 This is a schematic diagram of the fabrication process of an edge-emitting semiconductor laser in one embodiment of the present invention;

[0031] Figures 10 to 12 This is a schematic diagram of the optical path in a side-emitting semiconductor laser according to one embodiment of the present invention. Detailed Implementation

[0032] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0035] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0036] This embodiment provides a side-emitting semiconductor laser, in conjunction with a reference. Figure 1 , Figure 2 and Figure 3 ,include:

[0037] Semiconductor substrate layer 100;

[0038] The active layer 130 is located on the semiconductor substrate layer 100;

[0039] A first semiconductor cladding layer is located on the active layer 130, the first semiconductor cladding layer including a ridge region A;

[0040] A plurality of first etching grooves 201 located in the ridge region A (reference) Figure 7 The plurality of first etching trenches are arranged at intervals along the light emission direction;

[0041] A plurality of oxide layer groups are located in the ridge region A, and each oxide layer group is arranged at intervals. Each oxide layer group corresponds to a first etching groove. Each oxide layer group includes at least one oxide layer 210. The oxide layer 210 is located around the first etching groove. The sidewalls of the oxide layer 210 arranged in the light emission direction protrude outward. The refractive index of the oxide layer 210 is less than the refractive index of the ridge region A between adjacent oxide layers 210 in the light emission direction.

[0042] It should be noted that the light emission direction refers to the length extension direction of the ridge region A, which is perpendicular to both the slow axis and fast axis of the side-emitting semiconductor laser.

[0043] The edge-emitting semiconductor laser has a front cavity surface and a rear cavity surface arranged opposite each other, with the reflectivity of the rear cavity surface being greater than that of the front cavity surface. Light is emitted from the front cavity surface.

[0044] In this embodiment of the edge-emitting semiconductor laser, the ridge region A between adjacent oxide layers 210 in the light-emitting direction serves as the first lens region. Multiple first lens regions are cascaded along the extension direction of the ridge region, and second lens regions are formed between adjacent front cavity surfaces and oxide layers, as well as between adjacent rear cavity surfaces and oxide layers. The presence of multiple first and second lens regions makes the resonant cavities of the front and rear cavity surfaces selective for light modes. The multiple first and second lens regions amplify and diverge the light in the resonant cavity. The angle between higher-order mode light and the optical axis in the resonant cavity is larger than the angle between the fundamental mode light and the optical axis. Under the action of the multiple first and second lens regions, the angle between the higher-order mode light and the optical axis is further amplified, making the higher-order mode light prone to scattering and escaping, increasing the loss of the higher-order mode light. When the gain of the active layer is sufficiently large, the fundamental mode along the optical axis can be lased in the resonant cavity, while other higher-order modes cannot be lased due to excessive loss, thus achieving the effect of amplifying the fundamental mode while suppressing higher-order modes.

[0045] Secondly, the combination of oxide layer and first etching tank reduces the requirements for process technology and minimizes process stability fluctuations, thereby improving yield and reliability.

[0046] The edge-emitting semiconductor laser further includes a filling layer 200 located in the first etching trench. The filling layer material includes Si, Si3N4, SiO2, Al2O3, ZnSe, or photosensitive benzocyclobutene. The filling layer 200 has a stable structure, is non-conductive, and has a certain degree of heat dissipation.

[0047] The first semiconductor cladding includes an upper confinement layer 150 and an upper waveguide layer 140, with the upper waveguide layer 140 located between the upper confinement layer 150 and the active layer 130.

[0048] The edge-emitting semiconductor laser further includes a lower confinement layer 110 and a lower waveguide layer 120 located on the semiconductor substrate layer 100, with the lower waveguide layer 120 located between the lower confinement layer 110 and the active layer 130.

[0049] refer to Figure 3 The projection pattern of the sidewalls of the first etching trench arranged in the light emission direction on the surface of the semiconductor substrate 100 is elliptical. Correspondingly, the projection pattern of the sidewalls of the filling layer 200 arranged in the light emission direction on the surface of the semiconductor substrate 100 is elliptical.

[0050] In other embodiments, the projection pattern of the sidewalls of the first etching trench arranged in the light emission direction on the surface of the semiconductor substrate 100 is olive-shaped, and the projection pattern of the sidewalls of the filling layer 200 arranged in the light emission direction on the surface of the semiconductor substrate 100 is olive-shaped.

[0051] In one embodiment, the first etching trenches are arranged periodically along the light emission direction, that is, the spacing between the first etching trenches is equal. In other embodiments, the first etching trenches may also be arranged non-periodically.

[0052] The depth of each first etching trench is less than or equal to the thickness of the first semiconductor cladding.

[0053] It should be noted that, in one embodiment, the size and shape of each first etching trench are identical. The size and shape of each oxide layer are also identical.

[0054] In one embodiment, the maximum width of the first etching groove in the light emission direction is 3 micrometers to 30 micrometers, for example, 3 micrometers, 5 micrometers, 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers or 30 micrometers.

[0055] In this embodiment, each oxide layer group includes a plurality of oxide layers 210 spaced apart in a direction perpendicular to the surface of the semiconductor substrate 100. That is, any oxide layer group includes a plurality of oxide layers 210 spaced apart in the longitudinal direction. The advantage of this is that the total equivalent refractive index of the region where the plurality of spaced oxide layers 210 are located in the direction perpendicular to the surface of the semiconductor substrate 100 is reduced, thereby reducing the difference between the total equivalent refractive index of the region where the plurality of oxide layers 210 are located in the longitudinal direction and the refractive index of the first lens region, which is helpful for reducing the loss of higher-order modes.

[0056] For details, please refer to Figure 2 Any oxide layer group may include two oxide layers 210 arranged at intervals in the longitudinal direction. Alternatively, any oxide layer group may include three or more oxide layers arranged at intervals in the longitudinal direction.

[0057] In other instances, any group of oxide layers comprises an oxide layer arranged at intervals in the longitudinal direction.

[0058] In this embodiment, the first etching trench is located in the upper confinement layer and the upper waveguide layer, and a portion of the oxide layer is located in the upper confinement layer and a portion of the oxide layer is located in the upper waveguide layer.

[0059] In another embodiment, the first etched trench is located in the upper confinement layer and does not extend into the upper waveguide layer, and the oxide layer is located in the upper confinement layer.

[0060] In another embodiment, the first etched trench is located in the upper confinement layer and the upper waveguide layer, and the oxide layer is located only in the upper confinement layer.

[0061] In another embodiment, the first etched trench is located in the upper confinement layer and the upper waveguide layer, and the oxide layer is located only in the upper waveguide layer.

[0062] In one embodiment, the thickness of the oxide layer 210 is 0.01 micrometers to 0.05 micrometers, for example, 0.01 micrometers, 0.02 micrometers, 0.03 micrometers, 0.04 micrometers, or 0.05 micrometers. The advantage of this configuration is that a thicker oxide layer results in a smaller total equivalent refractive index in the region where the oxide layer 210 is located, thus reducing the difference between the total equivalent refractive index of the region where the oxide layer 210 is located and the refractive index of the first lens region. This helps reduce the loss of higher-order modes.

[0063] In one embodiment, the projection of the sidewalls of the oxide layer 210 arranged in the light-emitting direction onto the surface of the semiconductor substrate layer is arc-shaped.

[0064] In one embodiment, the maximum dimension L of the ridge region between adjacent oxide layers along the light emission direction is 0.1 mm to 0.5 mm. The advantages of this setting are: L is not too large, allowing for as many first lens regions as possible in the light emission direction, thus reducing light loss in higher-order modes; L is not too small, allowing for greater concavity in the first lens region, which helps improve the magnification factor of the first lens region.

[0065] In one embodiment, the difference between the width of the ridge region and the dimension of the first etching trench along the slow axis is greater than or equal to 10 micrometers, for example, 10 micrometers, 11 micrometers, 12 micrometers, or 13 micrometers. The advantage of this configuration is that the sidewalls of the first etching trench on both sides of the ridge region's width direction are not too thin, thus preventing a reduction in the structural stability of the first etching trench during subsequent filling layer formation and cleaning processes.

[0066] In one embodiment, the dimension of the first etching trench along the slow axis is greater than or equal to 5 micrometers, for example, 6 micrometers, 7 micrometers, or 8 micrometers. A dimension of 5 micrometers or more along the slow axis makes depth control of the first etching trench easier and results in better depth uniformity.

[0067] In this embodiment, the length of the oxide layer 210 along the slow axis direction is greater than the width of the ridge region A. In other embodiments, the length of the oxide layer along the slow axis direction is less than or equal to the width of the ridge region A.

[0068] In one example, for the oxide layer 210 surrounding the first etched trench, the size of the oxide layer 210 on one side of the first etched trench in the light-emitting direction is 5 micrometers to 20 micrometers, for example, 5 micrometers, 8 micrometers, 10 micrometers, 12 micrometers, 15 micrometers, 18 micrometers, or 20 micrometers. If the size of the oxide layer 210 on one side of the first etched trench in the light-emitting direction is too large, the stress on the ridge region will be greater, and the resistance of the device will be greater; if the size of the oxide layer 210 on one side of the first etched trench in the light-emitting direction is too small, the reduction in the equivalent refractive index of the region where the oxide layer 210 is located will be smaller.

[0069] In one embodiment, the radius of curvature of the sidewalls of the oxide layer 210 arranged in the light-emitting direction is 0.1 mm to 10 mm. If the radius of curvature of the sidewalls of the oxide layer 210 arranged in the light-emitting direction is too large, it will have little effect on improving the magnification factor of the first lens region; if the radius of curvature of the sidewalls of the oxide layer 210 arranged in the light-emitting direction is too small, the manufacturing process will be more difficult.

[0070] In one embodiment, the difference between the refractive index of the ridge region A between adjacent oxide layers 210 and the refractive index of the oxide layer 210 is 0.003 to 0.01.

[0071] The material of the oxide layer 210 includes aluminum oxide.

[0072] In one embodiment, the width of the ridge region A is 90µm to 300µm, for example, 90µm, 100µm, 110µm, 120µm, 150µm, 200µm, 250µm, or 300µm. Because the ridge region A has a relatively large width, the power of the light emitted from it is increased. The width of the ridge region A refers to its dimension in the slow axis direction.

[0073] Another embodiment of the present invention also provides a method for fabricating a side-emitting semiconductor laser, which is described below in conjunction with... Figures 4 to 9 Provide a detailed instruction manual.

[0074] refer to Figure 4 and Figure 5 , Figure 5 For along Figure 4 A cross-sectional view along the dicing line M-N shows a semiconductor substrate 100; an active layer 130 is formed on the semiconductor substrate 100; a first semiconductor cladding is formed on the side of the active layer 130 opposite to the semiconductor substrate 100, the first semiconductor cladding including a ridge region A.

[0075] The method of forming the first semiconductor cladding includes: forming an upper waveguide layer 140 on the active layer 130; and forming an upper confinement layer 150 on the upper waveguide layer 140.

[0076] The method for fabricating the edge-emitting semiconductor laser further includes: forming a lower confinement layer 110 on the semiconductor substrate layer 100 before forming the active layer 130; forming a lower waveguide layer 120 on the lower confinement layer 110; and forming the active layer 130 on the lower waveguide layer 120.

[0077] In one embodiment, the width of the ridge region A is 90um to 300um, for example, 90um, 100um, 110um, 120um, 150um, 200um, 250um or 300um.

[0078] Continue to refer to Figure 4 and Figure 5 A second etching trench 160 is formed in the first semiconductor cladding, and the second etching trench 160 is used to define the position of the ridge region A.

[0079] The second etched groove may be located only in the upper confinement layer 150, or it may be located in both the upper confinement layer 150 and the upper waveguide layer 140. Figure 4 The second etched groove is located in the upper confinement layer 150 and the upper waveguide layer 140 as an example.

[0080] refer to Figure 6 , Figure 6 In order to be in Figure 5 The schematic diagram shows that a plurality of first etching grooves 201 are formed in the ridge region A at intervals along the light emission direction.

[0081] In this embodiment, the step of forming a plurality of first etching grooves spaced apart along the light emission direction in the ridge region A includes: forming a plurality of first etching grooves 201 spaced apart along the light emission direction in the upper confinement layer 150 and the upper waveguide layer 140.

[0082] In other embodiments, the step of forming a plurality of first etching grooves spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etching grooves spaced apart along the light emission direction in the upper confining layer.

[0083] The projection pattern of the sidewalls of the first etching trench 201 arranged in the light emission direction on the surface of the semiconductor substrate 100 is elliptical or olive-shaped.

[0084] In one embodiment, the maximum width of the first etching groove 201 in the light-emitting direction is 3 micrometers to 30 micrometers.

[0085] refer to Figure 7A plurality of oxide layer groups are formed in the ridge region A, with each oxide layer group spaced apart. Each oxide layer group corresponds one-to-one with the first etching groove 201. The step of forming any one of the oxide layer groups includes forming at least one oxide layer 210. The oxide layer 210 is located around the first etching groove. The sidewalls of the oxide layer 210 arranged in the light emission direction protrude outward. The refractive index of the oxide layer 210 is less than the refractive index of the ridge region A between adjacent oxide layers 210 in the light emission direction.

[0086] The process for forming the oxide layer 210 is an oxidation process.

[0087] In this embodiment, an oxide layer 210 is formed by an oxidation process. The unstable resonant cavity of the cascaded lens can be realized through a single epitaxy (avoiding the epitaxial regrowth process), thereby improving the yield and reliability of the side-emitting semiconductor laser.

[0088] In this embodiment, each oxide layer group includes a plurality of oxide layers 210 spaced apart in a direction perpendicular to the surface of the semiconductor substrate layer 100. That is, any oxide layer group includes a plurality of oxide layers 210 spaced apart in the longitudinal direction. In other embodiments, any oxide layer group includes a single oxide layer spaced apart in the longitudinal direction.

[0089] In this embodiment, the step of forming at least one oxide layer 210 includes: forming a partial oxide layer 210 in the upper confinement layer and forming a partial oxide layer 210 in the upper waveguide layer.

[0090] It should be noted that in this embodiment, a portion of the thickness of the upper confinement layer is a high-alumina film, a portion of the thickness of the upper waveguide layer is a high-alumina film, and the high-alumina film exposed on the sidewall of the first etching trench is oxidized to form an oxide layer 210. The material of the high-alumina film is AlxGa1-xAs, where x is 0.94 to 1, and the doping concentration of p-type doped ions in the high-alumina film is 1E16 atom / cm³. 3 ~2E20atom / cm 3 Before oxidation, the thickness of the high-alumina film in the upper confinement layer is 10 to 50 nanometers, and the thickness of the high-alumina film in the upper waveguide layer is 10 to 50 nanometers.

[0091] In other embodiments, the step of forming a plurality of first etching trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etching trenches spaced apart along the light emission direction in the upper confining layer; the step of forming at least one oxide layer includes: forming an oxide layer in the upper confining layer. Accordingly, a portion of the thickness of the upper confining layer is a high-alumina film, and the high-alumina film exposed on the sidewalls of the first etching trenches is oxidized to form an oxide layer. Other descriptions of the high-alumina film are as described above and will not be repeated in detail.

[0092] In other embodiments, the step of forming a plurality of first etching trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etching trenches spaced apart along the light emission direction in the upper confinement layer and the upper waveguide layer; the step of forming at least one oxide layer includes: forming an oxide layer in the upper confinement layer. Accordingly, a portion of the thickness of the upper confinement layer is a high-alumina film, and the high-alumina film exposed on the sidewalls of the first etching trenches is oxidized to form an oxide layer. Other descriptions of the high-alumina film are as described above and will not be repeated in detail.

[0093] In other embodiments, the step of forming a plurality of first etching trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etching trenches spaced apart along the light emission direction in the upper confinement layer and the upper waveguide layer; the step of forming at least one oxide layer includes: forming an oxide layer in the upper waveguide layer. Accordingly, a portion of the thickness of the upper waveguide layer is a high-alumina film, and the high-alumina film exposed on the sidewalls of the first etching trenches is oxidized to form an oxide layer. Other descriptions of the high-alumina film are as described above and will not be repeated in detail.

[0094] In one embodiment, the oxidation process is a wet oxidation. Under the catalytic action of hydrogen atoms in water vapor, oxygen atoms (O) in the water react with aluminum atoms in AlxGa1-xAs at high temperature to generate solid aluminum oxide (Al2O3). The by-reactants are liquid arsenic oxide (As2O3) and hydrogen gas (H2) (wherein, arsenic oxide (As2O3) further reacts with hydrogen (H) to generate As and H2O, so H atoms can be considered as catalysts). The chemical reaction formula is as follows:

[0095] 2AlAs+6H2O=Al2O3+As2O3+6H2;

[0096] As2O3+3H2=2As+3H2O or As2O3+6H=2As+3H2O.

[0097] AlAs originates from AlxGa1-xAs. The size of the Al component x is related to the oxidation rate. The higher the Al component, the faster the reaction rate.

[0098] In one embodiment, the thickness of each oxide layer 210 is 10 nanometers to 50 nanometers.

[0099] In one embodiment, the projection of the sidewalls of the oxide layer 210 arranged in the light-emitting direction onto the surface of the semiconductor substrate layer is arc-shaped.

[0100] In one embodiment, the maximum size of the ridge region between adjacent oxide layers in the light-emitting direction is 0.1 mm to 0.5 mm along the light-emitting direction.

[0101] In one embodiment, the difference between the width of the ridge region and the dimension of the first etched groove along the slow axis is greater than or equal to 10 micrometers.

[0102] In one embodiment, the dimension of the first etched groove along the slow axis direction is greater than or equal to 5 micrometers.

[0103] In one embodiment, the radius of curvature of the sidewalls of the oxide layer 210 arranged in the light-emitting direction is 0.1 mm to 10 mm.

[0104] In one embodiment, the difference between the refractive index of the ridge region A between adjacent oxide layers 210 and the refractive index of the oxide layer 210 is 0.003 to 0.01.

[0105] The material of the oxide layer 210 includes aluminum oxide.

[0106] The edge-emitting semiconductor laser further includes a filling layer 200 located in the first etching trench, wherein the filling layer material includes Si, Si3N4, SiO2, Al2O3, ZnSe or photosensitive benzocyclobutene.

[0107] In one embodiment, the width of the ridge region A is 90um to 300um, for example, 90um, 100um, 110um, 120um, 150um, 200um, 250um or 300um.

[0108] In this embodiment, the ridge region between adjacent oxide layers in the light-emitting direction serves as the first lens region. Multiple first lens regions are cascaded along the extension direction of the ridge region, and second lens regions are formed between adjacent front cavity surfaces and oxide layers, as well as between adjacent rear cavity surfaces and oxide layers. The presence of multiple first and second lens regions makes the resonant cavities of the front and rear cavity surfaces selective for light modes. These multiple first and second lens regions amplify and diverge the light in the resonant cavity. The angle between higher-order mode light and the optical axis in the resonant cavity is larger than the angle between the fundamental mode light and the optical axis. Under the action of multiple first and second lens regions, the angle between the higher-order mode light and the optical axis is further amplified, making the higher-order mode light prone to scattering and escaping, thus increasing the loss of the higher-order mode light. When the gain of the active layer is sufficiently large, the fundamental mode along the optical axis can be lased in the resonant cavity, while other higher-order modes cannot be lased due to excessive loss, thereby achieving the effect of amplifying the fundamental mode while suppressing higher-order modes.

[0109] Using processes in primary and secondary epitaxy will always increase the defects and contamination of the epitaxial material. Therefore, the process of epitaxial regeneration requires a high technical threshold and the process stability fluctuates greatly, which will affect the yield and reliability.

[0110] In this application, the lower waveguide layer, lower confinement layer, active layer, upper waveguide layer, and upper confinement layer are formed sequentially in a single epitaxial process, eliminating the need for two separate epitaxial processes. This results in smaller process stability fluctuations and higher yield and reliability.

[0111] The ridge-shaped region between adjacent oxide layers in the light-emitting direction is the first lens region. The equivalent refractive index no of the region formed by the oxide layer and the filling layer is less than the equivalent refractive index na of the first lens region. The value of na depends on the entire epitaxial material, while the value of no depends on the epitaxial material and the oxide layer.

[0112] A second lens region is formed between adjacent front cavity surfaces and oxide layers, as well as between adjacent rear cavity surfaces and oxide layers.

[0113] refer to Figures 10-12 , Figure 11 for Figure 10 The optical path diagram corresponding to the dashed box Q1 in the middle. Figure 12 for Figure 10 The optical path diagram corresponding to the dashed box Q2 in the middle. Figure 11 To explain the working principle of the first lens region, Figure 12 The working principle of the second lens region will be explained, based on the imaging principle. Figure 11 and Figure 12 The relationship between the positions V of the front and rear virtual light sources (VP+ and VP-), the maximum length L of the first or second light-transmitting area in the light-emitting direction, and the radius of curvature R of the sidewalls of the oxide layer arranged in the light-emitting direction is as follows:

[0114]

[0115]

[0116] Wherein, R1 is the equivalent radius of curvature of the first lens region, and R2 is the equivalent radius of curvature of the concave surface of the second lens region.

[0117]

[0118]

[0119] Where M1 is the magnification factor of the first lens region and M2 is the magnification factor of the second lens region.

[0120] The magnification factor can be understood as the degree of expansion of the single-mode spot size. The larger the value, the more likely it is that single-mode output can be maintained in a wider ridge region, thereby increasing the single-mode power.

[0121] The total magnification of a series of first lens regions and second lens regions is the product of the magnification of the first lens regions and the magnification of the two second lens regions.

[0122] In one example, the maximum length L of the first lens region along the light-emitting direction is 0.1 mm to 0.5 mm, the dimension of the first etching groove along the slow axis is greater than or equal to 5 micrometers, the difference between the width of the ridge region and the dimension of the first etching groove along the slow axis is greater than or equal to 10 micrometers, the radius of curvature of the sidewalls of the oxide layer arranged in the light-emitting direction is 0.1 mm to 10 mm, the difference between the refractive index of the ridge region between adjacent oxide layers and the refractive index of the oxide layer is 0.003 to 0.01, the calculated spot magnification factor of a single first lens region is 1.01 to 1.6, and when 10 first lens regions are cascaded, the total magnification can reach 1.1 to 100.

[0123] refer to Figure 8 A filling layer 200 is formed in the first etching groove 201.

[0124] refer to Figure 9 A passivation layer 170 is formed on a portion of the first semiconductor cladding, exposing a ridge region A; a front electrode layer 180 is formed on the ridge region A; and a back electrode layer 190 is formed on the side surface of the semiconductor substrate layer 100 opposite to the active layer 130.

[0125] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A side-emitting semiconductor laser having a front cavity surface and a rear cavity surface disposed opposite to each other, wherein light is emitted from the front cavity surface, characterized in that, include: Semiconductor substrate layer; The active layer located on the semiconductor substrate; A first semiconductor cladding layer located on the active layer, the first semiconductor cladding layer including a ridge region; A plurality of first etching grooves are located in the ridge region, and the plurality of first etching grooves are arranged at intervals along the light emission direction; A plurality of oxide layer groups are located in the ridge region, with each oxide layer group spaced apart. Each oxide layer group corresponds one-to-one with a first etching groove. Each oxide layer group includes at least one oxide layer, which is located around the first etching groove. The sidewalls of the oxide layers arranged in the light-emitting direction protrude outward, so that the ridge region between adjacent oxide layers in the light-emitting direction forms a first lens region, and a second lens region is formed between adjacent front cavity surfaces and oxide layers, as well as between adjacent rear cavity surfaces and oxide layers. The radius of curvature of the sidewalls of the oxide layers arranged in the light-emitting direction is 0.1 mm to 10 mm, and the refractive index of the oxide layers is less than the refractive index of the ridge region between adjacent oxide layers in the light-emitting direction.

2. The edge-emitting semiconductor laser according to claim 1, characterized in that, Each of the oxide layer groups includes a plurality of oxide layers spaced apart in a direction perpendicular to the surface of the semiconductor substrate layer.

3. The edge-emitting semiconductor laser according to claim 1, characterized in that, The projection pattern of the sidewalls of the first etching trench arranged in the light emission direction on the surface of the semiconductor substrate includes an ellipse or an olive shape.

4. The edge-emitting semiconductor laser according to claim 1, characterized in that, The first semiconductor cladding includes an upper confinement layer and an upper waveguide layer, wherein the upper waveguide layer is located between the upper confinement layer and the active layer; The first etched trench is located in the upper confinement layer and does not extend into the upper waveguide layer; the oxide layer is located in the upper confinement layer. Alternatively, the first etching trench is located in the upper confinement layer and the upper waveguide layer, and the oxide layer is located only in the upper confinement layer; Alternatively, the first etched trench is located in the upper confinement layer and the upper waveguide layer, and the oxide layer is located only in the upper waveguide layer; Alternatively, the first etching trench is located in the upper confinement layer and the upper waveguide layer, with a portion of the oxide layer located in the upper confinement layer and a portion of the oxide layer located in the upper waveguide layer.

5. The edge-emitting semiconductor laser according to claim 1, characterized in that, The maximum width of the first etching groove in the light emission direction is 3 micrometers to 30 micrometers.

6. The edge-emitting semiconductor laser according to claim 1, characterized in that, Also includes: The filling layer located in the first etching tank includes Si, Si3N4, SiO2, Al2O3, ZnSe or photosensitive benzocyclobutene.

7. The edge-emitting semiconductor laser according to claim 1, characterized in that, The thickness of each oxide layer is 0.01 micrometers to 0.05 micrometers.

8. The edge-emitting semiconductor laser according to claim 1, characterized in that, The projection of the sidewalls of the oxide layer arranged in the light-emitting direction onto the surface of the semiconductor substrate layer is arc-shaped.

9. The edge-emitting semiconductor laser according to claim 1, characterized in that, The maximum size of the ridge region between adjacent oxide layers in the light-emitting direction is 0.1 mm to 0.5 mm.

10. The edge-emitting semiconductor laser according to claim 1, characterized in that, The difference between the width of the ridge region and the dimension of the first etching groove along the slow axis is greater than or equal to 10 micrometers.

11. The edge-emitting semiconductor laser according to claim 10, characterized in that, The dimension of the first etched groove along the slow axis direction is greater than or equal to 5 micrometers.

12. The edge-emitting semiconductor laser according to claim 1, characterized in that, The difference between the refractive index of the ridge region between adjacent oxide layers and the refractive index of the oxide layer is 0.003 to 0.

01.

13. The edge-emitting semiconductor laser according to claim 1, characterized in that, The material of the oxide layer includes aluminum oxide.

14. The edge-emitting semiconductor laser according to claim 1, characterized in that, The width of the ridge region is 90um to 300um.

15. A method for fabricating a side-emitting semiconductor laser, the side-emitting semiconductor laser having a front cavity surface and a rear cavity surface disposed opposite to each other, light being emitted from the front cavity surface, characterized in that, include: Provide semiconductor substrate layer; An active layer is formed on the semiconductor substrate; A first semiconductor cladding layer is formed on the side of the active layer opposite to the semiconductor substrate layer, and the first semiconductor cladding layer includes a ridge region; A plurality of first etching grooves are formed in the ridge region at intervals along the light emission direction; A plurality of oxide layer groups are formed in the ridge region, with each oxide layer group spaced apart. Each oxide layer group corresponds one-to-one with a first etching groove. The step of forming any one of the oxide layer groups includes forming at least one oxide layer located around the first etching groove. The sidewalls of the oxide layer arranged in the light-emitting direction protrude outward, so that the ridge region between adjacent oxide layers in the light-emitting direction forms a first lens region, and a second lens region is formed between adjacent front cavity surfaces and oxide layers, as well as between adjacent rear cavity surfaces and oxide layers. The radius of curvature of the sidewalls of the oxide layer arranged in the light-emitting direction is 0.1 mm to 10 mm, and the refractive index of the oxide layer is less than the refractive index of the ridge region between adjacent oxide layers in the light-emitting direction.

16. The method for fabricating a side-emitting semiconductor laser according to claim 15, characterized in that, The step of forming the oxide layer group includes: forming a plurality of oxide layers spaced apart in a direction perpendicular to the surface of the semiconductor substrate layer.

17. The method for fabricating a side-emitting semiconductor laser according to claim 15, characterized in that, The first semiconductor cladding includes an upper confinement layer and an upper waveguide layer, wherein the upper waveguide layer is located between the upper confinement layer and the active layer; The step of forming a plurality of first etching trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etching trenches spaced apart along the light emission direction in the upper confining layer; the step of forming at least one oxide layer includes: forming an oxide layer in the upper confining layer; Alternatively, the step of forming a plurality of first etched trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etched trenches spaced apart along the light emission direction in the upper confinement layer and the upper waveguide layer; the step of forming at least one oxide layer includes: forming an oxide layer in the upper confinement layer; Alternatively, the step of forming a plurality of first etched trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etched trenches spaced apart along the light emission direction in the upper confinement layer and the upper waveguide layer; the step of forming at least one oxide layer includes: forming an oxide layer in the upper waveguide layer; Alternatively, the step of forming a plurality of first etching trenches spaced apart along the light emission direction in the ridge region includes: forming a plurality of first etching trenches spaced apart along the light emission direction in the upper confinement layer and the upper waveguide layer; the step of forming at least one oxide layer includes: forming a partial oxide layer in the upper confinement layer and forming a partial oxide layer in the upper waveguide layer.

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