A replica circuit and an oscillator including the replica circuit

Abstract

The present technology includes a replica circuit and an oscillator including the replica circuit. A replica circuit includes a first terminal supplied with a replica voltage having a positive voltage, a second terminal supplied with a ground voltage, a replica main circuit connected between the first terminal and the second terminal and configured to form a first current path in response to the replica voltage, and a replica sub-circuit connected in parallel with the replica main circuit between the first terminal and the second terminal and configured to form a second current path in response to the replica voltage. A current flowing through the second current path having a replica sub-current amount is less than a current flowing through the first current path having a replica main current amount.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0044277, filed on April 5, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a replication circuit and an oscillator including the replication circuit, and more specifically to a replication circuit capable of improving the reliability of the replication circuit and an oscillator including the replication circuit. Background Technology

[0004] Clock generators, including phase-locked loop (PLL) circuits, can generate and output a clock with a fixed phase. For example, the clock can be used at the transmitter to send data or at the receiver to receive or recover data. PLL circuits can be classified as ring PLL circuits, inductor-capacitor (LC) PLL circuits, etc.

[0005] The PLL circuit may include a noise-reducing oscillator, and the oscillator may include a voltage-controlled oscillator (VCO). Summary of the Invention

[0006] Embodiments of this disclosure provide a replication circuit capable of improving reliability and an oscillator including the replication circuit.

[0007] According to embodiments of this disclosure, a replication circuit includes: a first terminal supplied with a replication voltage having a positive voltage; a second terminal supplied with a ground voltage; a replication main circuit connected between the first and second terminals and configured to form a first current path in response to the replication voltage to replicate the current of a main circuit in a voltage-controlled oscillator that generates a sub-clock and an inverting sub-clock; and a replication sub-circuit connected in parallel with the replication main circuit between the first and second terminals and configured to form a second current path in response to the replication voltage to replicate the current of a sub-circuit in the voltage-controlled oscillator used to reduce noise in the sub-clock and the inverting sub-clock. The replication main circuit is configured such that the current flowing through the first current path has a replication main current amount, and the replication sub-circuit is configured such that the current flowing through the second current path has a replication sub-current amount less than the replication main current amount.

[0008] According to embodiments of this disclosure, an oscillator includes: a voltage-controlled oscillator (VCO) operating according to a control voltage, the VCO including a main circuit and a sub-circuit, the main circuit being configured to generate a clock and an inverted clock by respectively inverting an input signal and an inverted input signal, and the sub-circuit being configured to reduce noise in the clock and the inverted clock; a replication circuit operating according to a replication voltage and including a replication main circuit and a replication sub-circuit, the replication main circuit being configured to replicate the voltage or current of the main circuit, and the replication sub-circuit being configured to replicate the voltage or current of the sub-circuit; and an amplifier configured to output an amplified voltage to the VCO and the replication circuit by amplifying the difference between a reference voltage and the replication voltage, such that the replication voltage and the control voltage are equal to each other. The VCO is configured to adjust the control voltage in response to the amplified voltage, and the replication circuit is configured to maintain the level of the replication voltage in response to the amplified voltage, and the level of the replication voltage is adjusted according to the magnitude of the switches configuring the replication main circuit and the replication sub-circuit.

[0009] According to embodiments of this disclosure, an oscillation circuit includes: a first transistor and a voltage-controlled oscillator (VCO) connected in series between a power node and a ground node; a second transistor and a replication circuit connected in series between the power node and the ground node; and an amplifier configured to compare a reference voltage and a replication voltage to generate a control voltage for controlling the on-state of corresponding first and second transistors. The VCO includes first to fourth inverters connected in parallel, the first and second inverters configured to invert corresponding inputs, and a third and fourth inverter are cross-connected and configured to reduce noise at the outputs of the corresponding first and second inverters. The replication voltage is the voltage at the node between the second transistor and the replication circuit. The replication circuit replicates the main current flowing in the first and second inverters and the sub-current flowing in the third and fourth inverters based on the replication voltage. The amount of the main current is greater than the amount of the sub-current.

[0010] This technology can improve the reliability of the replication circuit, thereby improving the reliability of the oscillator that includes the replication circuit. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating an oscillator according to an embodiment of the present disclosure.

[0012] Figure 2 This is a diagram illustrating a voltage-controlled oscillator according to an embodiment of the present disclosure.

[0013] Figure 3 This is a diagram illustrating a first transmission circuit according to an embodiment of the present disclosure.

[0014] Figure 4This is a diagram showing the amount of current flowing in the main circuit of a voltage-controlled oscillator according to an embodiment of the present disclosure.

[0015] Figure 5 This is a diagram showing the amount of current flowing in a sub-circuit of a voltage-controlled oscillator according to an embodiment of the present disclosure.

[0016] Figure 6 This is a diagram illustrating a replication circuit according to an embodiment of the present disclosure.

[0017] Figure 7 This is a diagram illustrating the size of a transistor included in a replication circuit according to an embodiment of the present disclosure.

[0018] Figure 8 This is a diagram showing the amount of current flowing in the replication master circuit of the replication circuit according to an embodiment of the present disclosure.

[0019] Figure 9 This is a diagram illustrating the amount of current flowing in the replicating sub-circuit of the replication circuit according to an embodiment of the present disclosure.

[0020] Figure 10 This is a diagram showing the total current of the replication circuit and the total current of the oscillator according to an embodiment of the present disclosure.

[0021] Figure 11 This is a diagram illustrating the current quantities of an oscillator based on the replication voltage and control voltage according to an embodiment of the present disclosure. Detailed Implementation

[0022] The specific structural or functional descriptions illustrating embodiments of the concepts disclosed in this specification are merely for the purpose of describing embodiments of the concepts disclosed herein. Embodiments of the concepts disclosed herein may be implemented in various forms and should not be construed as limited to the embodiments described herein.

[0023] Figure 1 This is a diagram illustrating an oscillator 1000 according to an embodiment of the present disclosure.

[0024] Reference Figure 1 The oscillator 1000 may include an amplifier 110, a replication group 120, and a voltage control group 130.

[0025] Amplifier 110 can be configured to amplify the difference between voltages input to two input terminals. A reference voltage Vref can be applied to the negative input terminal of amplifier 110, and a copy voltage Vrep with a positive voltage can be applied to the positive input terminal of amplifier 110. For example, when the copy voltage Vrep is higher than the reference voltage Vref with a positive voltage, amplifier 110 can output a first amplified voltage obtained by amplifying the difference between the copy voltage Vrep and the reference voltage Vref to the first node N1. The first amplified voltage can be a positive voltage. Conversely, when the copy voltage Vrep is lower than the reference voltage Vref, amplifier 110 can output a second amplified voltage obtained by amplifying the difference between the copy voltage Vrep and the reference voltage Vref to the first node N1. The second amplified voltage can be a negative voltage.

[0026] The replication group 120 can be configured to have a connection configuration electrically similar to that of the voltage-controlled group 130. The replication group 120 can be configured to receive a power supply voltage VCC and generate a replication voltage Vrep in response to a first amplified voltage or a second amplified voltage on the first node N1. For example, the replication group 120 may include a first switch S1 and a replication circuit REP. The first switch S1 may be connected between the terminal supplied with the power supply voltage VCC and the second node N2, and may include a PMOS transistor whose on-state is adjusted according to the amplified voltage of the first node N1. For example, as the amplified voltage of the first node N1 decreases, the on-state of the first switch S1 may increase, and as the amplified voltage of the first node N1 increases, the on-state of the first switch S1 may decrease or the first switch S1 may turn off. The replication circuit REP may be connected between the second node N2 and the terminal to which a ground voltage GND is applied, and may be configured to keep the internal current constant according to the replication voltage Vrep supplied through the second node N2.

[0027] The voltage-controlled assembly 130 can be configured to receive a power supply voltage VCC and generate a control voltage Vvco with a positive voltage in response to the amplified voltage of the first node N1. For example, the voltage-controlled assembly 130 may include a second switch S2 and a voltage-controlled oscillator (VCO). The second switch S2 may be connected between the terminal supplied with the power supply voltage VCC and the third node N3, and may include a PMOS transistor whose on-state is adjusted according to the amplified voltage of the first node N1. For example, as the amplified voltage of the first node N1 decreases, the on-state of the second switch S2 may increase, and as the amplified voltage of the first node N1 increases, the on-state of the second switch S2 may decrease or the second switch S2 may be turned off. The voltage-controlled oscillator VCO may be connected between the third node N3 and the terminal to which a ground voltage GND is applied, and may be configured to output a clock CLK in response to an input signal IN. For example, the voltage-controlled oscillator VCO may be configured to receive the control voltage Vvco as a voltage source and output a noise-reduced clock CLK in response to the input signal IN.

[0028] The oscillator 1000 may further include a capacitor CAP connected between the third node N3 and the terminal to which the ground voltage GND is applied to reduce noise in the control voltage Vvco.

[0029] like Figure 1 As shown, replication group 120 and voltage-controlled oscillator group 130 can be connected in parallel between the terminal supplied with power supply voltage VCC and the terminal to which ground voltage GND is applied, and can be configured to output replication voltage Vrep or control voltage Vvco in common response to the amplified voltage of the first node N1. Replication group 120 according to this embodiment may include replication circuit REP, which is constructed from transistors of a different size than the transistors that construct the voltage-controlled oscillator VCO, in order to maintain a constant current internally.

[0030] Figure 2 This is a diagram illustrating a voltage-controlled oscillator (VCO) according to an embodiment of the present disclosure.

[0031] Reference Figure 2 The voltage-controlled oscillator (VCO) may include a first transmission circuit 1TRAN to a k-th transmission circuit kTRAN, which are configured to output a clock CLK and an inverted clock CLKb in response to an input signal IN and an inverted input signal INb. The inverted input signal INb may be a signal whose phase or level is opposite to that of the input signal IN. For example, when the input signal IN is a high-level signal, the inverted input signal INb may be a low-level signal.

[0032] The first transmission circuit 1TRAN to the kth transmission circuit kTRAN can operate by receiving the control voltage Vvco as a voltage source, and can be configured to reduce the noise of the input signal IN and the inverted input signal INb and output clock CLK and inverted clock CLKb. The inverted clock CLKb can be a clock whose phase is opposite to that of clock CLK.

[0033] The first transmission circuit 1TRAN to the kth transmission circuit kTRAN can be connected in series. Therefore, the input signal IN and the inverted input signal INb can be input to the first transmission circuit 1TRAN, and the kth transmission circuit kTRAN, as the final circuit, can output a clock CLK and an inverted clock CLKb. As an example, the clock and inverted clock output from each of the first transmission circuit 1TRAN to the (k-1)th transmission circuit (k-1)TRAN are sub-clocks sCLK and sCLKb, respectively. The sub-clocks sCLK and sCLKb output from the previous transmission circuit can be used as the input and inverted input signals for the next transmission circuit. For example, the sub-clock sCLK output from the first transmission circuit 1TRAN can be input as an input signal to the second transmission circuit 2TRAN, and the inverted sub-clock sCLKb output from the first transmission circuit 1TRAN can be input as an inverted input signal to the second transmission circuit 2TRAN.

[0034] The first transmission circuit 1TRAN through the k-th transmission circuit kTRAN can be configured with the same structure. When the first transmission circuit 1TRAN is described as an example, it may include two main inverters I1 and I2 and two sub-inverters I3 and I4. The main inverters I1 and I2 can determine the phase of the sub-clock sCLK and the phase of the inverted sub-clock sCLKb in response to the input signal IN and the inverted input signal INb, and the sub-inverters I3 and I4 can reduce the noise in the sub-clock sCLK and the inverted sub-clock sCLKb output from the main inverters I1 and I2. For example, the first inverter I1 can be configured to output the sub-clock sCLK by inverting the input signal IN, and the second inverter I2 can be configured to output the inverted sub-clock sCLKb by inverting the inverted input signal INb. The output nodes of the first inverter I1 and the second inverter I2 can be configured to be separate from each other, and the third inverter I3 and the fourth inverter I4 can be connected in parallel between the terminal to which the control voltage Vvco is applied and the terminal to which the ground voltage GND is applied. The third inverter I3 and the fourth inverter I4 can receive signals from the output nodes of the first inverter I1 and the second inverter I2, respectively, and output signals to the output nodes of the second inverter I2 and the first inverter I1, respectively. For example, the third inverter I3 can be configured to invert the sub-clock sCLK output from the first inverter I1 and transmit the inverted sub-clock sCLKb to the output node of the second inverter I2, and the fourth inverter I4 can be configured to invert the inverted sub-clock sCLKb output from the second inverter I2 and transmit the sub-clock sCLK to the output node of the first inverter I1. The configuration of the first transmission circuit 1TRAN is described in more detail below.

[0035] Figure 3 This is a schematic diagram illustrating a first transmission circuit 1TRAN according to an embodiment of the present disclosure.

[0036] Reference Figure 3 The first transmission circuit 1TRAN may include: a main circuit MAC configured to determine the phase of the sub-clock sCLK and the inverted sub-clock sCLKb; and a sub-circuit SBC configured to reduce the noise of the sub-clock sCLK and the inverted sub-clock sCLKb.

[0037] The main circuit MAC may include: a first inverter I1, configured to output a sub-clock sCLK by inverting the input signal IN; and a second inverter I2, configured to output an inverted sub-clock sCLKb by inverting the inverted input signal INb. The first inverter I1 and the second inverter I2 may be implemented with the same structure. For example, the first inverter I1 and the second inverter I2 may include third switches S3 to sixth switches S6. The size of the third switches S3 to sixth switches S6 may be determined by the width and length of the transistors configuring each switch. For example, the third switch S3 and the fifth switch S5 may be implemented with the same size as each other, and the fourth switch S4 and the sixth switch S6 may also be implemented with the same size as each other. Alternatively, the third switch S3 and the fifth switch S5 may be implemented with a size larger than the fourth switch S4 and the sixth switch S6, and the third switches S3 to the sixth switch S6 may be implemented with the same size as each other.

[0038] The first inverter I1 may include a third switch S3 and a fourth switch S4, which are connected in series between the terminal to which a control voltage Vvco is applied and the terminal to which a ground voltage GND is applied. The third switch S3 may include a PMOS transistor configured to apply a positive voltage to the fourth node N4 in response to the input signal IN. The fourth switch S4 may include an NMOS transistor configured to discharge the fourth node N4 in response to the input signal IN. Because the third switch S3 and the fourth switch S4 are implemented using different types of transistors, they can be turned on at different levels or off at different times in response to the input signal IN. In the following, the amount of current flowing through the fourth node N4 according to the input signal IN is the first main current ImIp.

[0039] The second inverter I2 may include a fifth switch S5 and a sixth switch S6, which are connected in series between the terminal to which the control voltage Vvco is applied and the terminal to which the ground voltage GND is applied. The fifth switch S5 may include a PMOS transistor configured to apply a positive voltage to the fifth node N5 in response to the inverted input signal INb. The sixth switch S6 may include an NMOS transistor configured to discharge the fifth node N5 in response to the inverted input signal INb. Because the fifth switch S5 and the sixth switch S6 are implemented using different types of transistors, they may be turned on at different levels or off at different times in response to the inverted input signal INb. In the following, the amount of current flowing through the fifth node N5 according to the inverted input signal INb is the second main current 2mIp.

[0040] The third inverter I3 and the fourth inverter I4 can be configured by the seventh to tenth switches S7 to S10 to reduce the noise of the sub-clock sCLK and the inverted sub-clock sCLKb, wherein the size of the seventh to tenth switches S7 is smaller than the size of the switches S3 to S6 included in the first inverter I1 and the second inverter I2. As the size of the transistors configuring the switches decreases, the on-level of the switches decreases, and therefore the current can be finely adjusted.

[0041] Among the seventh switches S7 to the tenth switches S10, the seventh switch S7 and the ninth switch S9 can be implemented with the same size, and the eighth switch S8 and the tenth switch S10 can also be implemented with the same size. The seventh switch S7 and the ninth switch S9 can be implemented with a size larger than the eighth switch S8 and the tenth switch S10, or they can be implemented with the same size. Because the size of the seventh switches S7 to the tenth switches S10 can be determined by the width and length of the transistor configuring each switch, the width and length of the seventh switches S7 to the tenth switches S10 can be determined based on their sizes. For example, the seventh switch S7 and the ninth switch S9 can have the same width and the same length. For example, the eighth switch S8 and the tenth switch S10 can have the same width and the same length. For example, implementing the seventh switch S7 with a size larger than the eighth switch S8 means that the width and length of the seventh switch S7 can be larger than the width and length of the eighth switch S8, respectively. For example, when the seventh switch S7 is larger than the eighth switch S8, and the widths of the seventh and eighth switches S7 and S8 are the same, the length of the seventh switch S7 can be longer than the length of the eighth switch S8. Similarly, when the seventh switch S7 is larger than the eighth switch S8, and the lengths of the seventh and eighth switches S7 and S8 are the same, the width of the seventh switch S7 can be wider than the width of the eighth switch S8. The sizes of the seventh and ninth switches S9 can be smaller than the sizes of the third and fifth switches S3 and S5, and the sizes of the eighth and tenth switches S10 can be smaller than the sizes of the fourth and sixth switches S4 and S6.

[0042] Table 1 shows a comparison between the sizes of the third switches S3 to the sixth switches S6 included in the main circuit MAC and the sizes of the seventh switches S7 to the tenth switches S10 included in the sub-circuit SBC.

[0043] Table 1

[0044]

[0045] Referring to Table 1, the third to sixth switches S3 in the main circuit MAC are implemented with a first size 1SZ, and the seventh to tenth switches S10 in the sub-circuit SBC are implemented with a second size 2SZ. Because the second size 2SZ is smaller than the first size 1SZ, the seventh to tenth switches S10 in the sub-circuit SBC can be implemented with a smaller size than the third to sixth switches S3.

[0046] Table 2

[0047]

[0048] Referring to Table 2, the third switch S3 and the fifth switch S5 included in the main circuit MAC are implemented with a first size of 1SZ, the fourth switch S4 and the sixth switch S6 are implemented with a second size of 2SZ, the seventh switch S7 and the ninth switch S9 included in the sub-circuit SBC are implemented with a third size of 3SZ, and the eighth switch S8 and the tenth switch S10 are implemented with a fourth size of 4ZS. The sizes in Table 2 are independent of the sizes in Table 1. The second size 2SZ can be smaller than the first size 1SZ, and the fourth size 4SZ can be smaller than the third size 3SZ. The third size 3SZ can be smaller than the first size 1SZ, and the fourth size 4SZ can be smaller than the second size 2SZ. That is, the switches included in the sub-circuit SBC can be implemented smaller than the switches included in the main circuit MAC. In addition, the sizes of the seventh switch S7 and the ninth switch S9 included in the sub-circuit SBC can be implemented to be equal to or smaller than the sizes of the fourth switch S4 and the sixth switch S6 included in the main circuit MAC.

[0049] The third inverter I3 may include a seventh switch S7 and an eighth switch S8, which are connected in series between the terminal to which the control voltage Vvco is applied and the terminal to which the ground voltage GND is applied. The seventh switch S7 may include a PMOS transistor configured to apply a positive voltage to the fifth node N5 in response to a sub-clock sCLK applied to the fourth node N4. The eighth switch S8 may include an NMOS transistor configured to discharge the fifth node N5 in response to a sub-clock sCLK applied to the fourth node N4. Because the seventh switch S7 and the eighth switch S8 are implemented using different types of transistors, they may be turned on at different levels or off at different times in response to the sub-clock sCLK. In the following, the amount of current flowing through the fifth node N5 according to the sub-clock sCLK is the first sub-current IsIp.

[0050] The fourth inverter I4 may include a ninth switch S9 and a tenth switch S10, which are connected in series between the terminal to which the control voltage Vvco is applied and the terminal to which the ground voltage GND is applied. The ninth switch S9 may include a PMOS transistor configured to apply a positive voltage to the fourth node N4 in response to the inverted sub-clock sCLKb applied to the fifth node N5. The tenth switch S10 may include an NMOS transistor configured to discharge the fourth node N4 in response to the inverted sub-clock sCLKb applied to the fifth node N5. Because the ninth and tenth switches S9 and S10 are implemented using different types of transistors, they may be turned on at different levels or off at different times in response to the inverted sub-clock sCLKb. In the following, the amount of current flowing through the fourth node N4 according to the inverted sub-clock sCLKb is the second sub-current 2sIp.

[0051] Each of the current quantities in the main circuit MAC and the sub-circuit SBC is described below.

[0052] Figure 4 This is a diagram illustrating the current flow in the main circuit of a voltage-controlled oscillator according to an embodiment of the present disclosure, and Figure 5 This is a diagram showing the amount of current flowing in a sub-circuit of a voltage-controlled oscillator according to an embodiment of the present disclosure.

[0053] Reference Figure 3 and Figure 4 Because the main circuit MAC is configured to output sub-clocks sCLK and sCLKb in response to the input signal IN and the inverted input signal INb, the sub-clock sCLK can transition from low level L to high level H when the input signal IN changes from high level H to low level L. Since the main circuit MAC is supplied with a control voltage Vvco and grounded through the ground voltage GND, the voltage with a high level H can be the control voltage Vvco, and the low level L is the level of the ground voltage GND. When the input signal IN is high level H, because the inverted input signal INb has a low level L, when the input signal IN changes from high level H to low level L, the inverted input signal INb can transition from low level L to high level H. When the inverted input signal INb changes from low level L to high level H, the inverted sub-clock sCLKb can transition from high level H to low level L.

[0054] The first main current 1mIp of the first inverter I1 can increase during a predetermined period when the fourth switch S4 is turned on and a current path is formed in the fourth node N4, and the second main current 2mIp of the second inverter I2 can increase during a predetermined period when the sixth switch S6 is turned on and a current path is formed in the fifth node N5. Therefore, when the sub-clock sCLK transitions from high level H to low level L, the first main current 1mIp can temporarily increase, and when the inverted sub-clock sCLKb transitions from high level H to low level L, the second main current 2mIp can temporarily increase.

[0055] Reference Figure 3 and Figure 5 Because the sub-circuit SBC is configured to adjust the levels of the sub-clock sCLK and the inverted sub-clock sCLKb of different fourth nodes N4 and fifth nodes N5 in response to the sub-clock sCLK and the inverted sub-clock sCLKb, the sub-clock sCLK can transition from low level L to high level H when the input signal IN transitions from high level H to low level L. Since the size of the sub-circuit SBC is smaller than the size of the main circuit MAC, the time point at which the current increases in the sub-circuit SBC can be the time it takes for the sub-clock sCLK or the inverted sub-clock sCLKb to decrease from high level H to the decreased high level H_dec, and the time it takes for the sub-clock sCLK or the inverted sub-clock sCLKb to increase from low level L to the increased low level L_inc. For example, because the threshold voltages of the seventh switch S7 to the tenth switch S10 are lower than the threshold voltages of the third switch S3 to the sixth switch S6, when the seventh switch S7 or the ninth switch S9 is turned on, a reduced control voltage Vvco_dec, lower than the control voltage Vvco, can be output through the output node. The reduced control voltage Vvco_dec can be a voltage lower than the threshold voltage of the seventh switch S7 or the ninth switch S9, which is lower than the control voltage Vvco. When the eighth switch S8 or the tenth switch S10 is turned on, an increased ground voltage GND_inc, higher than the ground voltage GND, can be output through the output node. Therefore, when the seventh switch S7 or the eighth switch S8 is turned on, or the ninth switch S9 or the tenth switch S10 is turned on, the first sub-current 1sIp or the second sub-current 2sIp can be temporarily increased.

[0056] Figure 6 This is a diagram illustrating a replication circuit REP according to an embodiment of the present disclosure.

[0057] Reference Figure 6 The replication circuit REP may include a replication master circuit MAC_R and a replication sub-circuit SBC_R. The replication master circuit MAC_R can be configured to replicate components included in the voltage-controlled oscillator. Figure 3The voltage or current of the main circuit MAC, and the replication sub-circuit SBC_R can be configured to replicate the voltage included in the voltage-controlled oscillator. Figure 3 The voltage or current of the sub-circuit SBC. However, because Figure 3 The input signal IN and Figure 3 The inverted input signal INb is not applied to the replication circuit REP according to this embodiment, so it can be used with... Figure 1 The voltage-controlled oscillator (VCO) maintains a constant current, unlike other circuits. The master circuit MAC_R and the sub-circuit SBC_R are described in detail below.

[0058] The replication master circuit MAC_R can be connected between the sixth node N6, which is supplied with replication voltage Vrep, and the seventh node N7, which is supplied with ground voltage GND. The eleventh switch S11 and the twelfth switch S12 can be connected in series between the sixth node N6 and the seventh node N7. For example, the eleventh switch S11 can be connected between the sixth node N6 and the twelfth switch S12, and the twelfth switch S12 can be connected between the eleventh switch S11 and the seventh node N7. The eleventh switch S11 may include a PMOS transistor, with the ground voltage GND applied to its gate. The twelfth switch S12 may include an NMOS transistor, with its gate connected to the sixth node N6. That is, the eleventh switch S11 can always be turned on depending on the ground voltage GND, and the twelfth switch S12 can always be turned on when the replication voltage Vrep remains positive.

[0059] When the eleventh switch S11 and the twelfth switch S12 are turned on, the sixth node N6, the eleventh switch S11, the twelfth switch S12, and the seventh node N7 can be electrically connected, thus forming a current path. In the following text, the amount of current flowing along the current path of the replica main circuit MAC_R is the replica main current mIp_R. The eleventh switch S11 and the twelfth switch S12 can be implemented with the same size, or the eleventh switch S11 can be implemented larger than the twelfth switch S12.

[0060] The replicating sub-circuit SBC_R can be connected between the sixth node N6, which is supplied with the replication voltage Vrep, and the seventh node N7, which is supplied with the ground voltage GND. That is, the replication master circuit MAC_R and the replicating sub-circuit SBC_R can be connected in parallel between the sixth node N6 and the seventh node N7. A series of thirteenth switches S13 and fourteenth switches S14, as well as a series of first resistors 1R and second resistors 2R, can be connected in parallel between the sixth node N6 and the seventh node N7. For example, the thirteenth switch S13 and the fourteenth switch S14 can be connected in series between the sixth node N6 and the seventh node N7, and the first resistors 1R and second resistors 2R can also be connected in series between the sixth node N6 and the seventh node N7. A series of thirteenth switches S13 and fourteenth switches S14, as well as a series of first resistors 1R and second resistors 2R, can be connected in parallel between the sixth node N6 and the seventh node N7. The thirteenth switch S13 can be connected between the sixth node N6 and the fourteenth switch S14, and the fourteenth switch S14 can be connected between the thirteenth switch S13 and the seventh node N7. The first resistor 1R can be connected between the sixth node N6 and the second resistor 2R, and the second resistor 2R can be connected between the first resistor 1R and the seventh node N7. The first resistor 1R and the second resistor 2R can be connected to each other via the eighth node N8. The first resistor 1R can be configured to have a resistance value higher than that of the second resistor 2R. For example, the first resistor 1R can be configured to have a resistance value higher than the fixed resistance value of the second resistor 2R, or it can be configured by a variable resistor with a resistance value higher than that of the second resistor 2R.

[0061] The thirteenth switch S13 may include a PMOS transistor, the gate of which is connected to the eighth node N8. The fourteenth switch S14 may include an NMOS transistor, the gate of which is connected between the thirteenth and fourteenth switches S13. When a positive replication voltage Vrep is applied to the sixth node N6, a positive voltage lower than the replication voltage Vrep can be applied to the eighth node N8 due to the first resistor 1R. Therefore, the thirteenth switch S13 can be turned on by a level lower than that of the eleventh switch S11.

[0062] When the thirteenth switch S13 is turned on at a low level, a positive voltage lower than the replication voltage Vrep is also applied to the node between the thirteenth switch S13 and the fourteenth switch S14. Therefore, the fourteenth switch S14 can be turned on by a level lower than that of switch S12. In the following text, the amount of current flowing along the current path of the replicator circuit SBC_R is the replicator current sIp_R.

[0063] Because the conduction levels of the thirteenth switch S13 and the fourteenth switch S14 are lower than those of the eleventh switch S11 and the twelfth switch S12, the value of the replica sub-current sIp_R can be lower than the value of the replica master current mIp_R. Therefore, the size of the replica sub-circuit SBC_R can be implemented smaller than the size of the replica master circuit MAC_R. For example, the thirteenth switch S13 and the fourteenth switch S14 can have the same size, or the thirteenth switch S13 can be implemented larger than the fourteenth switch S14. The thirteenth switch S13 can be implemented smaller than the eleventh switch S11, and the fourteenth switch S14 can be implemented smaller than the twelfth switch S12. Alternatively, the fourteenth switch S14 can be implemented equal to or smaller than the eleventh switch S11.

[0064] Table 3 shows a comparison between the sizes of the eleventh switch S11 and the twelfth switch S12 included in the replication master circuit MAC_R and the sizes of the thirteenth switch S13 and the fourteenth switch S14 included in the replication sub-circuit SBC_R.

[0065] Table 3

[0066]

[0067] Referring to Table 3, the eleventh switch S11 and the twelfth switch S12 included in the replication master circuit MAC_R are implemented with a third size of 3SZ, and the thirteenth switch S13 and the fourteenth switch S14 included in the replication sub-circuit SBC_R are implemented with a fourth size of 4SZ. The sizes in Table 3 are independent of the sizes in Tables 1 and 2. Because the fourth size 4SZ is smaller than the third size 3SZ, the thirteenth switch S13 and the fourteenth switch S14 included in the replication sub-circuit SBC_R can be implemented with a smaller size than the eleventh switch S11 and the twelfth switch S12 included in the replication master circuit MAC_R. Therefore, the replication sub-current sIp_R can be smaller than the replication master current mIp_R.

[0068] Table 4

[0069]

[0070] Referring to Table 4, the eleventh switch S11 included in the replication master circuit MAC_R is implemented with a first size of 1SZ, the twelfth switch S12 is implemented with a second size of 2SZ, the thirteenth switch S13 included in the replication sub-circuit SBC_R is implemented with a third size of 3SZ, and the fourteenth switch S14 is implemented with a fourth size of 4ZS. The sizes in Table 4 are independent of the sizes in Tables 1 to 3. The second size 2SZ can be smaller than the first size 1SZ, and the fourth size 4SZ can be smaller than the third size 3SZ. The third size 3SZ can be smaller than the first size 1SZ, and the fourth size 4SZ can be smaller than the second size 2SZ. That is, the switches included in the replication sub-circuit SBC_R can be implemented smaller than the switches included in the replication master circuit MAC_R. In addition, the size of the thirteenth switch S13 included in the replication sub-circuit SBC_R can be implemented to be equal to or smaller than the size of the twelfth switch S12 included in the replication master circuit MAC_R.

[0071] Table 5 shows the table including the following: Figure 3 A comparison between the size of the switch in the first transmission circuit 1TRAN and the size of the switch included in the replication circuit REP.

[0072] Table 5

[0073]

[0074]

[0075] Referring to Table 5, the switches included in the main circuit MAC can have a maximum first size of 1SZ, the switches included in the replica main circuit MAC_R can be implemented with a third size of 3SZ which is less than the first size of 1SZ, the switches included in the replica sub-circuit SBC_R can be implemented with a fourth size of 4SZ which is less than the third size of 3SZ, and the switches included in the sub-circuit SBC can have a minimum second size of 2SZ.

[0076] Table 6

[0077]

[0078] Referring to Table 6, the third switch S3 and the fifth switch S5 included in the main circuit MAC can have the largest first size 1SZ, and the fourteenth switch S14 included in the replication sub-circuit SBC_R can have the smallest eighth size 8SZ. For example, the eleventh switch S11 included in the replication main circuit MAC_R can be implemented smaller than the third switch S3 and the fifth switch S5 included in the main circuit MAC, and the twelfth switch S12 included in the replication main circuit MAC_R can be implemented smaller than the fourth switch S4 and the sixth switch S6 included in the main circuit MAC. The thirteenth switch S13 included in the replication main circuit MAC_R can be implemented smaller than the seventh switch S7 and the ninth switch S9 included in the main circuit MAC, and the fourteenth switch S14 included in the replication main circuit MAC_R can be implemented smaller than the eighth switch S8 and the tenth switch S10 included in the main circuit MAC.

[0079] Figure 7 This is a diagram illustrating the size of a transistor included in a replication circuit according to an embodiment of the present disclosure.

[0080] Reference Figure 6 and Figure 7 The transistor TR may include a drain DR and a source SC formed in the active region ACT of the wafer, and a gate GT formed on the active region ACT. When the eleventh switch S11 is described as an example, the drain DR may be connected to the sixth node N6, the source SC may be connected to the drain of the twelfth switch S12, and the gate GT may be connected to a terminal to which a ground voltage GND is applied. The size of the eleventh switch S11 can be determined based on the width W and length L of the transistor TR. When the twelfth switch S12 is described as an example, the drain DR may be connected to the eleventh switch S11, the source SC may be connected to the seventh node N7, and the gate GT may be connected to the sixth node N6. The size of the twelfth switch S12 can be determined based on the width W and length L of the transistor TR. As the width W and length L of the transistor TR configuring the eleventh switch S11 and the twelfth switch S12 decrease, the replication main current mIp_R of the replication main circuit MAC_R can be reduced.

[0081] Figure 8 This is a diagram illustrating the current flow in the replication master circuit of the replication circuit according to an embodiment of the present disclosure, and Figure 9 This is a diagram illustrating the amount of current flowing in the replicating sub-circuit of the replication circuit according to an embodiment of the present disclosure.

[0082] Reference Figure 3 , Figure 6 and Figure 8The first main current 1mIp and the second main current 2mIp can have due to the input to Figure 3 The waveform is caused by the input signal IN and the inverted input signal INb of the first transmission circuit 1TRAN. However, since there is no signal input to the replication circuit REP, the replication main current mIp_R can remain at a constant value. Therefore, Figure 1 The main current in the oscillator 1000 can be obtained by replicating the main current mIp_R with Figure 2 The total main current mIp_T is calculated by adding the first main current 1mIp and the second main current 2mIp of each of the first transmission circuit 1TRAN to the kth transmission circuit kTRAN.

[0083] Reference Figure 3 , Figure 6 and Figure 9 The first sub-current 1sIp and the second sub-current 2sIp can have due to the input to Figure 3 The waveform is caused by the input signal IN and the inverted input signal INb of the first transmission circuit 1TRAN. However, since there is no signal input to the replication circuit REP, the replicator current sIp_R can remain at a constant value. Therefore, Figure 1 The subcurrent quantity in the oscillator 1000 can be obtained by replicating the subcurrent quantity sIp_R with Figure 2 The total subcurrent sIp_T is calculated by adding the first subcurrent 1sIp and the second subcurrent 2sIp of each of the first transmission circuits 1TRAN to the kth transmission circuit kTRAN.

[0084] Figure 10 This is a diagram showing the total current of the replication circuit and the total current of the oscillator according to an embodiment of the present disclosure.

[0085] Reference Figure 10 According to Table 3, based on the switch sizes, the total sub-current sIp_T of the transmission circuit is the smallest, and the replica sub-current sIp_R of the replication circuit REP is greater than the total sub-current sIp_T. Because the switches included in the replication master circuit MAC_R and the master circuit MAC are implemented with sizes larger than those included in the replication sub-circuit SBC_R and the sub-circuit SBC, the replication master current mIp_R and the total master current mIp_T are greater than the replication sub-current sIp_R and the total sub-current sIp_T. Because the switches included in the master circuit MAC are implemented with sizes larger than those included in the replication master circuit MAC_R, the total master current mIp_T is greater than the replication master current mIp_R. Therefore, Figure 1The total replica current Ip_R_T of the oscillator 1000 can remain constant as a whole, and the total current Ip_T can form a waveform in response to the input signal IN.

[0086] Figure 11 This is a diagram illustrating the current quantities of an oscillator based on the replication voltage and control voltage according to an embodiment of the present disclosure.

[0087] Reference Figure 11 When Figure 1 When the control voltage Vvco and replication voltage Vrep generated inside the oscillator 1000 are low, the amount of current flowing inside the oscillator 1000 decreases, and therefore the total replication current Ip_R_T and the total current Ip_T can decrease. As the total current Ip_T decreases, the amplitude PK also decreases, and therefore noise removal may be difficult. Conversely, when the control voltage Vvco and replication voltage Vrep are high, the amount of current flowing inside the oscillator 1000 increases, and therefore the total replication current Ip_R_T and the total current Ip_T can increase. As the total current Ip_T increases, the amplitude PK of the current also increases, and therefore the difference between the maximum peak value and the minimum peak value of the waveform increases. Therefore, noise removal becomes easier.

[0088] Various embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology has been used herein, it is for the purpose of describing embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein. Embodiments may be combined to form additional embodiments.

[0089] It should be noted that although the technical spirit of this disclosure has been described in conjunction with embodiments thereof, this is for illustrative purposes only and should not be construed as limiting. Those skilled in the art will understand that various modifications can be made without departing from the technical spirit of this disclosure and the appended claims.

[0090] For example, the logic gates and transistors provided as examples in the above embodiments can be implemented in different positions and types depending on the polarity of the input signal.

Claims

1. A replica circuit comprising: a first terminal supplied with a replica voltage having a positive voltage; a second terminal supplied with a ground voltage; a replica main circuit connected between the first terminal and the second terminal and forming a first current path in response to the replica voltage so as to replicate a current of a main circuit that generates a sub-clock and an inverted sub-clock in a voltage-controlled oscillator; and a replica sub-circuit connected in parallel with the replica main circuit between the first terminal and the second terminal and forming a second current path in response to the replica voltage so as to replicate a current of a sub-circuit that is used to reduce noise of the sub-clock and the inverted sub-clock in the voltage-controlled oscillator, wherein the replica main circuit causes a current flowing through the first current path to have a replica main current amount, and wherein the replica sub-circuit causes a current flowing through the second current path to have a replica sub-current amount that is smaller than the replica main current amount.

2. The replica circuit according to claim 1, wherein the replica main circuit includes a first switch and a second switch, the first switch and the second switch being connected in series between the first terminal and the second terminal.

3. The replica circuit according to claim 2, wherein the first switch includes a PMOS transistor, the PMOS transistor being connected between the first terminal and the second switch, and wherein a gate of the first switch is connected to a terminal supplied with the ground voltage.

4. The replica circuit according to claim 2, wherein the second switch includes an NMOS transistor, the NMOS transistor being connected between the first switch and the second terminal, and wherein a gate of the second switch is connected to the first terminal.

5. The replica circuit according to claim 1, wherein the replica sub-circuit includes: a third switch and a fourth switch, the third switch and the fourth switch being connected in series between the first terminal and the second terminal; and a first resistor and a second resistor, the first resistor and the second resistor being connected in parallel with the third switch and the fourth switch between the first terminal and the second terminal.

6. The replica circuit according to claim 5, wherein the third switch includes a PMOS transistor, the PMOS transistor being connected between the first terminal and the fourth switch, and wherein a gate of the third switch is connected to a node between the first resistor and the second resistor.

7. The replica circuit according to claim 5, wherein the fourth switch includes an NMOS transistor, the NMOS transistor being connected between the third switch and the second terminal, and wherein a gate of the fourth switch is connected to a node between the third switch and the fourth switch.

8. The replica circuit according to claim 5, wherein the first resistor and the second resistor are connected in series between the first terminal and the second terminal.

9. The replica circuit according to claim 5, wherein a resistance value of the first resistor is larger than a resistance value of the second resistor. ​ 10.The replica circuit of claim 1, wherein each of the replica master circuit and the replica slave circuit comprises a switch, and a size of the switch configured for the replica slave circuit is less than a size of the switch configured for the replica master circuit. 11.An oscillator comprising: a voltage-controlled oscillator operating according to a control voltage and comprising: a master circuit generating a clock and an inverted clock by inverting an input signal and an inverted input signal, respectively; and a slave circuit reducing noise of the clock and the inverted clock; a replica circuit operating according to a replica voltage and comprising: a replica master circuit replicating a voltage or a current of the master circuit; and a replica slave circuit replicating a voltage or a current of the slave circuit; and an amplifier outputting an amplified voltage to the voltage-controlled oscillator and the replica circuit by amplifying a difference between a reference voltage and the replica voltage to make the replica voltage and the control voltage equal to each other, wherein the voltage-controlled oscillator adjusts the control voltage in response to the amplified voltage, and the replica circuit maintains a level of the replica voltage in response to the amplified voltage, and wherein the level of the replica voltage is adjusted according to sizes of switches configured for the replica master circuit and the replica slave circuit. 12.The oscillator of claim 11, wherein the master circuit comprises: a first inverter operating according to the control voltage and outputting the clock by inverting the input signal; and a second inverter operating according to the control voltage and outputting the inverted clock by inverting the inverted input signal. 13.The oscillator of claim 12, wherein the slave circuit comprises: a third inverter operating according to the control voltage and outputting the inverted clock to an output node of the second inverter by inverting the clock; and a fourth inverter operating according to the control voltage and outputting the clock to an output node of the first inverter by inverting the inverted clock. 14.The oscillator of claim 13, wherein a slave current flowing inside the slave circuit is less than a master current flowing inside the master circuit. 15.The oscillator of claim 13, wherein each of the third inverter and the fourth inverter is less in size than each of the first inverter and the second inverter. 16.The oscillator of claim 11, a first switch and a second switch connected in series between a first terminal supplied with the replica voltage and a second terminal supplied with a ground voltage, and wherein the replica slave circuit comprises: wherein the replica master circuit comprises: a third switch and a fourth switch connected in series between the first terminal and the second terminal; and a first resistor and a second resistor connected in series between the first terminal and the second terminal. 17.The oscillator of claim 16, wherein the first switch comprises a PMOS transistor connected between the first terminal and the second switch, wherein the second switch comprises an NMOS transistor connected between the second terminal and the first resistor, and wherein the third switch comprises a PMOS transistor connected between the first terminal and the fourth switch, and wherein the fourth switch comprises an NMOS transistor connected between the second terminal and the second resistor. wherein the second switch comprises an NMOS transistor connected between the first switch and the second terminal, wherein the third switch comprises a PMOS transistor connected between the first terminal and the fourth switch, and wherein the fourth switch comprises an NMOS transistor connected between the third switch and the second terminal.

18. The oscillator of claim 17, wherein a gate of the first switch is connected to a terminal that is supplied with the ground voltage, wherein a gate of the second switch is connected to the first terminal, wherein a gate of the third switch is connected to a node between the first resistor and the second resistor, and wherein a gate of the fourth switch is connected to a node between the third switch and the fourth switch.

19. The oscillator of claim 16, wherein a size of each of the third switch and the fourth switch is smaller than a size of each of the first switch and the second switch.

20. The oscillator of claim 16, wherein a resistance value of the first resistor is greater than a resistance value of the second resistor.

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