A dynamic latch comparator

Abstract

The present invention provides a dynamic latch comparator. The dynamic latch includes a latch circuit and a flag signal generation circuit. The latch circuit is specifically a double-input and double-output latch circuit. The dynamic latch further includes a first level decision circuit and a second level decision circuit for correspondingly buffering the two outputs of the latch circuit, and further includes a third level decision circuit for buffering the output of the flag signal generation circuit. The present invention solves the problem of excessive comparator input offset voltage during the quantization process, improves the gain of the comparator, reduces the input offset voltage, can drive a larger current, and reduces the influence of dynamic offset.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of communication devices, and particularly relates to a dynamic latch comparator. Background Art

[0002] With the increasing application fields of communication and multimedia technologies, digital signal processing technology has developed rapidly. Therefore, as a bridge between analog systems and digital systems, analog-to-digital converters (ADCs) face more challenging difficulties. A high-performance comparator is one of the most basic components of most ADCs, and it greatly affects various performance parameters of ADCs, such as speed, accuracy, power consumption, etc. The offset of a comparator can be divided into static offset and dynamic offset. Static offset is caused by device mismatches and can be reduced by modifying the device dimensions to lower the static offset voltage of the comparator. Dynamic offset is caused by the change of the common mode of the comparator. Ideally, the comparator gain is infinite, that is, the accuracy is infinite, and it can accurately identify the input signal to obtain an accurate quantization result. However, in the actual quantization process, the input and output load capacitances of the comparator change, resulting in a change in the input common-mode level of the comparator, causing offset and seriously affecting the dynamic performance of the comparator. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a dynamic latch comparator to solve the problem of excessive input offset voltage of the comparator during the quantization process in view of the deficiencies of the prior art.

[0004] The technical solution of the present invention to solve the above technical problem is as follows: A dynamic latch comparator, the dynamic latch includes a latch circuit and a flag signal generation circuit, the latch circuit is specifically a dual-input dual-output latch circuit, the dynamic latch further includes a first level decision circuit and a second level decision circuit for correspondingly buffering the two outputs of the latch circuit, and further includes a third level decision circuit for buffering the output of the flag signal generation circuit;

[0005] The power supply terminals of the latch circuit, the power supply terminals of the flag signal generation circuit, the power supply terminals of the first level decision circuit, the power supply terminals of the second level decision circuit, and the power supply terminals of the third level decision circuit are all connected to a power supply, and the ground terminals of the latch circuit, the ground terminals of the flag signal generation circuit, the ground terminals of the first level decision circuit, the ground terminals of the second level decision circuit, and the ground terminals of the third level decision circuit are all grounded;

[0006] Two output terminals of the latch circuit are respectively connected to the input terminal of the first level decision circuit and the input terminal of the second level decision circuit. The output terminals of the first level decision circuit and the second level decision circuit are both connected to the input terminal of the flag signal generation circuit, and the output terminal of the flag signal generation circuit is connected to the input terminal of the three-level decision circuit.

[0007] The beneficial effects of the present invention are as follows: By means of the level decision circuit, the latch circuit and the flag signal generation circuit, the problem of excessive input offset voltage of the comparator during the quantization process is solved, the gain of the comparator is improved, the input offset voltage is reduced, and a relatively large current can be driven, reducing the influence of dynamic offset.

[0008] On the basis of the above technical solution, the present invention can be further improved as follows.

[0009] Further, the latch circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a first control switch, a second control switch, and a third control switch. Among them, the first MOS transistor, the second MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are PMOS transistors, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the seventh MOS transistor are NMOS transistors, the first control switch and the second control switch are both NMOS transistors, and the third control switch is a PMOS transistor. The source electrodes of the sixth MOS transistor, the third control switch, and the eighth MOS transistor are all connected to the power supply. The source electrodes of the third MOS transistor, the fourth MOS transistor, the first control switch, the second control switch, the fifth MOS transistor, and the seventh MOS transistor are all grounded. The gate electrodes of the first control switch, the second control switch, and the third control switch are all used to access a clock signal. The gate electrodes of the first MOS transistor and the second MOS transistor are used to access two input signals correspondingly. The source electrode of the first MOS transistor, the drain electrode of the third control switch, and the source electrode of the second MOS transistor are connected together. The drain electrode of the first MOS transistor, the drain electrode of the third MOS transistor, the gate electrode of the fourth MOS transistor, the drain electrode of the first control switch, the gate electrode of the fifth MOS transistor, and the gate electrode of the sixth MOS transistor are connected together. The drain electrode of the second MOS transistor, the gate electrode of the third MOS transistor, the drain electrode of the fourth MOS transistor, the drain electrode of the second control switch, the gate electrode of the seventh MOS transistor, and the gate electrode of the eighth MOS transistor are connected together. The drain electrodes of the fifth MOS transistor and the sixth MOS transistor are connected and form an output terminal of the latch circuit. The drain electrodes of the seventh MOS transistor and the eighth MOS transistor are connected and form another output terminal of the latch circuit.

[0010] The beneficial effects of adopting the above further solution are as follows: It can force one output to be high level and the other to be low level according to the comparison of the magnitudes of the input differential pair, and can reset the comparator and the flag signal valid to high level or compare the magnitudes of the input differential pair, solving the problem of excessive input offset voltage of the comparator during the quantization process.

[0011] Further, the first level decision circuit includes a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, and a twelfth MOS transistor; wherein, the ninth MOS transistor and the eleventh MOS transistor are NMOS transistors, and the tenth MOS transistor and the twelfth MOS transistor are PMOS transistors; the sources of the tenth MOS transistor and the twelfth MOS transistor are both connected to the power supply, the sources of the ninth MOS transistor and the eleventh MOS transistor are both grounded, the gates of the ninth MOS transistor and the tenth MOS transistor are connected together and form the input end of the first level decision circuit, the drains of the ninth MOS transistor, the tenth MOS transistor, the gate of the eleventh MOS transistor, and the gate of the twelfth MOS transistor are connected together, and the drain of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor and forms the output end of the first level decision circuit.

[0012] The beneficial effect of adopting the above further solution is: it can buffer the output signal of the comparator, improve the gain of the comparator, and thus achieve the purpose of reducing the input offset voltage.

[0013] Further, the second level decision circuit includes a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, and a sixteenth MOS transistor; wherein, the thirteenth MOS transistor and the fifteenth MOS transistor are NMOS transistors, and the fourteenth MOS transistor and the sixteenth MOS transistor are PMOS transistors; the sources of the fourteenth MOS transistor and the sixteenth MOS transistor are both connected to the power supply, the sources of the thirteenth MOS transistor and the fifteenth MOS transistor are both grounded, the drains of the thirteenth MOS transistor, the fourteenth MOS transistor, the gate of the fifteenth MOS transistor, and the gate of the sixteenth MOS transistor are connected together, the gates of the thirteenth MOS transistor and the fourteenth MOS transistor are connected together and form the input end of the second level decision circuit, and the drain of the fifteenth MOS transistor is connected to the drain of the sixteenth MOS transistor and forms the output end of the second level decision circuit.

[0014] The beneficial effect of adopting the above further solution is: it buffers the latch, can convert the signal output by the latch circuit into logic levels 0 and 1, and by pulling the output end of the latch to 0 - vdda, it improves the gain of the comparator and achieves the purpose of reducing the input offset voltage.

[0015] Further, the flag signal generation circuit includes a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, and a twentieth MOS transistor. Among them, the seventeenth MOS transistor and the eighteenth MOS transistor are PMOS transistors, and the nineteenth MOS transistor and the twentieth MOS transistor are NMOS transistors. The sources of the seventeenth MOS transistor and the eighteenth MOS transistor are both connected to the power supply. The source of the twentieth MOS transistor is grounded. The source of the nineteenth MOS transistor is connected to the drain of the twentieth MOS transistor. The gates of the eighteenth MOS transistor and the nineteenth MOS transistor are connected together to form an input terminal of the flag signal generation circuit. The gates of the seventeenth MOS transistor and the twentieth MOS transistor are connected together to form another input terminal of the flag signal generation circuit. The drains of the seventeenth MOS transistor, the eighteenth MOS transistor, and the nineteenth MOS transistor are connected together to form the output terminal of the flag signal generation circuit.

[0016] The beneficial effect of adopting the above further solution is: it can enable asynchronous control of the clock. Compared with a static comparator, the dynamic comparator is faster. In the reset stage, there is no current path, the static power consumption is almost zero, and the output voltage range can reach rail-to-rail.

[0017] Further, the third-level decision circuit includes a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, and a twenty-fourth MOS transistor. Among them, the twenty-first MOS transistor and the twenty-third MOS transistor are PMOS transistors, and the twenty-second MOS transistor and the twenty-fourth MOS transistor are NMOS transistors. The sources of the twenty-first MOS transistor and the twenty-third MOS transistor are both connected to the power supply. The sources of the twenty-second MOS transistor and the twenty-fourth MOS transistor are both grounded. The drains of the twenty-first MOS transistor, the twenty-second MOS transistor, the gate of the twenty-third MOS transistor, and the gate of the twenty-fourth MOS transistor are connected together. The drains of the twenty-third MOS transistor and the twenty-fourth MOS transistor are connected together. The gates of the twenty-first MOS transistor and the twenty-second MOS transistor are connected together to form the input terminal of the third-level decision circuit.

[0018] The beneficial effect of adopting the above further solution is: it can buffer the flag signal generation circuit, generate an output voltage with low offset, improve the gain of the comparator, and achieve the purpose of reducing the input offset voltage. Description of the Drawings

[0019] Figure 1 It is a circuit diagram of a dynamic latch comparator provided by an embodiment of the present invention.

[0020] Figure 2 Circuit diagram of the latch circuit provided by the embodiment of the present invention;

[0021] Figure 3 Circuit diagram of the first level decision circuit provided by the embodiment of the present invention;

[0022] Figure 4 Circuit diagram of the second level decision circuit provided by the embodiment of the present invention;

[0023] Figure 5 Circuit diagram of the flag signal generation circuit provided by the embodiment of the present invention;

[0024] Figure 6 Circuit diagram of the third level decision circuit provided by the embodiment of the present invention;

[0025] Figure 7 Functional simulation diagram of the dynamic latch comparator provided by the embodiment of the present invention;

[0026] Figure 8 Monte Carlo simulation diagram of the dynamic latch comparator provided by the embodiment of the present invention. Detailed implementation manners

[0027] The principles and features of the present invention will be described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not intended to limit the scope of the present invention.

[0028] Figure 1 Circuit diagram of a dynamic latch comparator provided by the embodiment of the present invention.

[0029] As Figure 1 shown, a dynamic latch comparator, the dynamic latch includes a latch circuit and a flag signal generation circuit. The latch circuit is specifically a dual-input and dual-output latch circuit. The dynamic latch further includes a first level decision circuit and a second level decision circuit for correspondingly buffering the two outputs of the latch circuit, and further includes a third level decision circuit for buffering the output of the flag signal generation circuit;

[0030] The power supply terminals of the latch circuit, the flag signal generation circuit, the first level decision circuit, the second level decision circuit, and the third level decision circuit are all connected to the power supply, and the grounding terminals of the latch circuit, the flag signal generation circuit, the first level decision circuit, the second level decision circuit, and the third level decision circuit are all grounded;

[0031] The two output terminals of the latch circuit are respectively connected to the input terminal of the first level decision circuit and the input terminal of the second level decision circuit. The output terminal of the first level decision circuit and the output terminal of the second level decision circuit are both connected to the input terminal of the flag signal generation circuit. The output terminal of the flag signal generation circuit is connected to the input terminal of the three-level decision circuit.

[0032] It should be understood that by using a level decision circuit (i.e., the second level decision circuit) as the output buffer stage of the comparator to buffer the output signal of the comparator, the output terminal of the latch can be pulled to 0 - Vdd, which can improve the gain of the comparator, reduce the input offset voltage, and drive a larger current.

[0033] Specifically, the output terminal of the latch circuit is connected to the input terminal of the level decision circuit (i.e., the first level decision circuit and / or the second level decision circuit) to buffer the latch. The output terminal of the level decision circuit (i.e., the first level decision circuit and / or the second level decision circuit) that buffers the latch is connected to the input terminal of the flag signal generation circuit. The output terminal of the flag signal generation circuit is connected to the input terminal of the level decision circuit (i.e., the third level decision circuit) that buffers the flag signal generation circuit. The output terminal of the level decision circuit (i.e., the first level decision circuit and / or the second level decision circuit) that buffers the latch forms the output terminal of the dynamic latch comparator with a low input offset voltage.

[0034] It should be understood that compared with a static comparator, a dynamic comparator is faster. In the reset stage, there is no current path, the static power consumption is almost zero, and the output voltage range can reach rail - to - rail.

[0035] In the above - mentioned embodiment, by using a level decision circuit, a latch circuit, and a flag signal generation circuit, the problem of excessive input offset voltage of the comparator during the quantization process is solved, the gain of the comparator is improved, the input offset voltage is reduced, and a larger current can be driven, reducing the influence of dynamic offset.

[0036] Optionally, as an embodiment of the present invention, such as Figure 1 and 2As shown, the latch circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a first control switch, a second control switch, and a third control switch. Among them, the first MOS transistor, the second MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are PMOS transistors; the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the seventh MOS transistor are NMOS transistors; the first control switch and the second control switch are both NMOS transistors; the third control switch is a PMOS transistor. The source of the sixth MOS transistor, the source of the third control switch, and the source of the eighth MOS transistor are all connected to the power supply. The source of the third MOS transistor, the source of the fourth MOS transistor, the source of the first control switch, the source of the second control switch, the source of the fifth MOS transistor, and the source of the seventh MOS transistor are all grounded. The gates of the first control switch, the second control switch, and the third control switch are all used to access a clock signal. The gates of the first MOS transistor and the second MOS transistor are used to access two input signals respectively. The source of the first MOS transistor, the drain of the third control switch, and the source of the second MOS transistor are connected together. The drain of the first MOS transistor, the drain of the third MOS transistor, the gate of the fourth MOS transistor, the drain of the first control switch, the gate of the fifth MOS transistor, and the gate of the sixth MOS transistor are connected together. The drain of the second MOS transistor, the gate of the third MOS transistor, the drain of the fourth MOS transistor, the drain of the second control switch, the gate of the seventh MOS transistor, and the gate of the eighth MOS transistor are connected together. The drain of the fifth MOS transistor and the drain of the sixth MOS transistor are connected and form an output terminal of the latch circuit. The drain of the seventh MOS transistor and the drain of the eighth MOS transistor are connected and form another output terminal of the latch circuit.

[0037] Preferably, the two input signals are an input signal inp and an input signal inn respectively.

[0038] It should be understood that the latch forces one output to a high level and the other to a low level according to the comparison of the magnitudes of the input differential pair.

[0039] Specifically, as Figure 1 and 2As shown, the latch circuit includes a first MOS transistor PM1, a second MOS transistor PM2, a third MOS transistor NM3, a fourth MOS transistor NM4, a fifth MOS transistor NM5, a sixth MOS transistor PM6, a seventh MOS transistor NM7, an eighth MOS transistor PM8, a first control switch S1, a second control switch S2, and a third control switch S3; wherein, the first MOS transistor PM1, the second MOS transistor PM2, the sixth MOS transistor PM6, and the eighth MOS transistor PM8 are PMOS transistors, the third MOS transistor NM3, the fourth MOS transistor NM4, the fifth MOS transistor NM5, and the seventh MOS transistor NM7 are NMOS transistors, the first control switch S1 and the second control switch S2 are both NMOS transistors, and the third control switch S3 is a PMOS transistor; the source of the sixth MOS transistor PM6, the source of the third control switch S3, and the source of the eighth MOS transistor PM8 are all connected to the power supply vdda, the source of the third MOS transistor NM3, the source of the fourth MOS transistor NM4, the source of the first control switch S1, the source of the second control switch S2, the source of the fifth MOS transistor NM5, and the source of the seventh MOS transistor NM7 are all grounded, the gates of the first control switch S1, the second control switch S2, and the third control switch S3 are all used to access a clock signal, the gates of the first MOS transistor PM1 and the second MOS transistor PM2 are used to access two input signals correspondingly, the source of the first MOS transistor PM1, the drain of the third control switch S3, and the source of the second MOS transistor PM2 are connected together, the drain of the first MOS transistor PM1, the drain of the third MOS transistor NM3, the gate of the fourth MOS transistor NM4, the drain of the first control switch S1, the gate of the fifth MOS transistor NM5, and the gate of the sixth MOS transistor PM6 are connected together, the drain of the second MOS transistor PM2, the gate of the third MOS transistor NM3, the drain of the fourth MOS transistor NM4, the drain of the second control switch S2, the gate of the seventh MOS transistor NM7, and the gate of the eighth MOS transistor PM8 are connected together, the drain of the fifth MOS transistor NM5 and the drain of the sixth MOS transistor PM6 are connected and form an output terminal of the latch circuit, and the drain of the seventh MOS transistor NM7 and the drain of the eighth MOS transistor PM8 are connected and form another output terminal of the latch circuit.

[0040] Specifically, the latch includes input pair transistors PM1-PM2, cross-coupled transistors NM3-NM4, clock control switches S1, S2, S3, and inverters M5-M8 (i.e., the fifth MOS transistor NM5, the sixth MOS transistor PM6, the seventh MOS transistor NM7, and the eighth MOS transistor PM8). The gate of MOS transistor PM1 is connected to the input signal inp; the gate of MOS transistor PM2 is connected to the input signal inn; the sources of MOS transistor PM1, MOS transistor PM2, and the drain of S3 are connected together; the sources of S3, MOS transistor PM6, and MOS transistor PM8 are connected to the power supply vdda; the drains of MOS transistor PM1, MOS transistor NM3, the gate of MOS transistor NM4, the drain of S1, the gate of MOS transistor NM5, and the gate of MOS transistor PM6 are connected together; the drains of MOS transistor PM2, MOS transistor PM4, the gate of MOS transistor NM3, the drain of S2, the gate of MOS transistor NM7, and the gate of MOS transistor PM8 are connected together; the gates of the clock control switches S1, S2, S3 are connected to the clock signal CLKc, and the sources of MOS transistor NM3, MOS transistor NM4, MOS transistor NM5, MOS transistor NM7, S1, and S2 are grounded; the drains of MOS transistor NM5 and MOS transistor PM6 are connected to the gates of MOS transistor NM9 and MOS transistor PM10 in the level decision circuit (i.e., the first level decision circuit); the drains of MOS transistor PM7 and MOS transistor PM8 are connected to the gates of MOS transistor NM13 and MOS transistor PM14 in the level decision circuit (i.e., the second level decision circuit). The latch forces one output to a high level and the other to a low level according to the comparison of the magnitudes of the input differential pair.

[0041] In the above embodiments, one output can be forced to a high level and the other to a low level according to the comparison of the magnitudes of the input differential pair, and the comparator and the flag signal valid can be reset to a high level or the magnitudes of the input differential pair can be compared, solving the problem of excessive input offset voltage of the comparator during the quantization process.

[0042] Optionally, as an embodiment of the present invention, as Figures 1 to 3As shown, the first level decision circuit includes a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, and a twelfth MOS transistor. Among them, the ninth MOS transistor and the eleventh MOS transistor are NMOS transistors, and the tenth MOS transistor and the twelfth MOS transistor are PMOS transistors. The sources of the tenth MOS transistor and the twelfth MOS transistor are both connected to the power supply. The sources of the ninth MOS transistor and the eleventh MOS transistor are both grounded. The gates of the ninth MOS transistor and the tenth MOS transistor are connected together to form the input terminal of the first level decision circuit. The drains of the ninth MOS transistor, the tenth MOS transistor, the gate of the eleventh MOS transistor, and the gate of the twelfth MOS transistor are connected together. The drain of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor to form the output terminal of the first level decision circuit.

[0043] It should be understood that the level decision circuit converts the signal output by the latch circuit into logic levels 0 and 1. By pulling the output terminal of the latch to 0 - vdda, the gain of the comparator is increased, achieving the purpose of reducing the input offset voltage.

[0044] Specifically, as Figures 1 to 3 shown, the first level decision circuit includes a ninth MOS transistor NM9, a tenth MOS transistor PM10, an eleventh MOS transistor NM11, and a twelfth MOS transistor PM12. Among them, the ninth MOS transistor NM9 and the eleventh MOS transistor NM11 are NMOS transistors, and the tenth MOS transistor PM10 and the twelfth MOS transistor PM12 are PMOS transistors. The sources of the tenth MOS transistor PM10 and the twelfth MOS transistor PM12 are both connected to the power supply vdda. The sources of the ninth MOS transistor NM9 and the eleventh MOS transistor NM11 are both grounded. The gates of the ninth MOS transistor NM9 and the tenth MOS transistor PM10 are connected together to form the input terminal of the first level decision circuit. The drain of the ninth MOS transistor, the drain of the tenth MOS transistor PM10, the gate of the eleventh MOS transistor NM11, and the gate of the twelfth MOS transistor PM12 are connected together. The drain of the eleventh MOS transistor NM11 is connected to the drain of the twelfth MOS transistor PM12 to form the output terminal of the first level decision circuit.

[0045] It should be understood that PMOS transistors are selected as the input pair transistors to operate normally within the input common - mode voltage range and reduce the influence of dynamic offset.

[0046] In the above - mentioned embodiment, it can buffer the output signal of the comparator, increase the gain of the comparator, and thus achieve the purpose of reducing the input offset voltage.

[0047] Optionally, as an embodiment of the present invention, as Figure 1 and 4 shown, the second level decision circuit includes a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, and a sixteenth MOS transistor; wherein, the thirteenth MOS transistor and the fifteenth MOS transistor are NMOS transistors, and the fourteenth MOS transistor and the sixteenth MOS transistor are PMOS transistors; the sources of the fourteenth MOS transistor and the sixteenth MOS transistor are both connected to the power supply, the sources of the thirteenth MOS transistor and the fifteenth MOS transistor are both grounded, the drains of the thirteenth MOS transistor, the fourteenth MOS transistor, the gate of the fifteenth MOS transistor, and the gate of the sixteenth MOS transistor are connected together, the gates of the thirteenth MOS transistor and the fourteenth MOS transistor are connected and form the input end of the second level decision circuit, and the drains of the fifteenth MOS transistor and the sixteenth MOS transistor are connected and form the output end of the second level decision circuit.

[0048] It should be understood that using the level decision circuit as the output buffer stage of the comparator can buffer the output signal of the comparator, pull the output end of the latch to 0-Vdd, increase the gain of the comparator, reduce the input offset voltage, and drive a larger current.

[0049] Specifically, as Figure 1 and 4 shown, the second level decision circuit includes a thirteenth MOS transistor NM13, a fourteenth MOS transistor PM14, a fifteenth MOS transistor NM15, and a sixteenth MOS transistor PM16; wherein, the thirteenth MOS transistor NM13 and the fifteenth MOS transistor NM15 are NMOS transistors, and the fourteenth MOS transistor PM14 and the sixteenth MOS transistor PM16 are PMOS transistors; the sources of the fourteenth MOS transistor PM14 and the sixteenth MOS transistor PM16 are both connected to the power supply vdda, the sources of the thirteenth MOS transistor NM13 and the fifteenth MOS transistor NM15 are both grounded, the drains of the thirteenth MOS transistor NM13, the fourteenth MOS transistor PM14, the gate of the fifteenth MOS transistor NM15, and the gate of the sixteenth MOS transistor PM16 are connected together, the gates of the thirteenth MOS transistor NM13 and the fourteenth MOS transistor PM14 are connected and form the input end of the second level decision circuit, and the drains of the fifteenth MOS transistor NM15 and the sixteenth MOS transistor PM16 are connected and form the output end of the second level decision circuit.

[0050] It should be understood that the drain of MOS transistor PM8 is connected to the gates of MOS transistors NM13 and PM14 in the level decision circuit (i.e., the second level decision circuit).

[0051] It should be understood that the second level decision circuit is used to buffer the latch.

[0052] In the above embodiment, buffering the latch can convert the signal output by the latch circuit into logic levels 0 and 1. By pulling the output terminal of the latch to 0 - vdda, the gain of the comparator is increased, achieving the purpose of reducing the input offset voltage.

[0053] Optionally, as an embodiment of the present invention, as Figure 1 and 5 shown, the flag signal generation circuit includes the seventeenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor, and the twentieth MOS transistor; among them, the seventeenth MOS transistor and the eighteenth MOS transistor are PMOS transistors, and the nineteenth MOS transistor and the twentieth MOS transistor are NMOS transistors; the sources of the seventeenth MOS transistor and the eighteenth MOS transistor are both connected to the power supply, the source of the twentieth MOS transistor is grounded, the source of the nineteenth MOS transistor and the drain of the twentieth MOS transistor are connected together, the gates of the eighteenth MOS transistor and the nineteenth MOS transistor are connected and form an input terminal of the flag signal generation circuit, the gates of the seventeenth MOS transistor and the twentieth MOS transistor are connected and form another input terminal of the flag signal generation circuit, and the drains of the seventeenth MOS transistor, the eighteenth MOS transistor, and the nineteenth MOS transistor are connected and form the output terminal of the flag signal generation circuit.

[0054] It should be understood that the flag signal generation circuit is used to enable the asynchronous control clock.

[0055] Specifically, as Figure 1 and 5As shown, the flag signal generation circuit includes a seventeenth MOS transistor PM17, an eighteenth MOS transistor PM18, a nineteenth MOS transistor NM19, and a twentieth MOS transistor NM20. Among them, the seventeenth MOS transistor PM17 and the eighteenth MOS transistor PM18 are PMOS transistors, and the nineteenth MOS transistor NM19 and the twentieth MOS transistor NM20 are NMOS transistors. The source electrodes of the seventeenth MOS transistor PM17 and the eighteenth MOS transistor PM18 are both connected to the power supply vdda, the source electrode of the twentieth MOS transistor NM20 is grounded, the source electrode of the nineteenth MOS transistor NM19 is connected to the drain electrode of the twentieth MOS transistor NM20, the gate electrodes of the eighteenth MOS transistor PM18 and the nineteenth MOS transistor NM19 are connected together and form an input terminal of the flag signal generation circuit, the gate electrodes of the seventeenth MOS transistor PM17 and the twentieth MOS transistor NM20 are connected together and form another input terminal of the flag signal generation circuit, and the drain electrodes of the seventeenth MOS transistor PM17, the eighteenth MOS transistor PM18, and the nineteenth MOS transistor NM19 are connected together and form the output terminal of the flag signal generation circuit.

[0056] It should be understood that the seventeenth MOS transistor PM17 and the eighteenth MOS transistor PM18 can be PMOS transistors, and the nineteenth MOS transistor NM19 and the twentieth MOS transistor NM20 can be cross-coupled transistors.

[0057] Specifically, the flag signal generation circuit includes MOS transistors M17 - M20 (i.e., the seventeenth MOS transistor PM17, the eighteenth MOS transistor PM18, the nineteenth MOS transistor NM19, and the twentieth MOS transistor NM20). The gate electrode of MOS transistor PM17, the gate electrode of MOS transistor NM20, the drain electrode of MOS transistor NM11, and the drain electrode of MOS transistor PM12; the drain electrodes of MOS transistor PM17, MOS transistor PM18, MOS transistor NM19, and the level decision circuit (i.e., the third level decision circuit) the gate electrode of MOS transistor PM21 and the gate electrode of MOS transistor NM22 are connected together; the gate electrodes of MOS transistor PM18 and MOS transistor NM19, the drain electrode of MOS transistor NM15, and the drain electrode of MOS transistor PM16 are connected together; the source electrode of MOS transistor NM19 is connected to the drain electrode of MOS transistor NM20; the source electrodes of MOS transistor PM17 and MOS transistor PM18 are connected to the power supply vdda; the source electrode of MOS transistor NM20 is grounded. The valid signal is pulled to a high level to enable the asynchronous control clock.

[0058] In the above embodiments, asynchronous control of the clock can be enabled. Compared with the static comparator, the dynamic comparator is faster. In the reset stage, there is no current path, the static power consumption is almost zero, and the output voltage range can reach rail-to-rail.

[0059] Optionally, as an embodiment of the present invention, as Figure 1 and 6 shown, the third-level decision circuit includes a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, and a twenty-fourth MOS transistor; wherein, the twenty-first MOS transistor and the twenty-third MOS transistor are PMOS transistors, and the twenty-second MOS transistor and the twenty-fourth MOS transistor are NMOS transistors; the sources of the twenty-first MOS transistor and the twenty-third MOS transistor are both connected to the power supply, the sources of the twenty-second MOS transistor and the twenty-fourth MOS transistor are both grounded, the drains of the twenty-first MOS transistor, the drains of the twenty-second MOS transistor, the gates of the twenty-third MOS transistor, and the gates of the twenty-fourth MOS transistor are connected together, the drains of the twenty-third MOS transistor and the twenty-fourth MOS transistor are connected together, and the gates of the twenty-first MOS transistor and the twenty-second MOS transistor are connected and constitute the input end of the third-level decision circuit.

[0060] It should be understood that the third-level decision circuit is used to buffer the flag signal generation circuit.

[0061] Specifically, as Figure 1 and 6 shown,

[0062] The third-level decision circuit includes a twenty-first MOS transistor PM21, a twenty-second MOS transistor NM22, a twenty-third MOS transistor PM23, and a twenty-fourth MOS transistor NM24; wherein, the twenty-first MOS transistor PM21 and the twenty-third MOS transistor PM23 are PMOS transistors, and the twenty-second MOS transistor NM22 and the twenty-fourth MOS transistor NM24 are NMOS transistors; the sources of the twenty-first MOS transistor PM21 and the twenty-third MOS transistor PM23 are both connected to the power supply vdda, the sources of the twenty-second MOS transistor NM22 and the twenty-fourth MOS transistor NM24 are both grounded, the drains of the twenty-first MOS transistor PM21, the twenty-second MOS transistor NM22, the gates of the twenty-third MOS transistor PM23, and the twenty-fourth MOS transistor NM24 are connected together, the drains of the twenty-third MOS transistor PM23 and the twenty-fourth MOS transistor NM24 are connected together, and the gates of the twenty-first MOS transistor PM21 and the twenty-second MOS transistor NM22 are connected and form the input end of the third-level decision circuit.

[0063] It should be understood that the twenty-first MOS transistor PM21 and the twenty-third MOS transistor PM23 can be PMOS transistors, and the twenty-second MOS transistor NM22 and the twenty-fourth MOS transistor NM24 can be cross-coupled transistors.

[0064] It should be understood that the drains of the MOS transistor PM17, the MOS transistor PM18, the MOS transistor NM19 are connected to the gates of the MOS transistor PM21 and the MOS transistor NM22 in the level decision circuit (i.e., the third-level decision circuit).

[0065] In the above embodiment, it can buffer the flag signal generation circuit, generate an output voltage with low offset, improve the gain of the comparator, and achieve the purpose of reducing the input offset voltage.

[0066] Optionally, as another embodiment of the present invention, when CLKc is at a high level, the comparator and the flag signal valid are reset to a high level. When CLKc becomes low, the magnitudes of the comparison input differential pair are compared, and the latch (i.e., the latch circuit) forces one output to a high level and the other to a low level according to the comparison result. The output passes through the buffering of the level decision circuit (i.e., the second-level decision circuit) to generate an output voltage with low offset.

[0067] Optionally, as another embodiment of the present invention, the level decision circuit includes inverters M9 - M16 (i.e., the ninth MOS transistor NM9, the tenth MOS transistor PM10, the eleventh MOS transistor NM11, the twelfth MOS transistor PM12, the thirteenth MOS transistor NM13, the fourteenth MOS transistor PM14, the fifteenth MOS transistor NM15, and the sixteenth MOS transistor PM16), and inverters M21 - M24 (i.e., the twenty - first MOS transistor PM21, the twenty - second MOS transistor NM22, the twenty - third MOS transistor PM23, and the twenty - fourth MOS transistor NM24). The gates of MOS transistor NM9 and MOS transistor PM10 are connected together with the drains of MOS transistor NM5 and MOS transistor PM6; the drains of MOS transistor NM9 and MOS transistor PM10 are connected together with the gates of MOS transistor NM11 and MOS transistor PM12; the drains of MOS transistor NM11 and MOS transistor PM12 are connected together with the gates of MOS transistor PM17 and MOS transistor NM20 in the flag signal generation circuit; the gates of MOS transistor NM13 and MOS transistor PM14 are connected together with the drains of MOS transistor NM7 and MOS transistor PM8; the drains of MOS transistor NM13 and MOS transistor PM14 are connected together with the gates of MOS transistor NM15 and MOS transistor PM16; the drains of MOS transistor NM15 and MOS transistor PM16 are connected together with the gates of MOS transistor PM18 and MOS transistor NM19 in the flag signal generation circuit; the sources of MOS transistor NM9, MOS transistor NM11, MOS transistor NM13, MOS transistor NM15, MOS transistor NM22, and MOS transistor NM24 are grounded; the sources of MOS transistor PM10, MOS transistor PM12, MOS transistor PM14, MOS transistor PM16, MOS transistor PM21, and MOS transistor PM23 are connected to the power supply vdda; the gates of MOS transistor PM21 and MOS transistor NM22 are connected together with the drains of MOS transistor PM17, MOS transistor PM18, and MOS transistor NM19 in the flag signal generation circuit; the drains of MOS transistor PM21 and MOS transistor NM22 are connected together with the gates of MOS transistor PM23 and MOS transistor NM24; the drains of MOS transistor PM23 and MOS transistor NM24 are connected together. The level decision circuit converts the signal output by the latch circuit into logic levels 0 and 1, and by pulling the output terminal of the latch to 0 - vdda, the gain of the comparator is increased, achieving the purpose of reducing the input offset voltage.

[0068] Optionally, as another embodiment of the present invention, as Figure 7As shown, when CLKc is at a high level, the output voltages outp and outn are reset to a high level; when CLKc is at a low level and inp > inn, the output voltage outp of the comparator becomes high, outn becomes low, and the comparator flag signal valid becomes high; when CLKc is at a low level and inp < inn, the output voltage outp of the comparator becomes low, outn becomes high, and the comparator flag signal valid remains high.

[0069] Optionally, as another embodiment of the present invention, as Figure 8 shown, through multiple experiments, it can be obtained that the average value of the comparator offset voltage is -36.3805 mV, and the standard deviation is 2.67510 μV. Therefore, the 3o input offset voltage is approximately 8.0253 μV. The present invention reduces the input offset voltage of the comparator by adding a level decision circuit.

[0070] Optionally, as another embodiment of the present invention, the present invention solves the problem of excessive input offset voltage of the comparator during the quantization process, and uses a level decision circuit as the output buffer stage of the comparator to buffer the output signal of the comparator, which can pull the output terminal of the latch to 0 - Vdd, improve the gain of the comparator, reduce the input offset voltage, and drive a larger current; and compared with the static comparator, the dynamic comparator is faster. In the reset stage, there is no current path, the static power consumption is almost zero, and the output voltage range can reach rail - to - rail; at the same time, the input pair transistors are selected as PMOS transistors to work normally within the input common - mode voltage range and reduce the influence of dynamic offset.

[0071] Optionally, as another embodiment of the present invention, the usage method of the present invention is as follows: 1) In the reset stage, when CLKc is at a high level, the comparator is reset. At this time, the clock control switch S3 is turned off, S1 and S2 are turned on, the connection point VP between the gates of MOS transistor NM5 and MOS transistor PM6 and the connection point VI between the gates of MOS transistor NM7 and MOS transistor PM8 are pulled down to a low potential, and the output voltages outp and outn are reset to a high level through the inverter formed by M5 - M8 (i.e., the fifth MOS transistor NM5, the sixth MOS transistor PM6, the seventh MOS transistor NM7, and the eighth MOS transistor PM8).

[0072] 2) Comparison stage: When CLKc is at a low level, the comparator is in the working state. At this time, the clock control switch S3 is turned on, S1 and S2 are turned off, and the input signals inp and inn are connected to the gates of PM1 and PM2. When inp > inn, the charging speed of VP is less than that of VI. When charged to a certain extent, the NM3 transistor is turned on, VP is pulled down to a low level, VI is pulled up to a high level, the output voltage outp of the comparator becomes a high level, outn becomes a low level, and the comparator flag signal valid becomes a high level; when inp < inn, the charging speed of VP is greater than that of VI. When charged to a certain extent, the NM4 transistor is turned on, VP becomes a high level, VI becomes a high level, the output voltage outp of the comparator becomes a low level, outn becomes a high level, and the comparator flag signal valid remains a high level.

[0073] Optionally, as another embodiment of the present invention, the advantages of the present invention are that the problems of excessive input offset voltage of the comparator during the quantization process are solved by the level decision circuit, the latch circuit and the flag signal generation circuit, the gain of the comparator is improved, the input offset voltage is reduced, and a larger current can be driven, reducing the influence of dynamic offset.

[0074] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A dynamic latch comparator, characterized in that The dynamic latch comparator includes a latch circuit and a flag signal generation circuit. The latch circuit is specifically a dual-input and dual-output latch circuit. The dynamic latch further includes a first level decision circuit and a second level decision circuit for correspondingly buffering the two outputs of the latch circuit, and also includes a third level decision circuit for buffering the output of the flag signal generation circuit; The power supply terminals of the latch circuit, the power supply terminals of the flag signal generation circuit, the power supply terminals of the first level decision circuit, the power supply terminals of the second level decision circuit, and the power supply terminals of the third level decision circuit are all connected to the power supply. The grounding terminals of the latch circuit, the grounding terminals of the flag signal generation circuit, the grounding terminals of the first level decision circuit, the grounding terminals of the second level decision circuit, and the grounding terminals of the third level decision circuit are all grounded; The two output terminals of the latch circuit are respectively connected to the input terminals of the first level decision circuit and the input terminals of the second level decision circuit. The output terminals of the first level decision circuit and the output terminals of the second level decision circuit are both connected to the input terminals of the flag signal generation circuit. The output terminal of the flag signal generation circuit is connected to the input terminal of the three-level decision circuit; The first level decision circuit includes a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, and a twelfth MOS transistor. Among them, the ninth MOS transistor and the eleventh MOS transistor are NMOS transistors, and the tenth MOS transistor and the twelfth MOS transistor are PMOS transistors. The source electrodes of the tenth MOS transistor and the twelfth MOS transistor are both connected to the power supply. The source electrodes of the ninth MOS transistor and the eleventh MOS transistor are both grounded. The gate electrode of the ninth MOS transistor is connected to the gate electrode of the tenth MOS transistor and constitutes the input terminal of the first level decision circuit. The drain electrode of the ninth MOS transistor, the drain electrode of the tenth MOS transistor, the gate electrode of the eleventh MOS transistor, and the gate electrode of the twelfth MOS transistor are connected together. The drain electrode of the eleventh MOS transistor is connected to the drain electrode of the twelfth MOS transistor and constitutes the output terminal of the first level decision circuit; The second level decision circuit includes a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, and a sixteenth MOS transistor; among them, the thirteenth MOS transistor and the fifteenth MOS transistor are NMOS transistors, and the fourteenth MOS transistor and the sixteenth MOS transistor are PMOS transistors; the source electrodes of the fourteenth MOS transistor and the sixteenth MOS transistor are both connected to the power supply, the source electrodes of the thirteenth MOS transistor and the fifteenth MOS transistor are both grounded, the drain electrode of the thirteenth MOS transistor, the drain electrode of the fourteenth MOS transistor, the gate electrode of the fifteenth MOS transistor, and the gate electrode of the sixteenth MOS transistor are connected together, the gate electrode of the thirteenth MOS transistor and the gate electrode of the fourteenth MOS transistor are connected and form the input end of the second level decision circuit, and the drain electrode of the fifteenth MOS transistor and the drain electrode of the sixteenth MOS transistor are connected and form the output end of the second level decision circuit.

2. The dynamic latch comparator according to claim 1, wherein The latch circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a first control switch, a second control switch, and a third control switch; wherein, the first MOS transistor, the second MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are PMOS transistors, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, and the seventh MOS transistor are NMOS transistors, the first control switch and the second control switch are both NMOS transistors, and the third control switch is a PMOS transistor; the source of the sixth MOS transistor, the source of the third control switch, and the source of the eighth MOS transistor are all connected to the power supply, the source of the third MOS transistor, the source of the fourth MOS transistor, the source of the first control switch, the source of the second control switch, the source of the fifth MOS transistor, and the source of the seventh MOS transistor are all grounded, the gates of the first control switch, the second control switch, and the third control switch are all used to access a clock signal, the gates of the first MOS transistor and the second MOS transistor are used to access two input signals correspondingly, the source of the first MOS transistor, the drain of the third control switch, and the source of the second MOS transistor are connected together, the drain of the first MOS transistor, the drain of the third MOS transistor, the gate of the fourth MOS transistor, the drain of the first control switch, the gate of the fifth MOS transistor, and the gate of the sixth MOS transistor are connected together, the drain of the second MOS transistor, the gate of the third MOS transistor, the drain of the fourth MOS transistor, the drain of the second control switch, the gate of the seventh MOS transistor, and the gate of the eighth MOS transistor are connected together, the drain of the fifth MOS transistor and the drain of the sixth MOS transistor are connected and form an output terminal of the latch circuit, and the drain of the seventh MOS transistor and the drain of the eighth MOS transistor are connected and form another output terminal of the latch circuit.

3. The dynamic latch comparator according to claim 1, wherein The flag signal generation circuit includes a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, and a twentieth MOS transistor; wherein, the seventeenth MOS transistor and the eighteenth MOS transistor are PMOS transistors, the nineteenth MOS transistor and the twentieth MOS transistor are NMOS transistors; the source electrodes of the seventeenth MOS transistor and the eighteenth MOS transistor are both connected to the power supply, the source electrode of the twentieth MOS transistor is grounded, the source electrode of the nineteenth MOS transistor is connected to the drain electrode of the twentieth MOS transistor, the gate electrodes of the eighteenth MOS transistor and the nineteenth MOS transistor are connected together and form an input terminal of the flag signal generation circuit, the gate electrodes of the seventeenth MOS transistor and the twentieth MOS transistor are connected together and form another input terminal of the flag signal generation circuit, and the drain electrodes of the seventeenth MOS transistor, the eighteenth MOS transistor, and the nineteenth MOS transistor are connected together and form the output terminal of the flag signal generation circuit.

4. The dynamic latch comparator according to claim 1, wherein The third-level decision circuit includes a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, and a twenty-fourth MOS transistor; wherein, the twenty-first MOS transistor and the twenty-third MOS transistor are PMOS transistors, the twenty-second MOS transistor and the twenty-fourth MOS transistor are NMOS transistors; the source electrodes of the twenty-first MOS transistor and the twenty-third MOS transistor are both connected to the power supply, the source electrodes of the twenty-second MOS transistor and the twenty-fourth MOS transistor are both grounded, the drain electrode of the twenty-first MOS transistor, the drain electrode of the twenty-second MOS transistor, the gate electrode of the twenty-third MOS transistor, and the gate electrode of the twenty-fourth MOS transistor are connected together, the drain electrodes of the twenty-third MOS transistor and the twenty-fourth MOS transistor are connected together, and the gate electrodes of the twenty-first MOS transistor and the twenty-second MOS transistor are connected together and form the input terminal of the third-level decision circuit.

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