Computation-in-memory dynamic random access memory

Abstract

A computation-in-memory dynamic random access memory bit cell is provided. The cell includes a first transistor having an on / off state controlled by a weight bit stored across a capacitor. The first transistor is connected in series with a current source transistor connected between the first transistor and a read bit line. When the first transistor is in the on state, an activation voltage controls whether the current source transistor conducts current.

Description

[0001] Claim of priority under 35 U.S.C. § 119

[0002] This patent application claims priority to non-provisional application No. 16 / 810,475, filed on March 5, 2020, entitled “COMPUTER-IN-MEMORY DYNAMICRANDOM ACCESS MEMORY,” which is assigned to the assignee of the present application and is expressly incorporated herein by reference. Technical Field

[0003] The present application relates to in-memory computing, and more particularly, to a dynamic random access memory in-memory computing bit cell. Background Art

[0004] Computer processing of data typically uses a von Neumann architecture, where data is retrieved from memory for processing in arithmetic and logic units (ALUs). In compute-intensive applications such as machine learning, the flow of data in and out of memory becomes a bottleneck for processing speed. To address this data movement bottleneck, compute-in-memory architectures have been developed, in which data processing hardware is distributed across bit cells. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a dynamic random access memory (DRAM) multiplication and accumulation circuit (MAC) is provided, the DRAM MAC including: a read bit line; a first transistor; a capacitor connected between a gate of the first transistor and ground; a second transistor connected between the read bit line and the first transistor; and a digital-to-analog converter configured to convert an input bit into an activation voltage and drive the gate of the second transistor with the activation voltage.

[0006] According to a second aspect of the present disclosure, a dynamic random access memory (DRAM) array is provided, comprising: a plurality of DRAM bit cells arranged into a plurality of columns and a plurality of rows, each DRAM bit cell being located at the intersection of a corresponding column in the column and a corresponding row in the row; a plurality of read bit lines corresponding to the plurality of columns; and a digital-to-analog converter configured to convert an input vector into a plurality of activation voltages corresponding to the plurality of rows, each DRAM bit cell being configured to store a weight bit and to discharge the read bit line of the corresponding column in response to the activation voltage of the corresponding row and the stored weight bit.

[0007] According to a third aspect of the present disclosure, an in-memory computing method for a dynamic random access memory (DRAM) bit cell is provided, the in-memory computing method comprising: turning on a first transistor in response to a first weight bit stored across a capacitor; turning on a second transistor in response to a first input bit during a turn-on time period when the first transistor is turned on; and conducting charge from a charged read bit line to ground through the turned-on first transistor and through the turned-on second transistor for a duration of the turn-on time period.

[0008] According to a fourth aspect of the present disclosure, a dynamic random access memory (DRAM) multiplication and accumulation circuit (MAC) is provided, the DRAM MAC comprising: a read bit line; a first component for charging the read bit line in response to a first polarity of a stored weight bit and in response to an input bit; and a second component for discharging the read bit line in response to a second polarity of the stored weight bit and in response to the input bit.

[0009] These and other advantageous features will be better understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A A first example in-DRAM memory calculation bit cell for AND logical function calculation according to one aspect of the present disclosure is illustrated.

[0011] Figure 1B A second example in-DRAM memory calculation bit cell for AND logical function calculation according to one aspect of the present disclosure is illustrated.

[0012] Figure 2 An example filter for computing bit cells in DRAM memory multiplied by two-bit weights is illustrated according to one aspect of the present disclosure.

[0013] Figure 3 An example filter of computational bit cells within DRAM memory for multiplication of three-bit weights is illustrated according to one aspect of the present disclosure.

[0014] Figure 4 Illustrated is an array of computational bit cells within a DRAM memory arranged in rows and columns to form multiple filters according to one aspect of the present disclosure.

[0015] Figure 5 An example analog-to-digital converter for converting a read bit line voltage into a digital value is illustrated according to one aspect of the present disclosure.

[0016] Figure 6 Illustrated is an example in-DRAM memory computation bit cell for exclusive-OR (XNOR) logic function computation according to one aspect of the present disclosure.

[0017] Figure 7 is a flow chart for computing bit cell operations within an example DRAM memory according to one aspect of the present disclosure.

[0018] Figure 8 Some example electronic systems including a computational bit cell array within a DRAM memory according to one aspect of the present disclosure are illustrated.

[0019] Embodiments of the present disclosure and their advantages are best understood by referring to the following detailed description.It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures. DETAILED DESCRIPTION

[0020] Using traditional von Neumann architectures for machine learning applications is cumbersome because the flow of data in and out of memory becomes a bottleneck for increasing processing speed. Therefore, in-memory compute bitcell architectures have been developed, in which the data processing hardware is distributed across the bitcells. To implement in-memory compute bitcells, the traditional choices are static random access memory (SRAM) architectures or dynamic random access memory (DRAM) architectures. Of these two options, DRAM in-memory compute architectures are advantageous because they are denser than comparable SRAM alternatives.

[0021] While digital DRAM in-memory computing architectures offer improved density, their implementation has encountered numerous challenges. For example, digital DRAM in-memory computing architectures are often used for machine learning applications. However, it is noted that DRAM typically uses large channel length devices that provide low leakage but are relatively slow and have relatively high capacitance. To address these issues, this paper provides an analog DRAM in-memory computing architecture. The longer channel length of the DRAM architecture actually benefits the analog architecture. Furthermore, the current domain computations performed by the analog architecture disclosed herein are not hindered by the relatively high device capacitance of DRAM implementations.

[0022] The analog current domain calculations are performed by DRAM bit cells that have an architecture that depends on whether the weight bit stored in the DRAM bit cell has a polarity (positive or negative sign). Unipolar DRAM bit cells will be discussed first, followed by DRAM bit cells where the stored weight bit is a signed stored weight bit. Example three transistor (3T) DRAM bit cell 100 in Figure 1A, a weight bit for unipolar storage. Capacitor C stores a weight bit (w0) for bit cell 100. Before the weight bit is written to bit cell 100, the write bit line (referred to herein as the bit line for simplicity) BL is charged according to the binary value of the weight bit. If the weight bit is binary one, the bit line BL is charged to the power supply voltage VDD (in a high-level effective implementation). Conversely, if the weight bit is binary zero, the bit line BL is discharged to ground (the bit line state can be reversed in a low-level effective implementation). In order to write the weight bit to bit cell 100, the write word line (WWL) is asserted to the power supply voltage VDD to turn on the n-type metal oxide semiconductor (NMOS) access transistor M0 connected between the bit line BL and the positive plate of capacitor C. The negative plate of capacitor C is grounded. Depending on the binary value of the weight bit, capacitor C will be charged to the power supply voltage VDD or discharged.

[0023] Although the bit cells 100 are used to multiply input bits with weight bits to form a multiply and accumulate circuit, it is noted that in deep learning applications, such multiplications are performed on various input bits and various corresponding weight bits in a convolution operation, which is often referred to as a "filter." In deep learning techniques, input bits are often referred to as "activations" because, similar to biological neurons, these neurons are also considered to process activations. Therefore, a filter will include multiple bit cells 100 for multiplying corresponding activations (input bits) with stored weight bits.

[0024] To form the activation, a digital-to-analog converter (DAC) ( Figure 1A ), which is not shown in the figure, is used to convert the input bit into an activation voltage. In the bit cell 100, one of the activation voltages (Act) drives the gate of the NMOS transistor M2. The source of the transistor M2 is connected to the drain of the NMOS transistor M1 having a source connected to ground. The positive plate of the capacitor C is also connected to the gate of the transistor M1. Therefore, the stored weight bit controls whether the transistor M1 is turned on or off. As used herein, "connected" refers to a direct electrical connection, although such a direct connection can be achieved through an intermediate element such as a resistor, a capacitor or an inductor. The drain of the transistor M2 is connected to the read bit line (RBL). The read bit line is charged to an evaluation voltage (e.g., charged to the power supply voltage VDD) before an evaluation phase in which the stored weight bits and the input bits are multiplied and accumulated to adjust the voltage of the read bit line.

[0025] Assume that the weight bit (w0) is a binary 1 value, causing transistor M1 to turn on. Depending on the value of the activation voltage, transistor M2 is then turned on to act as a current source, which conducts charge from the read bit line through transistors M2 and M1 to ground. However, if the activation voltage or the weight bit is ground (binary zero), then no charge is conducted from the read bit line to ground.

[0026] Thus, the DRAM bit cell 100 acts as an AND gate to compute the binary multiplication of the input bit and the weight bit. Figure 1A The DRAM bit cell 100 may then be modified to perform a multiplication of the input bit and the stored weight bit using an exclusive-OR (XNOR) operation to account for the polarity of the stored weight bit. Regardless of whether the multiplication is performed using an AND or NOR operation, the resulting current domain calculation is highly advantageous because it is compatible with the longer channel lengths and relatively large device capacitances resulting from DRAM manufacturing technology.

[0027] It will be appreciated that the positions of transistors M1 and M2 may be reversed in alternative embodiments, e.g. Figure 1B 100. In bit cell 150, the source of transistor M2 is connected to ground, and the drain of transistor M2 is connected to the source of transistor M1, which in turn has a drain connected to a read bit line. The remainder of DRAM bit cell 150 is arranged as discussed for DRAM bit cell 100.

[0028] The resulting multiply and accumulate circuit may be repeated to form a filter for multiplying a multi-bit weight with an input vector bit (or multiple input vector bits). Figure 2FIGURE 2 shows an example filter 200 for computing bit cells in a DRAM memory for a 2-bit weight calculation. A first DRAM bit cell 205 stores the most significant bit (w1) of the 2-bit weight, while a second DRAM bit cell 210 stores the least significant bit (w0) of the 2-bit weight. As discussed with respect to bit cell 100, each of bit cells 205 and 210 includes a capacitor C, a transistor M0, a transistor M1, and a transistor M2. DAC 215 converts an input vector (e.g., a two-bit input vector) into a current via a variable current source 220. Current source 220 drives current into the drain and gate of a diode-connected NMOS transistor M3. The gate of NMOS transistor M3 is connected to the gate of transistor M2 in bit cell 205 via a pulse-width modulated switch S1 (e.g., a switching transistor). Similarly, the gate of NMOS transistor M3 is connected to the gate of transistor M2 in bit cell 210 via another pulse-width modulated switch S1 (e.g., another switching transistor). Note, however, that the source of each transistor M2 is coupled to ground via a corresponding transistor M1. To provide diode-connected transistor M3 with the same source voltage as seen by each transistor M2, the source of diode-connected transistor M3 is coupled to ground via NMOS transistor M4. The gate of transistor M4 is connected to the supply node for supply voltage VDD. Thus, transistor M4 mimics the behavior of transistor M1 in each bit cell 205 or 210 that is programmed to a binary 1 value, such that its transistor M1 is turned on. In those programmed bit cells, diode-connected transistor M3 thus forms a current mirror with the programmed bit cell's transistor M2, such that transistor M2 conducts a mirrored version of the current from current source 220. In embodiments where the positions of transistors M1 and M2 are reversed as described above, transistor M4 may be omitted.

[0029] The pulse width modulator 225 controls the pulse width modulation of the switch S1 according to the bit weight for the bit cells 205 and 210. Since the bit cell 205 is storing the most significant bit w1, the switch S1 in the bit cell 205 is pulsed on for a pulse width that is greater than twice the on time of the switch S1 in the bit cell 210. After the pulse width for the switch S1 has expired (the current mode calculation ends), the charge Q released from the read bit line is multiplied by the input vector bit (or bits) and the stored weight bits. Once the read bit line voltage is evaluated to determine the result of the current mode calculation, the reset switch S2 in each bit cell 205 and 210 is closed, which is connected between the gate of the corresponding transistor M2 and ground to discharge the gate voltage. A new evaluation phase can then be performed with the new value of the input bit and / or the new value of the stored weight bits.

[0030] It will be appreciated that if the width of the stored weights is greater than two bits, then additional bit cells will be used. For example, a three bit wide weight filter 300 in Figure 3 . Bit cell 305 stores the most significant bit (Wmsb) of a three-bit wide weight. Bit cell 310 stores the next most significant bit (Wmsb-1). Finally, bit cell 315 stores the least significant bit (Wmsb-2). Each bit cell in filter 300 can be formed as discussed with respect to bit cell 100. DAC 320 functions as discussed with respect to DAC 215 to drive the gate of each transistor M2 with an activation voltage so that each transistor conducts a mirror current generated by the digital-to-analog conversion of the input vector bit (or bits). The following discussion will assume that the input vector has the same precision (bit width) as the stored weights, but it will be understood that it can have a higher or lower precision than the stored weights.

[0031] The pulse width modulation associated with DAC 320 provides a maximum on-time or pulse width for bit cell 305, causing its transistor M2 to conduct the activation current I_act. A pulse width modulator (not shown) provides bit cell 310 with an on-time that is half that of bit cell 300, causing transistor M2 in bit cell 305 to conduct a current of I_act / 2. Similarly, a pulse width modulator (not shown) provides bit cell 315 with an on-time that is half that of bit cell 310, causing transistor M2 in bit cell 315 to conduct a current of I_act / 4. It will be appreciated that this binary weighting of the on-times can be extended to n-bit wide memory weight embodiments, where n is a positive integer. Typically, the pulse width (on-time) of a bit cell in an n-bit wide implementation is 2 (wtbit) where wtbit is the bit weight of the bit cell.

[0032] The resulting filter performs a multiply-accumulate (MAC) function on the input vector bits multiplied by the stored weights. For example, in filter 300, the MAC value can be represented as follows:

[0033]

[0034] Where W[i] is the stored weight bit in the i-th bit cell, and In[i] is the current value of the current conducted by the transistor M2 of the i-th bit cell.

[0035] Multiple filters can be used to form a computation-in-memory DRAM array of bit cells. For example, Figure 4A two-bit filter array 400 of bit cells is shown in FIG. The bit cells are arranged in columns and rows. Each column of bit cells shares the same read bit line and write word line. Each bit cell is located at the intersection of a corresponding row and a corresponding column. In the array 400, there are six columns, where each column defines a two-bit filter ranging from a first filter ( Filt1 ) to a sixth filter ( Filt6 ). Each row of bit cells shares the same current weight from a DAC (not shown). Each filter extends across three stored two-bit binary weights in the column direction. For example, the first filter stores the first two-bit weight W1 as bit W2 <1> and W2 <0> , and the third two-bit weight is stored as bit W3 <1> and W3 <2> Each stored bit is multiplied by the corresponding input bit represented by the current. For example, bit W2 <1> Use current Iact2 to multiply, and bit W2 <0> Multiply the current by 0.5*Iact2. Finally, bit W3 <1> Use current Iact3 to multiply, and bit W3 <0> The current 0.5*Iact3 is multiplied. The remaining filters are arranged in a similar manner. For clarity, the weights of the remaining filters are not shown.

[0036] An analog-to-digital converter (ADC) converts the voltage remaining on each read bit line after the evaluation phase to determine the result of the multiply-accumulate function. Figure 5 An example ADC 500 for an array 505 of bit units is shown in FIG. Array 505 is arranged as discussed for array 400. Referring again to FIG. Figure 4 , each read bit line for the filter extends across several different weights. These different weights are located at the current from the corresponding DAC multiplied. Figure 5 As shown in , there is therefore one DAC 515 for each multi-bit weight of a given filter (the filters in array 505 are not shown for clarity of illustration, but are similar to the filters discussed for array 400). Each filter (which could also be represented as a column of bit cells) has its own read bit line, but for clarity of illustration, Figure 5Only a single read bit line with voltage Vsum is shown in FIG. To increase the capacitance of the read bit line so that it can store sufficient charge when the read bit line is precharged prior to the evaluation phase, a read bit line capacitor C1 can be connected between the read bit line and ground. However, if the read bit line capacitance is sufficiently large, capacitor C1 can be omitted in an alternative embodiment. Prior to the evaluation phase, the read bit line is precharged to the power supply voltage VDD. After precharging, the controller 510 enables each DAC 515 to begin providing the appropriate current as determined by the input vector bits. Simultaneously, the controller 510 starts the counter 520 to begin counting in response to cycles of a clock signal from a clock source (not shown). Based on the current and the stored weight, the charge from the read bit line will be discharged at a corresponding rate. The comparator 525 compares the read bit line voltage with a threshold voltage. When the read bit line voltage is discharged below the threshold voltage, the comparator 525 triggers the counter 520 to stop counting. The resulting count represents a digital value obtained by multiplying the corresponding input bit by the stored weight bits. The counter 520 thus acts as a time-to-digital converter and can be easily scaled to the desired DRAM technology node.The various filters can all be computed in parallel, so that there is one counter 520 and one comparator 525 for each filter.

[0037] As previously mentioned, the bit cell 100 is configured to perform a logical AND function of the stored binary weight bit and the input bit. If both the binary weight and the input bit are logically true, the bit cell 100 will discharge the read bit line for any applicable pulse width, taking into account the significance of the stored weight bit. However, in machine learning applications, it may be useful for the stored binary weight to have a polarity, i.e., a positive or negative sign. Since the bit cell 100 can only discharge the read bit line, the stored binary weight bit can be considered to have only one polarity. However Figure 6 The bit cell 600 shown in allows the stored binary weight bit w1 to have a positive or negative sign. The bit cell 600 is arranged similarly to that discussed for the bit cell 100, but also includes a PMOS transistor P1 having a source connected to a power supply node for the power supply voltage VDD. The drain of transistor P1 is connected to the source of PMOS transistor P2, and the drain of PMOS transistor P2 is connected to the drain of transistor M2 and the read bit line. A first bias signal Biasp drives the gate of transistor P2. Similarly, a second bias signal Biasn drives the gate of transistor M2. The polarity of the stored weight bit wt controls the first bias signal and the second bias signal. In the following discussion, it will be assumed that the positive polarity of the stored weight bit wt turns on transistor M2 and turns off transistor P2, while the negative polarity of the stored weight bit wt turns on transistor P2 and turns off transistor M2. However, in alternative embodiments, the polarity control can be reversed.

[0038] To assign polarity to the stored weight bit wt, a voltage value of 0V across the capacitor C can be considered equal to -1, while a positive value of the same capacitor voltage can be considered equal to a+1. When the stored weight bit wt is equal to a+1, the transistor M1 is turned on. Figure 2 , a second bias signal Biasn is generated as discussed with respect to the activation signal so that if the input bit is true, transistor M2 will conduct a mirror current during the appropriate conduction period to discharge the read bit line accordingly. However, if the stored weight bit wt is equal to a-1, transistors M1 and M2 are turned off. Conversely, since the gate of transistor P1 is connected to the gate of transistor M1, transistor P1 is turned on. If the input bit is true, a second current mirror (not shown) can then generate a first bias signal Biasp during the appropriate conduction period given the polarity to turn on transistor P2 to conduct a mirror current to charge the read bit line when the stored binary weight bit is equal to a-1. Therefore, it can be shown that the resulting operation of the bit cell 600 is equivalent to a logical XNOR of the stored weight bit and the input bit. Since the bit cell 600 can charge or discharge the read bit line, the read bit line is not precharged to the power supply voltage VDD before the evaluation phase, but is precharged to an intermediate voltage, such as VDD / 2.

[0039] In one embodiment, transistors P1 and P2 can be considered to form a first component for charging the read bit line in response to a first polarity of the stored weight bit and in response to an input bit. Similarly, transistors M1 and M2 can be considered to form a second component for discharging the read bit line in response to a second polarity of the stored weight bit and in response to an input bit.

[0040] Now about Figure 7 The flowchart of discusses a method of operating a computational bit cell within a DRAM memory. The method includes an act 700 of turning on a first transistor in response to a first weight bit stored across a capacitor. Turning on transistor M1 in bit cell 100 or bit cell 600 is an example of act 700. The method also includes an act 705 of turning on a second transistor during an on-time period in response to a first input bit when the first transistor is turned on. Turning on transistor M2 in bit cell 100 or bit cell 600 is an example of act 705. Finally, the method includes an act 710 of conducting charge from a charged read bit line to ground through the turned-on first transistor and through the turned-on second transistor for the duration of the on-time period. Discharging the read bit line through transistors M1 and M2 during the appropriate on-time period in bit cell 100 or bit cell 600 is an example of act 710.

[0041] The in-memory computation bit cell disclosed herein may be advantageously incorporated into any suitable mobile device or electronic system. Figure 8 As shown in FIG, a cellular phone 800, a laptop computer 805, and a tablet PC 810 according to the present disclosure can each include in-memory computing, such as a DRAM bit cell array for machine learning applications. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with in-memory computing constructed according to the present disclosure. Similarly, in-memory computing as disclosed herein can be incorporated into servers such as in cloud-based applications, or into servers such as in base stations in 5G systems.

[0042] It will be understood that many modifications, substitutions, and changes may be made to the materials, devices, configurations, and methods of use of the apparatus of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to that of the specific embodiments shown and described herein, as they are intended only as some examples thereof, but should be fully commensurate with the contents of the appended claims and their functional equivalents.

Claims

1. A dynamic random access memory (DRAM) multiplication and accumulation circuit (MAC), comprising: Read the bit line; a first transistor; a capacitor connected between the gate of the first transistor and ground; a second transistor connected between the read bit line and the first transistor; and a digital-to-analog converter configured to convert an input bit into an activation voltage and drive the gate of the second transistor with the activation voltage, The digital-to-analog converter comprises: a variable current source configured to generate a current in response to the input bit; and A diode-connected transistor, wherein the variable current source is further configured to drive the current into a terminal of the diode-connected transistor to generate the activation voltage.

2. The DRAM MAC according to claim 1 , further comprising: Write bit line; an access transistor connected between the write bit line and the capacitor; and A write word line is connected to the gate of the access transistor.

3. The DRAM MAC according to claim 1 , further comprising: Pulse Width Modulator; and First switch; wherein the gate of the diode-connected transistor is connected to the gate of the second transistor via the first switch, and wherein the pulse width modulator is further configured to control a conduction time of the first switch during an evaluation phase.

4. The DRAM MAC of claim 3 , wherein the digital-to-analog converter further comprises a third transistor connected between a source of the diode-connected transistor and ground, wherein a gate of the third transistor is connected to a power supply node for a power supply voltage.

5. The DRAM MAC according to claim 1 , further comprising: A reset switch is connected between the read bit line and a power supply node for a power supply voltage.

6. The DRAM MAC according to claim 1 , further comprising: An analog-to-digital converter is configured to convert the voltage of the read bit line into a digital value.

7. The DRAM MAC according to claim 3, further comprising: An analog-to-digital converter, the analog-to-digital converter comprising: a comparator configured to compare the voltage of the read bit line with a threshold voltage; and The method is configured to count from the start of the on-time to the detection by the comparator that the voltage for the read bit line has exceeded the threshold voltage.

8. The DRAM MAC according to claim 1 , further comprising: A read bit line capacitor is connected between the read bit line and ground.

9. The DRAM MAC of claim 1, wherein the DRAM MAC is integrated into a mobile device.

10. The DRAM MAC of claim 9, wherein the mobile device is a cellular phone.

11. A dynamic random access memory (DRAM) array comprising: a plurality of DRAM bit cells arranged in a plurality of columns and a plurality of rows, each DRAM bit cell being located at an intersection of a corresponding one of the columns and a corresponding one of the rows; a plurality of read bit lines corresponding to the plurality of columns; and a digital-to-analog converter configured to convert an input vector into a plurality of activation voltages corresponding to the plurality of rows, each DRAM bit cell configured to store a weight bit and discharge a read bit line of the corresponding column in response to the activation voltage of the corresponding row and the stored weight bit, The digital-to-analog converter comprises: a variable current source configured to generate a current in response to the stored weight bits; and A diode-connected transistor, wherein the variable current source is further configured to drive the current into a terminal of the diode-connected transistor to generate the activation voltage.

12. The DRAM array according to claim 11, further comprising: An analog-to-digital converter is configured to convert the voltage for each read bit line into a digital value.

13. The DRAM array of claim 11, wherein each column is configured to form a filter for deep learning applications.

14. The DRAM array of claim 11, wherein each DRAM bit cell is a three-transistor DRAM bit cell.

15. An in-memory computation method for a dynamic random access memory (DRAM) bit cell, comprising: turning on the first transistor in response to a first weight bit stored across the capacitor; When the first transistor is turned on, turning on the second transistor during an on-time period in response to a first input bit; as well as conducting charge from the charged read bit line to ground through the conductive first transistor and through the conductive second transistor for a duration of the conductive period, Wherein the method is performed during a first evaluation phase, the method further comprises: During the second assessment phase: In response to a second weight bit stored across the capacitor and in response to a second input bit, a third transistor in the DRAM bit cell is turned on to charge the read bit line.

16. The in-memory computing method of claim 15, wherein the method is performed during a first evaluation phase, the method further comprising: During the second assessment phase: The first transistor is turned off in response to a second weight bit stored across the capacitor.

17. A dynamic random access memory (DRAM) multiplication and accumulation circuit (MAC), comprising: Read the bit line; a capacitor configured to store a weight bit; a first component for charging the read bit line in response to a first polarity of the stored weight bit and in response to an input bit; and Second means for discharging the read bit line in response to a second polarity of the stored weight bit and in response to the input bit.

18. The DRAM MAC of claim 17 , wherein the first component comprises: a first transistor; a capacitor connected between the gate of the first transistor and ground; A second transistor is connected between the read bit line and the first transistor.

19. A dynamic random access memory (DRAM) multiply and accumulate circuit (MAC), the DRAM MAC comprising: Read the bit line; a first transistor having a first terminal connected to the read bit line; a capacitor connected between the gate of the first transistor and ground; a second transistor connected between the second terminal of the first transistor and ground; and a digital-to-analog converter configured to convert an input bit into an activation voltage and drive the gate of the second transistor with the activation voltage, The digital-to-analog converter comprises: a variable current source configured to generate a current in response to the stored weight bits; and A diode-connected transistor, wherein the variable current source is further configured to drive the current into a terminal of the diode-connected transistor to generate the activation voltage.

20. The DRAM MAC of claim 19, further comprising: Write bit line; an access transistor connected between the write bit line and the capacitor; and A write word line is connected to the gate of the access transistor.

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