Integrated circuit with high-speed clock bypass before reset

Abstract

An integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input being coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input being coupled to the divider output, the second clock input being coupled to the reference clock input, and the bypass logic output being coupled to the clock domain input. The bypass logic selectively bypasses the PLL and the divider in response to a bypass control signal triggered by a reset signal. The reset signal also triggers a reset control signal that is delayed relative to the bypass control signal.

Description

Background Art

[0001] The popularity of electronic devices and integrated circuit (IC) technology has led to the commercialization of IC products. As new electronic devices are developed and IC technology advances, new IC products are commercialized. An example IC product required for electronic devices is a multimedia or infotainment system-on-chip (SoC).

[0002] In an example infotainment SoC, there are a large number of different clock domains and different operating modes to save power. Example operating modes include functional mode and low power mode. In addition, full reset and partial reset options are provided in the example infotainment SoC, where the partial reset results in a lower frequency clock signal being provided to some of the different clock domains. In the case of a synchronous reset mechanism (e.g., partial reset), many clock domains consume more power during the reset interval than during the functional mode. The end result is that during the reset interval, the power consumption of the SoC may be 1.5 to 4 times that during the functional mode. This high power consumption may trigger a power failure and / or may not meet customer specifications for the infotainment SoC. Summary of the invention

[0003] According to at least one example of the present disclosure, an integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input being coupled to the PLL clock output; and a bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input being coupled to the divider output, the second clock input being coupled to the reference clock input, and the bypass logic output being coupled to the clock domain input. The integrated circuit also includes reset management logic, the logic having: a controller including a controller input; and delay logic coupled to the controller. The delay logic includes a reset input, a first delay logic output, and a second delay logic output, the reset input being configured to receive a reset signal, the first delay logic output being coupled to the bypass control input, and the second delay logic output being coupled to the controller input. The reset management logic is configured to: provide a bypass control signal at a first reset output in response to a reset signal; and provide a reset control signal delayed relative to the bypass control signal at a second reset output in response to the reset signal.

[0004] According to at least one example of the present disclosure, an infotainment circuit includes: a first clock domain having a first clock domain input; a second clock domain having a second clock domain input; and clock management logic coupled to the first and second clock domains. The clock management logic includes: a first PLL having a first reference clock input and a first PLL clock output; a first divider having a first divider input and a first divider output, the first divider input being coupled to the first PLL clock output; a second PLL having a second reference clock input and a second PLL clock output; a second divider having a second divider input and a second divider output, the second divider input being coupled to the second PLL clock output, and the second divider output being coupled to the second clock domain input; and a bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input being coupled to the first divider output, the second clock input being coupled to the first reference clock input, and the bypass logic output being coupled to the first clock domain input. The infotainment circuit also includes a reset management logic having: a controller including a controller input; a delay logic coupled to the controller, the delay logic including a reset input, a first delay logic output, and a second delay logic output, the reset input being configured to receive a reset signal, the first delay logic output being coupled to a bypass control input, and the second delay logic output being coupled to the controller input. The reset management logic is configured to: provide a bypass control signal at the first reset output in response to the reset signal; and provide a reset control signal delayed relative to the bypass control signal at the second reset output in response to the reset signal.

[0005] According to at least one example of the present disclosure, a system includes: an infotainment chip; and a peripheral device connected to the infotainment chip. The infotainment chip includes: a first clock domain having a first clock domain input; a second clock domain having a second clock domain input, the second clock domain including an output pin to the peripheral device; and clock management logic connected to the first and second clock domains. The clock management logic includes: a first PLL having a first reference clock input and a first PLL clock output; a first divider having a first divider input and a first divider output, the first divider input is connected to the first PLL clock output; a second PLL having a second reference clock input and a second PLL clock output; a second divider having a second divider input and a second divider output, the second divider input is connected to the second PLL clock output; and a bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input is connected to the first divider output, the second clock input is connected to the first reference clock input, and the bypass logic output is connected to the first clock domain input. The infotainment chip also includes a reset management logic, the logic having: a controller including a controller input; and a delay logic coupled to the controller, the delay logic including a reset input, a first delay logic output, and a second delay logic output, the reset input being configured to receive a reset signal, the first delay logic output being coupled to a bypass control input, and the second delay logic output being coupled to the controller input. The reset management logic is configured to: provide a bypass control signal at the first reset output in response to the reset signal; and provide a reset control signal delayed relative to the bypass control signal at the second reset output in response to the reset signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a detailed description of various examples, reference will now be made to the accompanying drawings, in which:

[0007] Figure 1 is a diagram illustrating a system according to an example embodiment;

[0008] Figure 2 is a flow chart illustrating a partial reset method according to an example embodiment;

[0009] Figure 3 is a diagram illustrating a reset management system according to an example embodiment;

[0010] Figure 4 is a timing diagram illustrating reset management and clock management signals according to an example embodiment;

[0011] Figure 5 is a diagram illustrating a clock management system according to an example embodiment; and

[0012] Figure 6is a table illustrating phase locked loop (PLL) bypass options for an integrated circuit (IC) according to an example embodiment. DETAILED DESCRIPTION

[0013] Described herein is an integrated circuit (IC) having a phase-locked loop (PLL) and frequency divider bypass mechanism incorporating a delay of a partial reset (sometimes referred to as a warm reset). By bypassing the PLL and frequency divider before performing a partial reset, the current level of the IC during the partial reset is reduced compared to previous partial reset techniques. Using the described bypass mechanism, the clock frequency provided to at least some of the IC clock domains is reduced from a functional clock frequency (e.g., in the gigahertz range) to a lower clock frequency (e.g., in the megahertz range). As used herein, "clock domain" refers to one or more components that use a specific functional clock frequency provided by a PLL and possibly other components (e.g., frequency divider). In some example embodiments, the IC includes a first group of clock domains affected by the bypass mechanism and a second group of clock domains not affected by the bypass mechanism. In some example embodiments, staggered bypass control signals are used to bypass the PLL and frequency divider associated with the first group of clock domains in a staggered (multi-stage) manner before initiating a partial reset. During the partial reset, a bypass control shadow value is set in a memory. Once the partial reset is completed, the bypass control shadow value in the memory is cleared and the IC resumes normal function.

[0014] In an example embodiment, an IC includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input being coupled to the PLL clock output; and a bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input being coupled to the divider output, the second clock input being coupled to the reference clock input, and the bypass logic output being coupled to the clock domain input. The IC also includes reset management logic having: a controller including a controller input; and delay logic coupled to the controller. The delay logic includes a reset input, a first delay logic output, and a second delay logic output, the reset input being configured to receive a reset signal, the first delay logic output being coupled to the bypass control input, and the second delay logic output being coupled to the controller input. The reset management logic is configured to: provide a bypass control signal at a first reset output in response to the reset signal; and provide a reset control signal delayed relative to the bypass control signal at a second reset output in response to the reset signal. The described IC uses a PLL combined with a partial reset delay and a divider bypass mechanism to reduce the IC's current level during a partial reset. To provide a better understanding, various IC options and associated clock management options, reset management options, and system usage are described as shown in the following figure.

[0015] Figure 1 is a diagram illustrating a system 100 according to an example embodiment. In some example embodiments, the system 100 is a vehicle having a graphical user interface (GUI) or display. As shown, the system 100 includes an infotainment chip 102 coupled to a peripheral device 154. In addition, a power supply 160 having a first power output 162 and a second power output 166 is represented in the system 100, wherein the first power output 162 is coupled to a power input 157 of the peripheral device 154 and provides a power supply voltage 164. At the same time, the second power output 166 is coupled to a power input 170 of the infotainment chip 102 and provides a power supply voltage 168 to provide a power supply voltage 168. In an example where the system 100 is a vehicle, the power supply 160 includes a battery, one or more voltage regulators, and / or a current loop.

[0016] like Figure 1 As shown, the infotainment chip 102 includes a clock management logic 104 coupled to a first group of clock domains 134 and a second group of clock domains 136. More specifically, the clock management logic 104 includes a first group of PLLs 106, a first group of frequency dividers 112, a bypass logic 118, a second group of PLLs 126, and a second group of frequency dividers 130. In operation, the clock management logic 104 controls the clock frequency for each of the first clock domains 134 and the second clock domains 136. Without limitation to other embodiments, in some embodiments, the first group of PLLs 106 includes a microprocessor (MCU) PLL, an audio subsystem PLL, a video subsystem PLL, an accelerator subsystem PLL, and / or other subsystem PLLs. In addition, the second group of PLLs includes one or more peripheral subsystem PLLs, an Ethernet subsystem PLL, and a display subsystem PLL configured to provide limited display functions (e.g., information display, but no video).

[0017] In some example embodiments, each PLL in the first group of PLLs 106 includes a corresponding reference clock input 109 and a corresponding PLL clock output 111, wherein each reference clock input 109 receives the reference clock signal 108, and wherein each PLL clock output 111 provides a corresponding PLL clock signal 110. Furthermore, each frequency divider in the first group of frequency dividers 112 includes a corresponding frequency divider input 113 and a corresponding frequency divider output 115, wherein each frequency divider input 113 in the first group of frequency dividers 112 is coupled to a corresponding PLL clock output 111 in the first group of PLLs 106 and is configured to receive a corresponding PLL clock signal 110. Furthermore, each PLL in the second group of PLLs 126 includes a corresponding reference clock input 127 and a corresponding PLL clock output 129, wherein each reference clock input 127 receives the reference clock signal 108, and wherein each PLL clock output 129 provides a corresponding PLL clock signal 128. In addition, each of the frequency dividers in the second group of frequency dividers 126 includes a corresponding frequency divider input 131 and a corresponding frequency divider output 133, each frequency divider input 131 is connected to a corresponding PLL clock output 129 in the second group of PLLs 126 and is configured to receive the corresponding PLL clock output 129. In addition, each frequency divider output 133 is connected to a corresponding clock domain input 137 in the second group of clock domains 136 and is configured to provide a corresponding divided PLL clock signal 132 to each clock domain input 137. Figure 1 In an example, the operation of the bypass logic 118 does not affect the second group of clock domains 136. Example clock domains of the second group of clock domains 136 include peripherals 154, a display subsystem, and an Ethernet subsystem.

[0018] In some example embodiments, the second group of clock domains 136 includes a clock output 139 coupled to a clock input 155 of a peripheral device 154, wherein the clock output 139 is configured to forward one or more clock signals 156 to the clock input 155 of the peripheral device 154. In other words, the peripheral device 154 is an external component that is included with the second group of clock domains 136 or receives the same clock signal as one or more clock domains of the second group of clock domains 136.

[0019] exist Figure 1In the example, the clock management logic 104 also includes a bypass logic 118 having a corresponding first clock input 119, a corresponding second clock input 123, a corresponding bypass control input 125, and a corresponding bypass logic output 121 for each PLL and a divider combination associated with the first group of PLLs 106 and the first group of frequency dividers 112. Each corresponding first clock input 119 is coupled to a corresponding frequency divider output 115 and is configured to receive a corresponding divided PLL clock signal 116. In addition, each corresponding second clock input 123 is coupled to a reference clock input 109, and each bypass logic output 121 is coupled to a corresponding clock domain input 135 of the first group of clock domains 134. In addition, each corresponding bypass control input 125 is configured to receive a bypass control signal 120. In operation, the bypass logic 118 enables the first group of PLLs 106 and the first group of frequency dividers 112 to be bypassed. When bypassed, the first group of clock domains 134 receive the reference clock signal 108 at each corresponding clock domain input 135. When not bypassed, the first set of clock domains 134 receives a corresponding divided PLL clock signal 116 at each corresponding clock domain input 135. Without limitation to other example embodiments, in some examples, the first set of clock domains 134 includes a microprocessor (MCU), an audio subsystem, a video subsystem, an accelerator subsystem, and / or other subsystems.

[0020] exist Figure 1, the infotainment chip 102 also includes a reset management logic 140 having: a controller 141 including a controller input 152; and a delay logic 142 coupled to the controller 141. More specifically, the delay logic 142 includes a reset input 143, a first delay logic output 145, a second delay logic output 147, and a third delay logic output 149. The reset input 143 is configured to receive one or more reset signals or requests 114 provided to the reset management logic 140. The first delay logic output 145 is coupled to at least some of the corresponding bypass control inputs 125 of the bypass logic 118, and the second delay logic output 147 is coupled to the controller input 152. In operation, the reset management logic is configured to: provide a bypass control signal 146 at the first reset output 145 in response to the reset signal 114; and provide a reset control signal 148 delayed relative to the bypass control signal 146 at the second reset output 147 in response to the reset signal 114. In some example embodiments, the third delay logic output 149 is coupled to some of the corresponding bypass control inputs 125 in the bypass logic 118, and the first delay logic output 145 and the third delay logic output 149 are coupled to different subsets of the corresponding bypass control inputs 125. In operation, the reset management logic 140 is configured to: provide a first bypass control signal 146 to the first delay logic output 145; and provide a second bypass control signal 150 to the third delay logic output 149, wherein the second bypass control signal 150 is delayed or staggered relative to the first bypass control signal 146.

[0021] After the bypass process is completed (after the first group of PLLs 106 and the first group of frequency dividers 112 are bypassed), the reset control signal 148 causes the controller 141 to initiate a warm reset. During the warm reset, various warm reset operations are performed according to a conventional warm reset procedure. In some example embodiments, the controller 141 includes a memory 144, wherein the controller 141 is configured to: store the bypass value in the memory 144 in response to the initiation of the warm reset; and clear the bypass value in the memory after the warm reset is completed. Figure 1In the embodiment, the controller 141 includes a processor, a computer readable memory (e.g., memory 144) having instructions and values, and / or other components that perform a warm reset operation. Using the described clock management logic 104 and reset management logic 140, the infotainment chip 102 can respond to a partial reset request by: delaying the partial reset request, performing a bypass operation for some clock domains of the infotainment chip 102 (using one or more bypass control signals, such as staggered bypass control signals); initiating a partial reset after the bypass operation is completed; performing a partial reset operation; tracking when a partial reset condition exists or does not exist; and ending the partial reset if the partial reset condition does not exist. Using the described clock management logic 104 and reset management logic 140, the current level of the infotainment chip 102 during a partial reset is reduced compared to previous ICs.

[0022] Figure 2 2 is a flow chart showing a partial reset method 200 according to an example embodiment. As shown, the partial reset method 200 includes detecting a partial reset request or signal (WRST, Figure 1 ). At block 204, the propagation of WRST is delayed and two staggered bypass control signals (eg, Figure 1 At block 206, bypass control signals 146 and 150 are used to bypass (e.g., from Figure 1 106 and the first group of PLLs 106 and the first group of dividers 112) PLL and high speed divider (HSDIV) clock. At block 208, WRST is propagated to the reset controller (e.g., Figure 1 141 in the controller 141), causing a partial reset. At box 210, a new bypass control shadow value (bypass-ctrl-shadow-MMR) is set in memory. At box 212, a change in WRST is detected (e.g., WRST ends at its source or related conditions). At box 214, the PLL and HSDIV clocks continue to be bypassed. At box 216, the IC is released from the partial reset associated with the WRST detected in box 202. At box 218, the bypass control shadow value is cleared from memory. As needed, the partial reset method 200 is repeated where the IC has different WRST sources. Example WRST sources for an IC (e.g., infotainment chip 102) include master reset logic, device management logic, voltage thermal manager, and debug logic.

[0023] Figure 3 is a diagram illustrating a reset management system 300 according to an example embodiment. Figure 3 , the reset management system 300 includes a reset management logic 301 (eg, Figure 1308) are reset sources (part of the reset management logic 140 in ): master reset logic 302, device manager 304, thermal manager 306, and debug 308. More specifically, reset source 302 is a master reset logic configured to receive reset requests (e.g., mcu_porz, RESET_REQz, SW_MAIN_WARMRESETz, mcu_resetz_final, CLK_12RC, MAIN_PLLCRTL_1_RST_n). As shown, SW_MAIN_WARMRESETz is an inverted signal based on another signal (SW_MAIN_WARMRESET) through inverter 303. In response to one or more reset requests, the master reset logic 302 outputs a reset signal (main_resetz). Reset source 304 is a device manager configured to assert a partial reset signal (warm_reset) in response to a related request or condition. Reset source 306 is a thermal manager 306 configured to assert a reset signal (maxtemp_alert) in response to an overtemperature condition. Reset source 308 is debug logic configured to assert a reset signal (reset_n) in response to a debug option of the IC.

[0024] As shown, the reset management logic 301 includes delay blocks 312, 314, 316, 318 coupled to respective reset sources: the master reset logic 302, the device manager 304, the thermal manager 306, and the debug 308 and configured to receive reset signals (e.g., main_resetz, warm_reset, maxtemp_alert, and reset_n). The outputs of the delay blocks 312, 314, 316, and 318 are provided to a reset controller (e.g., Figure 1 During this delay, reset signals (e.g., main_resetz, warm_reset, maxtemp_alert, and reset_n) are input to a controller 141 configured to provide a bypass control signal ("force_main_pll_bypass", Figure 1 In some example embodiments, the reset management logic 301 further includes a delay block 322 after the gate 320, wherein the delay block 322 is configured to provide a bypass control signal (“force_main_pll_bypass_dly”, Figure 1100 ). In some example embodiments, force_main_pll_bypass is used to bypass some PLLs and dividers associated with the first group of PLLs 106 and the first group of frequency dividers 112. In one example, force_main_pll_bypass is used to bypass all PLLs and dividers associated with the first group of PLLs 106 and the first group of frequency dividers 112, except for the main PLL (MAIN_PLL0) and the partial reset isolated PLL. After a delay, force_main_pll_bypass_dly is used to bypass the main PLL and the associated dividers, wherein the bypass operations of force_main_pll_bypass and force_main_pll_bypass_dly are interleaved and occur before the partial reset of the reset controller is triggered by the delayed reset signal.

[0025] Figure 4 4 is a timing diagram 400 illustrating reset management and clock management signals according to an example embodiment. Figure 4 In the example of FIG. 1 , signals are shown for a reference clock signal (CLK_12M_RC), main_resertz, force_main_pll_bypass, force_main_pll_bypass_dly, main_resertz_dly, chip_rst (e.g., from a reset controller such as Figure 1 Controller 141 in mod_g_rst_n), main_pll_bypass_warmrst[n] (MMR bit reset on mod_g_rst_n), main_pll_extbypass(n) (MMR bit reset on mod_por_rst_n), MAIN_PLL(n)_HSDIV, and MAIN PLL0_HSDIVs. Figure 4As shown, CLK_12M_RC maintains a given clock frequency over time, while MAIN PLL0_HSDIVs to MAIN PLL(n)_HSDIVs vary over time according to the bypass operation described herein. More specifically, main_resetz is deasserted at time t1. Once main_resetz is deasserted, force_main_pll_bypass is asserted to enable bypass operation for the selected PLL (e.g., processor, accelerator, non-reset isolator PLL) starting at time t2, wherein the bypass operation bypasses the PLL and possibly associated dividers to reduce MAIN_PLL[n]_HSDIVs from the functional clock frequency to a lower clock frequency. At time t3, force_main_pll_bypass_dly is asserted and bypass operation is initiated for the other selected PLLs (e.g., main PLL and associated dividers) to reduce MAIN_PLL0_HSDIVs from the functional clock frequency to a lower clock frequency, as described herein. At time t4, main_resetz_dly is deasserted, main_pll_bypass_warmrst[n] is asserted, and a partial reset (e.g., warm reset) is initiated. In addition, chip_rst is deasserted at time t4. At time t5, main_resetz is asserted and force_main_pll_bypass is deasserted. At time t6, force_main_pll_bypass_dly is deasserted. At time t7, main_resetz_dly and chip_rst are asserted. At time t8, software disables bypass operation, causing MAIN_PLL[n]_HSDIVs and MAIN_PLL0_HSDIVs to return to their functional clock frequencies at t9.

[0026] Figure 5 1 is a diagram illustrating a clock management system 500 according to an example embodiment. As shown in the figure, the clock management system 500 includes a clock management logic 104A ( Figure 1 104 ) and a PLL memory mapped register (MMR) controller 502 and a PLL spread spectrum modulator (SSMOD) 504 (labeled “PLL[m]_SSMOD”). Figure 5, the PLL MMR controller 502 provides a first control signal 505 to a control input ("PLL_CONTROLS") of the PLL 106A (labeled "PLL[m]") to enable or disable the PLL 106A. In addition, the PLL SSMOD 504 provides a second control signal 507 to a control input ("FBDIV[11:0]") of the PLL 106A to adjust the feedback divider value based on the SSMOD operation.

[0027] exist Figure 5 In the example of FIG. 1 , the clock management logic 104A includes a PLL 106A and a plurality of divider blocks 510A-510N, wherein each of the divider blocks 510A-510N includes a corresponding divider 112A-112N and a corresponding bypass circuit system 512A-512N (the combined bypass circuit system 512A-512N is Figure 1 100 ). As shown, each of the bypass circuit systems 512A-512N includes a corresponding multiplexer 518A-518N, a corresponding OR gate 516A-516N, and a corresponding AND gate 514A-514N. In addition, each of the bypass circuit systems 512A-512N is connected to an OR gate 508, which provides an external bypass control signal (EXTBYPASS). As shown, the inputs to the OR gate 508 include main_pll_bypass_warmrst[m], force_main_pll_bypass, and PLL[m]_EXTBYPASS. Figure 5 In the example of , each of the OR gates 516A-516N is configured to receive EXTBYPASS as an input. Another input to each of the OR gates 516A-516N comes from the output of each corresponding AND gate 514A-514N. As shown, the inputs to the corresponding AND gates 514A-514N include a lock loss control signal (BYPASS_ON_LOCKLOSS, where the value at PORz = 1) and a lock signal (LOCK) based on the PLL output. The output of each of the OR gates 516A-516N is a bypass control signal for each corresponding multiplexer 518A-518N. When the bypass control signal from the OR gates 516A-516N is low, the output from the divider 112A-112N is output from the multiplexer 518A-518N. In some examples, a respective integrated clock gating (ICG) block 520A-520N is used at the output of each of the multiplexers 518A-518N. When bypassing is not performed, the output of each divider block 510A-510N is based on the PLL 106A and the respective divider 112A-112N (e.g., various options are possible and are provided in Figure 510N). When the bypass operation is performed (based on EXTBYPASS or based on the output of AND gates 514A-514N), the reference clock signal (FREF) 108 input to PLL 106A is output from divider blocks 510A-510N. In other words, the bypass operation causes PLL 106A and dividers 112A-112B to be bypassed, so that a lower clock frequency (reference clock signal 108) is output from divider blocks 510A-510N.

[0028] exist Figure 5 In the example of FIG. 5 , PLL 106A is used with multiple divider blocks 510A-510N. In addition to the PLL clock signal output to the divider blocks 510A-510N, PLL 106A also outputs an SSMOD control signal (from an output labeled “CLKSSCG”) and a lock control signal (PLL_LOCK) from an output labeled “LOCK”. Additionally, in some example embodiments, all components in system 500 are replicated for a given IC. In one example, an IC includes up to 20 PLLs, each of which has one or more associated divider blocks. Additionally, an IC may include PLLs and dividers without bypass circuitry (e.g., Figure 1 The second group of PLLs 126 and the second group of frequency converters 130 in FIG.

[0029] Using the described clock management system 500 and reset management logic (e.g., Figure 1 The reset management logic 140 in Figure 3 ), an IC or an infotainment chip (e.g., Figure 1 The infotainment chip 102 in the embodiment of the present invention can respond to a partial reset request by delaying the partial reset request, performing a bypass operation for some clock domains of the IC or infotainment chip (using one or more bypass control signals, such as staggered bypass control signals); initiating a partial reset after the bypass operation is completed; performing a partial reset operation; tracking when a partial reset condition exists or does not exist; and ending the partial reset if the partial reset condition does not exist. Using the described clock management system 500 and reset management logic, the current level of the IC or infotainment chip during a partial reset is reduced compared to previous ICs.

[0030] like Figure 6602 and 604 are tables showing bypass options for IC according to example embodiments. As shown, table 602 includes MCU PLLs (MCU_PLL0 to MCU_PLL2) bypassed by bypass operation as described herein. In addition, table 604 includes various main PLLs (MAIN_PLL0 to MAIN_PLL25), many of which are bypassed by bypass operation (e.g., MAIN_PLL0, MAIN_PLL4 to MAIN_PLL15, MAIN_PLL24 and MAIN_PLL25). In one example, the type of bypassed main PLL includes audio subsystem PLL, video subsystem PLL, processor PLL and accelerator PLL. In addition, in table 604, some main PLLs are not bypassed by bypass operation. For example, MAIN_PLL 1 and MAIN_PLL2 support peripheral devices and are not bypassed by bypass operation. In addition, MAIN_PLL3 supports Ethernet subsystem and is not bypassed by bypass operation. Additionally, MAIN_PLL 16 through MAIN_PLL 20 support one or more display subsystems that are not bypassed by the bypass operation. Table 604 includes various reserved PLLs (e.g., MAIN_PLL 9 through MAIN_PLL 11 and MAIN_PLL 20 through MAIN_PLL 22), where MAIN_PLL 9 through MAIN_PLL 11 are bypassed and where MAIN_PLL 20 through MAIN_PLL 22 are not bypassed. Figure 6 The example is for illustration only and is not intended to limit the bypass operation to a specific set of PLLs. Figure 6 In the example given in FIG. 1 , the PLL supporting peripherals and external communications is not bypassed (to ensure continued communication with external components). In addition, the PLL supporting the display subsystem is not bypassed (to ensure some display functions).

[0031] Certain terms are used throughout the specification and claims to refer to specific system components. As will be appreciated by those skilled in the art, different parties may refer to a component by different names.

[0032] In this specification, the term "coupled" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, if the intermediate component C does not change the functional relationship between device A and device B, device A is coupled to device B via the intermediate component C, so that device B is controlled by device A via the control signal generated by device A.

[0033] Modifications can be made in the described embodiments, and other embodiments are possible, within the scope of the claims. For example, the described embodiments refer to partial reset scenarios, where only some IC components are reset. In other example embodiments, the described clock bypass and reset delay are used for full chip reset scenarios where the chip can bypass and perform a full reset when a reset request is detected.

Claims

1. An integrated circuit, comprising: a clock domain with clock domain inputs; A clock management logic coupled to the clock domain, the clock management logic comprising: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and a bypass logic having a first clock input coupled to the divider output, a second clock input coupled to the reference clock input, a bypass control input, and a bypass logic output coupled to the clock domain input; and A reset management logic, the reset management logic having: a controller including a controller input; and a delay logic coupled to the controller, the delay logic comprising a reset input, a first delay logic output, and a second delay logic output, the reset input being configured to receive a reset signal, the first delay logic output being coupled to the bypass control input, the second delay logic output being coupled to the controller input, and the reset management logic being configured to: providing a bypass control signal at a first reset output in response to the reset signal; and A reset control signal delayed relative to the bypass control signal is provided at a second reset output in response to the reset signal.

2. The integrated circuit of claim 1 , further comprising: a first group of clock domains including the clock domains, each clock domain in the first group of clock domains having a corresponding clock domain input; as well as a second group of clock domains, each clock domain in the second group of clock domains having a corresponding clock domain input, the clock management logic being coupled to each corresponding clock domain input of the first group of clock domains and the second group of clock domains, and the clock management logic comprising: a first group of PLLs including the PLL, each PLL in the first group of PLLs having a corresponding reference clock input and a corresponding PLL clock output; a first set of frequency dividers, each frequency divider in the first set of frequency dividers having a corresponding frequency divider input and a corresponding frequency divider output, each frequency divider input in the first set of frequency dividers being coupled to a corresponding PLL clock output in the first set of PLLs; a second set of PLLs, each PLL in the second set of PLLs having a respective reference clock input and a respective PLL clock output; and a second set of frequency dividers, each frequency divider in the second set of frequency dividers having a respective frequency divider input and a respective frequency divider output, each frequency divider input in the second set of frequency dividers being coupled to a respective PLL clock output of the second set of PLLs, The bypass logic has a corresponding first clock input, a corresponding second clock input, a corresponding bypass control input and a corresponding bypass logic output for each divider in the first group of dividers, each first clock input is connected to a corresponding divider output, each second clock input is connected to a corresponding reference clock input, each bypass logic output is connected to a corresponding clock domain input, and a reset output of the reset management logic is connected to each corresponding bypass control input.

3. The integrated circuit according to claim 2, wherein: The delay logic further comprises a third delay logic output coupled to some of the corresponding bypass control inputs, the first delay logic output is coupled to other of the corresponding bypass control inputs, the bypass control signal is a first bypass control signal, and the reset management logic is configured as: providing the first bypass control signal to the first delay logic output; and A second bypass control signal is provided to the third delay logic output, the second bypass control signal being delayed relative to the first bypass control signal.

4. The integrated circuit according to claim 2, wherein: The first group of PLLs includes a microprocessor PLL, ie, an MCU PLL, and an audio subsystem PLL, and the second group of PLLs includes a peripheral subsystem PLL and a display subsystem PLL configured to display information without video.

5. The integrated circuit according to claim 2, wherein: The first set of PLLs includes video subsystem PLLs, and the second set of PLLs includes Ethernet subsystem PLLs.

6. The integrated circuit of claim 1, wherein: The bypass logic includes: a multiplexer having the first clock input, the second clock input, the bypass control input, and the bypass logic output; and An OR gate having a first gate input coupled to the reset output, a second gate input configured to receive the bypass control signal, and a gate output coupled to the bypass control input.

7. The integrated circuit according to claim 2, wherein: The reset control signal causes the controller to initiate a warm reset after the first set of PLLs and the first set of frequency converters are bypassed.

8. The integrated circuit according to claim 7, wherein: The controller includes a memory, and the controller is configured to: storing a bypass value in the memory in response to initiation of the warm reset; and The bypass value in the memory is cleared after the warm reset is completed.

9. An infotainment circuit comprising: a first clock domain having a first clock domain input; a second clock domain having a second clock domain input; A clock management logic coupled to the first clock domain and the second clock domain, the clock management logic comprising: a first PLL having a first reference clock input and a first PLL clock output; a first divider having a first divider input and a first divider output, the first divider input coupled to the first PLL clock output; a second PLL having a second reference clock input and a second PLL clock output; a second divider having a second divider input coupled to the second PLL clock output and a second divider output coupled to the second clock domain input; and a bypass logic having a first clock input coupled to the first divider output, a second clock input coupled to the first reference clock input, a bypass control input, and a bypass logic output coupled to the first clock domain input; and A reset management logic, the reset management logic having: a controller including a controller input; and a delay logic coupled to the controller, the delay logic comprising a reset input, a first delay logic output, and a second delay logic output, the reset input being configured to receive a reset signal, the first delay logic output being coupled to the bypass control input, the second delay logic output being coupled to the controller input, and the reset management logic being configured to: providing a bypass control signal at a first reset output in response to the reset signal; and A reset control signal delayed relative to the bypass control signal is provided at a second reset output in response to the reset signal.

10. The infotainment circuit of claim 9, further comprising: a first group of clock domains including the first clock domain, each clock domain in the first group of clock domains having a corresponding clock domain input; as well as a second group of clock domains including the second clock domain, each clock domain in the second group of clock domains having a corresponding clock domain input, the clock management logic being coupled to each corresponding clock domain input in the first group of clock domains and the second group of clock domains, and the clock management logic comprising: a first group of PLLs including the first PLL, each PLL in the first group of PLLs having a corresponding reference clock input and a corresponding PLL clock output; a first set of frequency dividers including the first frequency divider, each frequency divider in the first set of frequency dividers having a respective frequency divider input and a respective frequency divider output, each frequency divider input in the first set of frequency dividers being coupled to a respective PLL clock output in the first set of PLLs; a second set of PLLs, each PLL in the second set of PLLs having a respective reference clock input and a respective PLL clock output; and a second set of frequency dividers, each frequency divider in the second set of frequency dividers having a respective frequency divider input and a respective frequency divider output, each frequency divider input in the second set of frequency dividers being coupled to a respective PLL clock output of the second set of PLLs, The bypass logic has a corresponding first clock input, a corresponding second clock input, a corresponding bypass control input and a corresponding bypass logic output for each divider in the first group of dividers, each first clock input is connected to a corresponding divider output, each second clock input is connected to a corresponding reference clock input, each bypass logic output is connected to a corresponding clock domain input, and a reset output of the reset management logic is connected to each corresponding bypass control input.

11. The infotainment circuit of claim 10, wherein: The delay logic further comprises a third delay logic output coupled to some of the corresponding bypass control inputs, the first delay logic output is coupled to other of the corresponding bypass control inputs, the bypass control signal is a first bypass control signal, and the reset management logic is configured as: providing the first bypass control signal to the first delay logic output; and A second bypass control signal is provided to the third delay logic output, the second bypass control signal being delayed relative to the first bypass control signal.

12. The infotainment circuit of claim 10, wherein: The first group of PLLs includes a microprocessor PLL, ie, an MCU PLL, a video subsystem PLL, and an audio subsystem PLL, and the second group of PLLs includes a peripheral subsystem PLL, an Ethernet subsystem PLL, and a display subsystem PLL configured to display information without video.

13. The infotainment circuit of claim 9, wherein the bypass logic comprises: a multiplexer having the first clock input, the second clock input, the bypass control input, and the bypass logic output; as well as An OR gate having a first gate input coupled to the reset output, a second gate input configured to receive the bypass control signal, and a gate output coupled to the bypass control input.

14. The infotainment circuit of claim 10, wherein: The reset control signal causes the controller to initiate a warm reset after the first set of PLLs and the first set of frequency converters are bypassed.

15. The infotainment circuit of claim 14, wherein: The controller includes a memory, and the controller is configured to: storing a bypass value in the memory in response to initiation of the warm reset; and The bypass value in the memory is cleared after the warm reset is completed.

16. A system comprising: Infotainment chips; as well as A peripheral device coupled to the infotainment chip, wherein the infotainment chip comprises: a first clock domain having a first clock domain input; a second clock domain having a second clock domain input, the second clock domain including an output pin to the peripheral device; A clock management logic coupled to the first clock domain and the second clock domain, the clock management logic comprising: a first PLL having a first reference clock input and a first PLL clock output; a first divider having a first divider input and a first divider output, the first divider input coupled to the first PLL clock output; a second PLL having a second reference clock input and a second PLL clock output; a second divider having a second divider input and a second divider output, the second divider input coupled to the second PLL clock output; and a bypass logic having a first clock input coupled to the first divider output, a second clock input coupled to the first reference clock input, a bypass control input, and a bypass logic output coupled to the first clock domain input; and A reset management logic, the reset management logic having: a controller including a controller input; and a delay logic coupled to the controller, the delay logic comprising a reset input, a first delay logic output, and a second delay logic output, the reset input being configured to receive a reset signal, the first delay logic output being coupled to the bypass control input, the second delay logic output being coupled to the controller input, and the reset management logic being configured to: providing a bypass control signal at a first reset output in response to the reset signal; and A reset control signal delayed relative to the bypass control signal is provided at a second reset output in response to the reset signal.

17. The system of claim 16, further comprising: a first group of clock domains including the first clock domain, each clock domain in the first group of clock domains having a corresponding clock input; as well as a second group of clock domains including the second clock domain, each clock domain in the second group of clock domains having a corresponding clock domain input, the clock management logic being coupled to each corresponding clock domain input in the first group of clock domains and the second group of clock domains, and the clock management logic comprising: a first group of PLLs including the first PLL, each PLL in the first group of PLLs having a corresponding reference clock input and a corresponding PLL clock output; a first set of frequency dividers including the first frequency divider, each frequency divider in the first set of frequency dividers having a respective frequency divider input and a respective frequency divider output, each frequency divider input in the first set of frequency dividers being coupled to a respective PLL clock output of the first set of PLLs; a second group of PLLs, each PLL in the second group of PLLs having a respective reference clock input and a respective PLL clock output; and a second set of frequency dividers, each frequency divider in the second set of frequency dividers having a respective frequency divider input and a respective frequency divider output, each frequency divider input of the second set of frequency dividers being coupled to a respective PLL clock output of the second set of PLLs, The bypass logic has a corresponding first clock input, a corresponding second clock input, a corresponding bypass control input and a corresponding bypass logic output for each divider in the first group of dividers, each first clock input is connected to a corresponding divider output, each second clock input is connected to a corresponding reference clock input, each bypass logic output is connected to a corresponding clock domain input, and a reset output of the reset management logic is connected to each corresponding control input.

18. The system of claim 17, wherein: The delay logic further comprises a third delay logic output coupled to some of the corresponding bypass control inputs, the first delay logic output is coupled to other of the corresponding bypass control inputs, the bypass control signal is a first bypass control signal, and the reset management logic is configured as: providing the first bypass control signal to the first delay logic output; and A second bypass control signal is provided to the third delay logic output, the second bypass control signal being delayed relative to the first bypass control signal.

19. The system of claim 16, wherein: The system is a vehicle.

20. The system of claim 17, wherein: The first group of PLLs includes an audio subsystem PLL and a video subsystem PLL, and the second group of PLLs includes a display subsystem PLL and an Ethernet subsystem PLL.

21. The system of claim 16, wherein: The bypass logic includes: a multiplexer having the first clock input, the second clock input, the bypass control input, and the bypass logic output; and An OR gate having a first gate input coupled to the reset output, a second gate input configured to receive a bypass control signal separate from the reset output, and a gate output coupled to the control input.

22. The system of claim 17, wherein: The reset control signal causes the controller to initiate a warm reset after the first set of PLLs and the first set of frequency converters are bypassed.

23. The system of claim 22, wherein: The controller includes a memory, and the controller is configured to: storing a bypass value in the memory in response to initiation of the warm reset; and The bypass value in the memory is cleared after the warm reset is completed.

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