A detection circuit, a display panel and a display device

Abstract

The embodiment of the present application provides a detection circuit, a display panel and a display device; in the detection circuit, a detection signal line is used to transmit a detection signal; the input end of the first switch unit is electrically connected to the input end of the second switch unit and is used to receive the detection signal, the output end of the first switch unit is electrically connected to the output end of the second switch unit and is used to transmit the detection signal to the detection port; the first switch unit includes a first control end, the first control end is electrically connected to the first signal line; the second switch unit includes a second control end, the second control end is electrically connected to the second signal line; the time period during which the signal transmitted by the first signal line controls the first switch unit to be turned on is different from the time period during which the signal transmitted by the second signal line controls the second switch unit to be turned on. The present application can monitor the accuracy of the signals on the first signal line and the second signal line, so as to determine whether an error occurs in a circuit that uses the signal on the first signal line and / or the signal on the second signal line as a driving signal.

Description

[Technical field]

[0001] The present application relates to the field of display technology, and in particular to a detection circuit, a display panel and a display device. [Background technology]

[0002] With the rapid development and application of information technology, people are becoming more and more dependent on electronic devices, which has also brought about the vigorous development of various display technologies and display devices.

[0003] The display device includes a variety of circuits, which are usually driven by driving signals. The accuracy of the driving signals is the premise for ensuring the correct operation of these circuits. Therefore, there is an urgent need for a solution that can detect the accuracy of the driving signals so that the display device can handle the errors in time and avoid the display device displaying erroneous information.

[0004]

Application Contents

[0005] In view of this, embodiments of the present application provide a detection circuit, a display panel, and a display device to solve the above problems.

[0006] In a first aspect, an embodiment of the present application provides a detection circuit, which includes a detection signal line, a detection port and a switch module; the detection signal line is used to transmit a detection signal; the switch module includes a first switch unit and a second switch unit, the input end of the first switch unit is electrically connected to the input end of the second switch unit, and is used to receive the detection signal transmitted on the detection signal line, the output end of the first switch unit is electrically connected to the output end of the second switch unit, and is used to transmit the detection signal to the detection port; wherein the first switch unit includes a first control end, the first control end is electrically connected to the first signal line; the second switch unit includes a second control end, the second control end is electrically connected to the second signal line; the time period during which the signal transmitted by the first signal line controls the first switch unit to be turned on is different from the time period during which the signal transmitted by the second signal line controls the second switch unit to be turned on.

[0007] In an implementation of the first aspect, the first switch unit includes a first transistor, a first electrode of the first transistor is electrically connected to the input end of the first switch unit, a second electrode is electrically connected to the output end of the first switch unit, and a gate is electrically connected to the first control end; the second switch unit includes a second transistor, a first electrode of the second transistor is electrically connected to the input end of the second switch unit, a second electrode is electrically connected to the output end of the second switch unit, and a gate is electrically connected to the second control end; the channel type of the first transistor and the second transistor is the same.

[0008] In an implementation manner of the first aspect, a phase difference between a signal transmitted by the first signal line and a signal transmitted by the second signal line is 180°.

[0009] In an implementation of the first aspect, the first switch unit also includes a third control terminal, the third control terminal is electrically connected to the third signal line, and the time period during which the third signal line transmits an enable signal is at least partially the same as the time period during which the first signal line transmits an enable signal; the second switch unit also includes a fourth control terminal, the fourth control terminal is electrically connected to the fourth signal line, and the time period during which the fourth signal line transmits an enable signal is at least partially the same as the time period during which the second signal line transmits an enable signal.

[0010] In an implementation of the first aspect, the first switch unit includes a first transistor and a third transistor, the first electrode of the first transistor is electrically connected to the input end of the first switch unit, the second electrode is electrically connected to the first electrode of the third transistor, and the gate is electrically connected to the first control end; the second electrode of the third transistor is electrically connected to the output end of the first switch unit, and the gate is electrically connected to the third control end; the second switch unit includes a second transistor and a fourth transistor, the first electrode of the second transistor is electrically connected to the input end of the second switch unit, the second electrode is electrically connected to the second electrode of the first transistor and the first electrode of the fourth transistor, and the gate is electrically connected to the second control end; the second electrode of the fourth transistor is electrically connected to the output end of the second switch unit, and the gate is electrically connected to the fourth control end.

[0011] In an implementation manner of the first aspect, a phase difference between a signal transmitted by the first signal line and a signal transmitted by the second signal line is 180°, and a phase difference between a signal transmitted by the third signal line and a signal transmitted by the fourth signal line is 180°.

[0012] In an implementation of the first aspect, the first switch unit includes a first transistor and a third transistor, the first electrode of the first transistor is electrically connected to the input end of the first switch unit, the second electrode is electrically connected to the first electrode of the third transistor, and the gate is electrically connected to the first control end; the second electrode of the third transistor is electrically connected to the output end of the first switch unit, and the gate is electrically connected to the third control end; the second switch unit includes a second transistor and a fourth transistor, the first electrode of the second transistor is electrically connected to the input end of the second switch unit, the second electrode is electrically connected to the first electrode of the fourth transistor, and the gate is electrically connected to the second control end; the second electrode of the fourth transistor is electrically connected to the output end of the second switch unit, and the gate is electrically connected to the fourth control end.

[0013] In an implementation manner of the first aspect, a phase difference between a signal transmitted by the first signal line and a signal transmitted by the fourth signal line is 180°, and a phase difference between a signal transmitted by the second signal line and a signal transmitted by the third signal line is 180°.

[0014] In an implementation manner of the first aspect, the channel types of the first transistor, the second transistor, the third transistor, and the fourth transistor are all the same.

[0015] In an implementation of the first aspect, the switch module further includes a third switch unit, which is connected in parallel with the first switch unit and the second switch unit, and a time period during which the third switch unit is turned on is different from a time period during which the first switch unit and the second switch unit are turned on.

[0016] In an implementation of the first aspect, the third switch unit includes a fifth transistor and a sixth transistor, the first electrode of the fifth transistor is electrically connected to the input end of the third switch unit, the second electrode is electrically connected to the first electrode of the sixth transistor, and the gate is electrically connected to the fifth signal line; the second electrode of the sixth transistor is electrically connected to the output end of the third switch unit, and the gate is electrically connected to the sixth signal line; the time period in which the fifth signal line transmits the enable signal is at least partially the same as the time period in which the sixth signal line transmits the enable signal.

[0017] In an implementation manner of the first aspect, the fifth transistor and the sixth transistor have the same channel type as the first transistor.

[0018] In an implementation of the first aspect, the phase difference between the signal transmitted by the first signal line and the signal transmitted by the sixth signal line is 180°, the phase difference between the signal transmitted by the second signal line and the signal transmitted by the third signal line is 180°, and the phase difference between the signal transmitted by the fourth signal line and the signal transmitted by the fifth signal line is 180°.

[0019] In a second aspect, an embodiment of the present application provides a display panel, which includes a detection circuit and a gate driving circuit as provided in the first aspect; the gate driving circuit is electrically connected to the first signal line and the second signal line.

[0020] In an implementation manner of the second aspect, the first signal line transmits a first clock signal, the second signal line transmits a second clock signal, and a phase difference between the first clock signal and the second clock signal is 180°.

[0021] In a third aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the second aspect.

[0022] In the present application, the detection circuit can perform real-time detection on the signals transmitted on the first signal line and the second signal line, and determine whether the signal transmitted on the first signal line or the second signal line is erroneous through the detection signal received by the detection port, thereby determining whether the circuit in the display device that uses the signal on the first signal line and / or the signal on the second signal line as a driving signal can work normally, which is beneficial for the display device to promptly process the error information appearing in the aforementioned circuit, and avoid the display device displaying error information.

Brief Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of a detection circuit provided in an embodiment of the present application;

[0025] Figure 2 for Figure 1 A schematic diagram of the detection circuit shown;

[0026] Figure 3 for Figure 2 A timing diagram of the detection circuit shown;

[0027] Figure 4 A schematic diagram of a detection circuit provided in an embodiment of the present application;

[0028] Figure 5 for Figure 4 A timing diagram of the detection circuit shown;

[0029] Figure 6 A schematic diagram of another detection circuit provided in an embodiment of the present application;

[0030] Figure 7 for Figure 6 A timing diagram of the detection circuit shown;

[0031] Figure 8 A schematic diagram of another detection circuit provided in an embodiment of the present application;

[0032] Fig. 9 for Figure 8 A timing diagram of the detection circuit shown;

[0033] Fig.10 A schematic diagram of a display panel provided in an embodiment of the present application;

[0034] Fig.11 A schematic diagram of a display device provided in an embodiment of the present application. [Specific implementation method]

[0035] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0036] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0037] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0038] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0039] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0040] It should be understood that, although the terms first, second, etc. may be used to describe switch units, transistors, signal lines, etc. in the embodiments of the present application, these switch units, transistors, signal lines, etc. should not be limited to these terms. These terms are only used to distinguish switch units, transistors, signal lines, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first switch unit may also be referred to as the second switch unit, and similarly, the second switch unit may also be referred to as the first switch unit.

[0041] The applicant in this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0042] Figure 1 A schematic diagram of a detection circuit provided in an embodiment of the present application, Figure 2 for Figure 1 A schematic diagram of the detection circuit shown in FIG. Figure 3 for Figure 2 A timing diagram of the detection circuit shown.

[0043] The present application embodiment provides a detection circuit 001, combined with Figure 1-Figure 3As shown, the detection circuit 001 includes a detection signal line TL, a detection port Po and a switch module 10. The detection signal line TL is used to transmit a detection signal V1, which can be a high level signal; the detection port Po receives the detection signal V1 through the switch module 10.

[0044] The switch module 10 includes a first switch unit 11 and a second switch unit 12. The input end 11A of the first switch unit 11 is electrically connected to the input end 12A of the second switch unit 12, and is used to receive the detection signal V1 transmitted on the detection signal line TL. The output end 11B of the first switch unit 11 is electrically connected to the output end 12B of the second switch unit 12, and is used to transmit the detection signal V1 to the detection port Po.

[0045] Specifically, Figure 1 and Figure 2 As shown, the input end 11A of the first switch unit 11 and the input end 12A of the second switch unit 12 are both electrically connected to the detection signal line TL; the output end 11B of the first switch unit 11 and the output end 12B of the second switch unit 12 are both electrically connected to the detection port Po. The detection signal V1 transmitted on the detection signal line TL can be transmitted to the detection port Po through the first switch unit 11 or the second switch unit 12.

[0046] Among them, the first switch unit 11 includes a first control terminal 11C, which is electrically connected to the first signal line SL1; the second switch unit 12 includes a second control terminal 12C, which is electrically connected to the second signal line SL2; the time period during which the signal transmitted by the first signal line SL1 controls the first switch unit 11 to be turned on is different from the time period during which the signal transmitted by the second signal line SL2 controls the second switch unit 12 to be turned on.

[0047] That is, the detection port Po receives the detection signal V1 on the detection signal line TL through the first switch unit 11 and the second switch unit 12 in a time-sharing manner.

[0048] Specifically, combined Figure 2 and Figure 3 The working process of the detection circuit 001 includes a first stage T1 and a second stage T2; in the first stage T1, the first signal line SL1 transmits a valid signal to control the first switch unit 11 to turn on, and in the second stage, the second signal line SL2 transmits a valid signal to control the second switch unit 12 to turn on. The detection port Po receives the detection signal V1 in both the first stage T1 and the second stage T2.

[0049] It can be understood that when the detection port Po does not receive the detection signal V1 in the first stage T1, it can be determined that an error occurs in the signal transmitted on the first signal line SL1, and the circuit using the signal on the first signal line SL1 as a driving signal in the display device cannot work properly; when the detection port Po does not receive the detection signal V1 in the second stage T2, it can be determined that an error occurs in the signal transmitted on the second signal line SL2, and the circuit using the signal on the second signal line SL2 as a driving signal in the display device cannot work properly. Of course, the circuit using both the signal on the first signal line SL1 and the signal on the second signal line SL2 as driving signals in the display device cannot work properly either.

[0050] It should be noted that, in the present application, errors in the signals transmitted on the first signal line SL1 and the second signal line SL2 include the situation that the first signal line SL1 and the second signal line SL2 are short-circuited or open-circuited.

[0051] In the embodiment of the present application, the detection circuit 001 can perform real-time detection on the signals transmitted on the first signal line SL1 and the second signal line SL2, and determine whether the signal transmitted on the first signal line SL1 or the second signal line SL2 is erroneous by detecting the detection signal V1 received by the detection port Po, thereby determining whether the circuit in the display device that uses the signal on the first signal line SL1 and / or the signal on the second signal line SL2 as a driving signal can work normally, which is beneficial for the display device to promptly process the error information appearing in the aforementioned circuit, and avoid the display device displaying error information.

[0052] Please continue to refer to Figure 2 In one embodiment of the present application, the first switch unit 11 includes a first transistor M1, a first electrode of the first transistor M1 is electrically connected to an input terminal 11A of the first switch unit 11, a second electrode is electrically connected to an output terminal 11B of the first switch unit 11, and a gate is electrically connected to a first control terminal 11C, that is, the first switch unit 11 may include only one transistor.

[0053] The first electrode of the first transistor M1 may be its source, and the second electrode of the first transistor M1 may be its drain. Of course, in some other embodiments, the first electrode of the first transistor M1 may also be its drain, and the second electrode of the first transistor M1 may be its source.

[0054] The second switch unit 12 includes a second transistor M2, a first electrode of the second transistor M2 is electrically connected to the input terminal 12A of the second switch unit 12, a second electrode is electrically connected to the output terminal 12B of the second switch unit 12, and a gate is electrically connected to the second control terminal 12C, that is, the second switch unit 12 can include only one transistor.

[0055] The first electrode of the second transistor M2 may be its source, and the second electrode of the second transistor M2 may be its drain. Of course, in some other embodiments, the first electrode of the second transistor M2 may also be its drain, and the second electrode of the second transistor M2 may be its source.

[0056] The first transistor M1 and the second transistor M2 have the same channel type.

[0057] Alternatively, if Figure 2 As shown, the first transistor M1 and the second transistor M2 are both N-type transistors. Of course, the first transistor M1 and the second transistor M2 can also be P-type transistors.

[0058] It should be noted that, in some other embodiments, the channel types of the first transistor M1 and the second transistor M2 may also be different.

[0059] In the embodiment of the present application, the channel types of the first transistor M1 and the second transistor M2 are set to be the same, then the enable signal transmitted by the first signal line SL1 is the same as the enable signal transmitted by the second signal line SL2. Moreover, since the first switch unit 11 and the second switch unit 12 have different opening periods, the period during which the first signal line SL1 transmits the enable signal is different from the period during which the second signal line SL2 transmits the enable signal. The first signal line SL1 and the second signal line SL2 can output the enable signal alternately.

[0060] Optionally, the phase difference between the signal transmitted by the first signal line SL1 and the signal transmitted by the second signal line SL2 is 180°, that is, the signal transmitted by the first signal line SL1 and the signal transmitted by the second signal line SL2 may be anti-phase signals.

[0061] In an application scenario of an embodiment of the present application, a gate drive circuit is generally used in a display device to transmit a scan signal, and commonly used gate drive circuits include a GIP circuit using a gate in panel (GIP) technology, a GOA circuit using a gate driver on array (GOA) technology, and an amorphous silicon gate (ASG) circuit, etc. The gate drive circuit generally receives clock signals that appear in pairs, and the pair of clock signals are generally inverted signals.

[0062] The detection circuit 001 provided in the embodiment of the present application can monitor the clock signal received by the gate driving circuit in real time, and determine whether the gate driving circuit in the display device can transmit the correct scanning signal by detecting whether the clock signal is wrong.

[0063] Combine the following Figure 2 and Figure 3 right Figure 2The working process of the detection circuit 001 shown is described.

[0064] In the first stage T1, the first signal line SL1 transmits an enable signal, i.e., a high level signal, and the first transistor M1 is turned on; the second signal line SL2 transmits a low level signal, and the second transistor M2 is turned off. The detection signal V1 on the detection signal line TL is transmitted to the detection port Po through the turned-on first transistor M1.

[0065] In the second stage T2, the first signal line SL1 transmits a low level signal, the first transistor M1 is turned off, the second signal line SL2 transmits an enable signal, i.e. a high level signal, the second transistor M2 is turned on, and the detection signal V1 on the detection signal line TL is transmitted to the detection port Po through the turned-on second transistor M2.

[0066] When the detection port Po does not receive the detection signal V1 in the first stage T1, it indicates that the first transistor M1 is not turned on in the first stage T1, thereby indicating that the first transistor M1 does not receive the high-level signal that the first signal line SL1 should transmit, and further it can be determined that an error occurs in the signal transmitted on the first signal line SL1.

[0067] When the detection port Po does not receive the detection signal V1 in the second stage T2, it indicates that the second transistor M2 is not turned on in the second stage T2, thereby indicating that the second transistor M2 does not receive the high-level signal that the second signal line SL2 should transmit, and further it can be determined that an error occurs in the signal transmitted on the second signal line SL2.

[0068] Of course, for a circuit that uses the signals on the first signal line SL1 and the second signal line SL2 as driving signals at the same time, it is only necessary to determine whether the signal transmitted by at least one of the first signal line SL1 and the second signal line SL2 is wrong, without determining whether it is the signal transmission error on the first signal line SL1 or the signal transmission error on the second signal line SL2.

[0069] For example, Figure 3 As shown, it is assumed that the first signal line SL1 and the second signal line SL2 transmit the clock signals required by the gate drive circuit respectively, and the clock signals transmitted by the first signal line SL1 and the second signal line SL2 are inverted signals. During the operation of the detection circuit 001, when the detection port Po does not receive the detection signal V1, it can be determined that the signal transmitted by at least one of the first signal line SL1 and the second signal line SL2 is wrong, thereby determining that the gate drive circuit cannot work normally.

[0070] Figure 4 A schematic diagram of a detection circuit provided in an embodiment of the present application, Figure 5 for Figure 4A timing diagram of the detection circuit shown, Figure 6 A schematic diagram of another detection circuit provided in an embodiment of the present application, Figure 7 for Figure 6 A timing diagram of the detection circuit shown.

[0071] In one embodiment of the present application, Figure 4 and Figure 6 As shown, the first switch unit 11 further includes a third control terminal 11D, which is electrically connected to the third signal line SL3, and the period during which the third signal line SL3 transmits the enable signal is at least partially the same as the period during which the first signal line SL1 transmits the enable signal.

[0072] The second switch unit 12 further includes a fourth control terminal 12D, which is electrically connected to a fourth signal line SL4 , and a period during which the fourth signal line SL4 transmits an enable signal is at least partially the same as a period during which the second signal line SL2 transmits an enable signal.

[0073] That is, the signals transmitted by the first signal line SL1 and the third signal line SL3 jointly control the switching state of the first switch unit 11 ; the signals transmitted by the second signal line SL2 and the fourth signal line SL4 jointly control the switching state of the second switch unit 12 .

[0074] In a technical solution of an embodiment of the present application, Figure 4 As shown, the first switch unit 11 includes a first transistor M1 and a third transistor M3, the first electrode of the first transistor M1 is electrically connected to the input terminal 11A of the first switch unit 11, the second electrode is electrically connected to the first electrode of the third transistor M3, and the gate is electrically connected to the first control terminal 11C; the second electrode of the third transistor M3 is electrically connected to the output terminal 11B of the first switch unit 11, and the gate is electrically connected to the third control terminal 11D.

[0075] The second switch unit 12 includes a second transistor M2 and a fourth transistor M4, wherein a first electrode of the second transistor M2 is electrically connected to an input terminal 12A of the second switch unit 12, a second electrode is electrically connected to a second electrode of the first transistor M1, a first electrode of the third transistor M3 and a first electrode of the fourth transistor M4, and a gate is electrically connected to a second control terminal 12C; a second electrode of the fourth transistor M4 is electrically connected to an output terminal 12B of the second switch unit 12, and a gate is electrically connected to a fourth control terminal 12D.

[0076] Among them, the first electrode of the first transistor M1 can be one of its source and drain, and the second electrode can be the other of its source and drain; the first electrode of the second transistor M2 can be one of its source and drain, and the second electrode can be the other of its source and drain; the first electrode of the third transistor M3 can be one of its source and drain, and the second electrode can be the other of its source and drain; the first electrode of the fourth transistor M4 can be one of its source and drain, and the second electrode can be the other of its source and drain.

[0077] Optionally, the channel types of the first transistor M1 , the second transistor M2 , the third transistor M3 and the fourth transistor M4 are all the same.

[0078] Furthermore, if Figure 5 As shown, the phase difference between the signal transmitted by the first signal line SL1 and the signal transmitted by the second signal line SL2 is 180°, and the phase difference between the signal transmitted by the third signal line SL3 and the signal transmitted by the fourth signal line SL4 is 180°.

[0079] In this technical solution, combined Figure 4 and Figure 5 As shown, when the period during which any one of the first signal line SL1 and the second signal line SL2 transmits the enable signal overlaps with the period during which any one of the third signal line SL3 and the fourth signal line SL4 transmits the enable signal, the detection port Po can receive the detection signal V1. When the detection port Po does not receive the detection signal V1 during the period during which it should receive the detection signal V1, it can be determined that an error occurs in the signal transmitted by at least one of the first signal line SL1, the second signal line SL2, the third signal line SL3 and the fourth signal line SL4, and thus it can be determined that the circuit using the signal on the first signal line SL1, the second signal line SL2, the third signal line SL3 and the fourth signal line SL4 as the driving signal cannot work normally.

[0080] It should be noted that when it is necessary to monitor the signals on more signal lines, Figure 4 On the basis of the detection circuit shown, the number of transistors can be increased in the first switch unit 11 and the second switch unit 12 to meet the requirements. The connection mode of adjacent transistors in the first switch unit 11 is the same as the connection mode of the first transistor M1 and the third transistor M3, the connection mode of adjacent transistors in the second switch unit 12 is the same as the connection mode of the second transistor M2 and the fourth transistor M4, and the connection mode between the corresponding transistors in the first switch unit 11 and the second switch unit 12 is the same as the connection mode of the first transistor M1 and the second transistor M2.

[0081] In another technical solution of the embodiment of the present application, Figure 6As shown, the first switch unit 11 includes a first transistor M1 and a third transistor M3, the first electrode of the first transistor M1 is electrically connected to the input terminal 11A of the first switch unit 11, the second electrode is electrically connected to the first electrode of the third transistor M3, and the gate is electrically connected to the first control terminal 11C; the second electrode of the third transistor M3 is electrically connected to the output terminal 11B of the first switch unit 11, and the gate is electrically connected to the third control terminal 11D.

[0082] The second switch unit 12 includes a second transistor M2 and a fourth transistor M4, wherein a first electrode of the second transistor M2 is electrically connected to an input terminal 12A of the second switch unit 12, a second electrode is electrically connected to a first electrode of the fourth transistor M4, and a gate is electrically connected to a second control terminal 12C; a second electrode of the fourth transistor M4 is electrically connected to an output terminal 12B of the second switch unit 12, and a gate is electrically connected to a fourth control terminal 12D.

[0083] Among them, the first electrode of the first transistor M1 can be one of its source and drain, and the second electrode can be the other of its source and drain; the first electrode of the second transistor M2 can be one of its source and drain, and the second electrode can be the other of its source and drain; the first electrode of the third transistor M3 can be one of its source and drain, and the second electrode can be the other of its source and drain; the first electrode of the fourth transistor M4 can be one of its source and drain, and the second electrode can be the other of its source and drain.

[0084] Optionally, the channel types of the first transistor M1 , the second transistor M2 , the third transistor M3 and the fourth transistor M4 are all the same.

[0085] Furthermore, if Figure 7 As shown, the phase difference between the signal transmitted by the first signal line SL1 and the signal transmitted by the fourth signal line SL4 is 180°, and the phase difference between the signal transmitted by the second signal line SL2 and the signal transmitted by the third signal line SL3 is 180°.

[0086] In this technical solution, combined Figure 6 and Figure 7 As shown, when the period of the first signal line SL1 transmitting the enable signal overlaps with the period of the third signal line SL3 transmitting the enable signal, or when the period of the second signal line SL2 transmitting the enable signal overlaps with the period of the fourth signal line SL4 transmitting the enable signal, the detection port Po can receive the detection signal V1. Figure 7As shown, the detection signal V1 can be a high-level signal. When the detection port Po does not receive the detection signal V1 during the period when it should receive it, it can be determined that an error occurs in the signal transmitted by at least one of the first signal line SL1, the second signal line SL2, the third signal line SL3, and the fourth signal line SL4, so that it can be determined that the circuit using the signal on the first signal line SL1, the second signal line SL2, the third signal line SL3, and the fourth signal line SL4 as the driving signal cannot work normally.

[0087] Figure 8 A schematic diagram of another detection circuit provided in an embodiment of the present application, Fig. 9 for Figure 8 A timing diagram of the detection circuit shown.

[0088] In one embodiment of the present application, Figure 8 and Fig. 9 As shown, the switch module 10 further includes a third switch unit 13, which is connected in parallel with the first switch unit 11 and the second switch unit 12, and the period during which the third switch unit 13 is turned on is different from the period during which the first switch unit 11 and the second switch unit 12 are turned on.

[0089] That is to say, the detection port Po can receive the detection signal V1 through the first switch unit 11 , the second switch unit 12 , and the third switch unit 13 in a time-division manner.

[0090] Specifically, the input end 13A of the third switch unit 13 is electrically connected to the input end 11A of the first switch unit 11 and the input end 12A of the second switch unit 12 , and the output end 13B is electrically connected to the output end 11B of the first switch unit 11 and the output end 12B of the second switch unit 12 .

[0091] The third switch unit 13 includes a fifth transistor M5 and a sixth transistor M6, wherein a first electrode of the fifth transistor M5 is electrically connected to an input terminal 13A of the third switch unit 13, a second electrode is electrically connected to a first electrode of the sixth transistor M6, and a gate is electrically connected to a fifth signal line SL5; a second electrode of the sixth transistor M6 is electrically connected to an output terminal of the third switch unit 13, and a gate is electrically connected to a sixth signal line SL6. The time period during which the fifth signal line SL5 transmits an enable signal is at least partially the same as the time period during which the sixth signal line SL6 transmits an enable signal, that is, the signals transmitted on the fifth signal line SL5 and the sixth signal line SL6 jointly control the switch state of the third switch unit 13.

[0092] Optionally, the fifth transistor M5 and the sixth transistor M6 have the same channel type as the first transistor M1. Of course, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 may all have the same channel type.

[0093] Furthermore, if Fig. 9 As shown, the phase difference between the signal transmitted by the first signal line SL1 and the signal transmitted by the sixth signal line SL6 is 180°, the phase difference between the signal transmitted by the second signal line SL2 and the signal transmitted by the third signal line SL3 is 180°, and the phase difference between the signal transmitted by the fourth signal line SL4 and the signal transmitted by the fifth signal line SL5 is 180°.

[0094] In the present application embodiment, combined Figure 8 and Fig. 9 As shown, when the period of the first signal line SL1 transmitting the enable signal overlaps with the period of the third signal line SL3 transmitting the enable signal, or when the period of the second signal line SL2 transmitting the enable signal overlaps with the period of the fourth signal line SL4 transmitting the enable signal, or when the period of the fifth signal line SL5 transmitting the enable signal overlaps with the period of the sixth signal line SL6 transmitting the enable signal, the detection port Po can receive the detection signal V1. Fig. 9 As shown, the detection signal V1 can be a high-level signal. When the detection port Po does not receive the detection signal V1 during the period when it should receive it, it can be determined that an error occurs in the signal transmitted by at least one of the first signal line SL1, the second signal line SL2, the third signal line SL3, the fourth signal line SL4, the fifth signal line SL5, and the sixth signal line SL6, so that it can be determined that the circuit using the signal on the first signal line SL1, the second signal line SL2, the third signal line SL3, the fourth signal line SL4, the fifth signal line SL5, and the sixth signal line SL6 as the driving signal cannot work normally.

[0095] It should be noted that when it is necessary to monitor the signals on more signal lines, Figure 8 On the basis of the detection circuit shown, the detection circuit 001 can increase the number of switch units connected in parallel to meet the requirements, and the time periods during which the switch units are turned on are different from each other.

[0096] Fig.10 A schematic diagram of a display panel provided in an embodiment of the present application.

[0097] An embodiment of the present application provides a display panel 100 , and the display panel 100 includes a detection circuit 001 and a gate driving circuit 002 as provided in the above embodiment.

[0098] The gate driving circuit 002 is electrically connected to the first signal line SL1 and the second signal line SL2, and can generate a scanning signal under the control of the signal transmitted on the first signal line SL1 and the second signal line SL2. The gate driving circuit 002 can be any one of a GIP circuit, a GOA circuit and an ASG circuit.

[0099] Optionally, the first signal line SL1 transmits a first clock signal, and the second signal line SL2 transmits a second clock signal, and the phase difference between the first clock signal and the second clock signal is 180°. That is, the first signal line SL1 and the second signal line SL2 transmit clock signals of opposite phases to the gate driving circuit 002 .

[0100] In the display panel 100, the detection circuit 001 can perform real-time detection on the signals transmitted on the first signal line SL1 and the second signal line SL2, and determine whether the signals transmitted on the first signal line SL1 or the second signal line SL2 are erroneous by detecting the detection signal V1 received by the detection port Po, thereby determining whether the gate drive circuit 002 using the signals on the first signal line SL1 and the second signal line SL2 as drive signals can work normally, which is beneficial for the display panel 100 to process the error information of the gate drive circuit 002 in a timely manner, and avoid the display panel 100 from displaying error information.

[0101] Fig.11 A schematic diagram of a display device provided in an embodiment of the present application.

[0102] The present application embodiment provides a display device 200, such as Fig.11 As shown, the display device 200 includes the display panel 100 provided in the above embodiment, and further includes a driver chip 101, the driver chip 101 is electrically connected to the first signal line SL1 and the second signal line SL2, and the signals on the first signal line SL1 and the second signal line SL2 are provided by the driver chip 101. The display device 200 provided in the embodiment of the present application may be a mobile phone, and furthermore, the display device 200 provided in the embodiment of the present application may also be an electronic device such as a computer, a television, and a car display.

[0103] In the display device 200, the detection circuit 001 can perform real-time detection on the signals transmitted on the first signal line SL1 and the second signal line SL2, and determine whether the signals transmitted on the first signal line SL1 or the second signal line SL2 are erroneous by detecting the detection signal V1 received by the detection port Po, thereby determining whether the gate drive circuit 002 using the signals on the first signal line SL1 and the second signal line SL2 as drive signals can work normally, which is beneficial for the display device 200 to process the error information of the gate drive circuit 002 in a timely manner, and avoid the display device 200 from displaying error information.

[0104] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A detection circuit, characterized in that: The detection circuit comprises: A detection signal line, used for transmitting a detection signal; Detection port; A switch module, the switch module comprising a first switch unit and a second switch unit; an input end of the first switch unit is electrically connected to an input end of the second switch unit, and is used to receive the detection signal transmitted on the detection signal line; an output end of the first switch unit is electrically connected to an output end of the second switch unit, and is used to transmit the detection signal to the detection port; The first switch unit includes a first control end, the first control end is electrically connected to the first signal line; the second switch unit includes a second control end, the second control end is electrically connected to the second signal line; the time period during which the signal transmitted by the first signal line controls the first switch unit to be turned on is different from the time period during which the signal transmitted by the second signal line controls the second switch unit to be turned on; The first switch unit includes at least one control terminal, and the at least one control terminal of the first switch unit is electrically connected to the corresponding signal line; the second switch unit includes at least one control terminal, and the at least one control terminal of the second switch unit is electrically connected to the corresponding signal line; If the detection port does not receive the detection signal during the period when the first switch unit is turned on, the signal transmitted by at least one signal line electrically connected to the control end of the first switch unit is erroneous. If the detection port does not receive the detection signal during the period when the second switch unit is turned on, the signal transmitted by at least one signal line electrically connected to the control end of the second switch unit is erroneous.

2. The detection circuit according to claim 1, characterized in that: The first switch unit comprises a first transistor, wherein a first electrode of the first transistor is electrically connected to an input terminal of the first switch unit, a second electrode of the first transistor is electrically connected to an output terminal of the first switch unit, and a gate of the first transistor is electrically connected to the first control terminal; The second switch unit comprises a second transistor, a first electrode of the second transistor is electrically connected to the input end of the second switch unit, a second electrode is electrically connected to the output end of the second switch unit, and a gate is electrically connected to the second control end; The first transistor and the second transistor have the same channel type.

3. The detection circuit according to claim 2, characterized in that: The phase difference between the signal transmitted by the first signal line and the signal transmitted by the second signal line is 180°.

4. The detection circuit according to claim 1, characterized in that: The first switch unit further includes a third control terminal, the third control terminal is electrically connected to a third signal line, and a period during which the third signal line transmits an enable signal is at least partially the same as a period during which the first signal line transmits an enable signal; The second switch unit further includes a fourth control terminal, the fourth control terminal is electrically connected to a fourth signal line, and a period during which the fourth signal line transmits an enable signal is at least partially the same as a period during which the second signal line transmits an enable signal.

5. The detection circuit according to claim 4, characterized in that: The first switch unit includes a first transistor and a third transistor, wherein a first electrode of the first transistor is electrically connected to an input terminal of the first switch unit, a second electrode is electrically connected to a first electrode of the third transistor, and a gate is electrically connected to the first control terminal; a second electrode of the third transistor is electrically connected to an output terminal of the first switch unit, and a gate is electrically connected to the third control terminal; The second switch unit includes a second transistor and a fourth transistor, wherein the first electrode of the second transistor is electrically connected to the input end of the second switch unit, the second electrode is electrically connected to the second electrode of the first transistor and the first electrode of the fourth transistor, and the gate is electrically connected to the second control end; the second electrode of the fourth transistor is electrically connected to the output end of the second switch unit, and the gate is electrically connected to the fourth control end.

6. The detection circuit according to claim 5, characterized in that: A phase difference between a signal transmitted by the first signal line and a signal transmitted by the second signal line is 180°, and a phase difference between a signal transmitted by the third signal line and a signal transmitted by the fourth signal line is 180°.

7. The detection circuit according to claim 4, characterized in that: The first switch unit includes a first transistor and a third transistor, wherein a first electrode of the first transistor is electrically connected to an input terminal of the first switch unit, a second electrode is electrically connected to a first electrode of the third transistor, and a gate is electrically connected to the first control terminal; a second electrode of the third transistor is electrically connected to an output terminal of the first switch unit, and a gate is electrically connected to the third control terminal; The second switch unit includes a second transistor and a fourth transistor, wherein the first electrode of the second transistor is electrically connected to the input end of the second switch unit, the second electrode is electrically connected to the first electrode of the fourth transistor, and the gate is electrically connected to the second control end; the second electrode of the fourth transistor is electrically connected to the output end of the second switch unit, and the gate is electrically connected to the fourth control end.

8. The detection circuit according to claim 7, characterized in that: A phase difference between a signal transmitted by the first signal line and a signal transmitted by the fourth signal line is 180°, and a phase difference between a signal transmitted by the second signal line and a signal transmitted by the third signal line is 180°.

9. The detection circuit according to claim 5 or 7, characterized in that: The channel types of the first transistor, the second transistor, the third transistor and the fourth transistor are all the same.

10. The detection circuit according to claim 7, characterized in that: The switch module further includes a third switch unit, which is connected in parallel with the first switch unit and the second switch unit, and a time period during which the third switch unit is turned on is different from a time period during which the first switch unit and the second switch unit are turned on.

11. The detection circuit according to claim 10, characterized in that: The third switch unit includes a fifth transistor and a sixth transistor, wherein a first electrode of the fifth transistor is electrically connected to an input terminal of the third switch unit, a second electrode is electrically connected to a first electrode of the sixth transistor, and a gate is electrically connected to a fifth signal line; a second electrode of the sixth transistor is electrically connected to an output terminal of the third switch unit, and a gate is electrically connected to a sixth signal line; A period during which the fifth signal line transmits an enable signal is at least partially the same as a period during which the sixth signal line transmits an enable signal.

12. The detection circuit according to claim 11, characterized in that: The fifth transistor and the sixth transistor have the same channel type as the first transistor.

13. The detection circuit according to claim 12, characterized in that: The phase difference between the signal transmitted by the first signal line and the signal transmitted by the sixth signal line is 180°, the phase difference between the signal transmitted by the second signal line and the signal transmitted by the third signal line is 180°, and the phase difference between the signal transmitted by the fourth signal line and the signal transmitted by the fifth signal line is 180°.

14. A display panel, characterized in that: The display panel comprises a detection circuit and a gate driving circuit as described in any one of claims 1 to 13; The gate driving circuit is electrically connected to the first signal line and the second signal line.

15. The display panel according to claim 14, characterized in that: The first signal line transmits a first clock signal, and the second signal line transmits a second clock signal. The phase difference between the first clock signal and the second clock signal is 180°.

16. A display device, characterized in that: Comprising a display panel as described in any one of claims 14-15.

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