A high-reliability SONOS type pFLASH switch cell structure

Abstract

The application discloses a high-reliability SONOS type pFLASH switch unit structure, and belongs to the microelectronic field. The structure comprises two 2T-FLASH tubes and one pMOS type signal transmission tube. The two 2T-FLASH tubes are in the same well. The two 2T-FLASH tubes are respectively 2T-FLASH tube T1 and 2T-FLASH tube T2, and the one pMOS type signal transmission tube is pMOS type signal transmission tube T3. T1 comprises pMOS type selection tube T12 and SONOS type pFLASH programming / erasing tube T11, the source end of T12 is connected with the drain end of T11, and a series connection relationship is formed. T2 comprises pMOS type selection tube T22 and SONOS type pFLASH programming / erasing tube T21, the source end of T22 is connected with the drain end of T21, and a series connection relationship is formed. T11 and T21 share a control gate.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a highly reliable SONOS-type pFLASH switch unit structure. Background Technology

[0002] With major projects in aerospace, electronic warfare, and communications requiring electronic systems to develop towards multi-functionality, high speed, miniaturization, and low power consumption, the demand for highly reliable and radiation-resistant programmable logic devices is becoming increasingly prominent.

[0003] FLASH switching units are the basic building blocks for reconfigurable FLASH programmable logic devices and their cores. Compared to SRAM and antifuse switching units, FLASH switching units offer advantages such as power-on operation, strong single-event immunity, and reconfigurability. FLASH switching units include floating-gate (FG) FLASH switching units and charge-trapping (CP) FLASH switching units. Floating-gate FLASH switching units store charge through a floating gate, resulting in poor charge retention. Furthermore, the feature size of floating-gate devices is difficult to shrink, limiting their development towards process nodes below 65nm. Summary of the Invention

[0004] The purpose of this invention is to provide a highly reliable SONOS-type pFLASH switch unit structure to solve the problems in the background art.

[0005] To solve the above-mentioned technical problems, the present invention provides a high-reliability SONOS type pFLASH switch unit structure, including two 2T-FLASH transistors and one pMOS type signal transmission transistor; and the two 2T-FLASH transistors are located in the same well; the two 2T-FLASH transistors are 2T-FLASH transistor T1 and 2T-FLASH transistor T2, and the pMOS type signal transmission transistor is pMOS type signal transmission transistor T3;

[0006] The 2T-FLASH transistor T1 includes a pMOS type select transistor T12 and a SONOS type pFLASH programming / erasing transistor T11. The source terminal of the pMOS type select transistor T12 is connected to the drain terminal of the SONOS type pFLASH programming / erasing transistor T11, forming a series connection.

[0007] The 2T-FLASH transistor T2 includes a pMOS type select transistor T22 and a SONOS type pFLASH programming / erasing transistor T21. The source terminal of the pMOS type select transistor T22 is connected to the drain terminal of the SONOS type pFLASH programming / erasing transistor T21, forming a series connection.

[0008] The SONOS-type pFLASH programming / erasing transistor T11 and the SONOS-type pFLASH programming / erasing transistor T21 share a common control gate; the source terminal of the SONOS-type pFLASH programming / erasing transistor T11, the source terminal of the SONOS-type pFLASH programming / erasing transistor T21, and the control gate terminal of the pMOS-type signal transmission transistor T3 are interconnected.

[0009] In one embodiment, the SONOS-type pFLASH programming / erasing transistor T11 and the SONOS-type pFLASH programming / erasing transistor T21 are respectively implemented in the on / off state using the band-to-band tunneling programming method and the Fowler-Nordheim erasing method.

[0010] In one embodiment, when the SONOS-type pFLASH programming / erasing transistor T11 is programmed, a negative potential is applied to the gate terminal of the pMOS-type select transistor T12 to turn it on, a positive potential is applied to the gate terminal of the pMOS-type select transistor T22 to turn it off, a negative potential is applied to the drain terminal of the pMOS-type select transistor T12, and a positive potential is applied to the gate terminal of the SONOS-type pFLASH programming / erasing transistor T11. This band-to-band tunneling programming method allows electrons to enter the nitride layer of the SONOS-type pFLASH programming / erasing transistor T11.

[0011] In one embodiment, when the SONOS-type pFLASH programming / erasing transistor T21 is programmed, a negative potential is applied to the gate terminal of the pMOS-type select transistor T22 to turn it on, a positive potential is applied to the gate terminal of the pMOS-type select transistor T12 to turn it off, a negative potential is applied to the drain terminal of the pMOS-type select transistor T22, and a positive potential is applied to the gate terminal of the SONOS-type pFLASH programming / erasing transistor T21. This band-to-band tunneling programming method allows electrons to enter the nitride layer of the SONOS-type pFLASH programming / erasing transistor T21.

[0012] In one embodiment, when the SONOS-type pFLASH programming / erasing transistor T11 and the SONOS-type pFLASH programming / erasing transistor T21 are simultaneously performing an erase operation, a positive potential is applied to the gate terminals of the pMOS-type select transistor T12 and the pMOS-type select transistor T22 to turn them off, a positive potential is applied to the drain terminals of the pMOS-type select transistor T12 and the pMOS-type select transistor T22, and a negative potential is applied to the common control gate terminal of the SONOS-type pFLASH programming / erasing transistors T11 and T21. The Fowler-Nordheim erase method is used to allow electrons to flow out of the nitride layer of the SONOS-type pFLASH programming / erasing transistors T11 and T21.

[0013] In one embodiment, the first operation method steps for the pMOS type signal transmission transistor T3 to be in the on state are as follows: (1) simultaneously erasing the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21; (2) programming the SONOS type pFLASH programming / erasing transistor T21; (3) connecting the drain of the pMOS type selection transistor T12 to the GND potential, and simultaneously erasing the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21. The common control gate of the OS-type pFLASH programming / erasing transistor T21 is connected to the GND potential. The gates of the pMOS-type select transistor T12 and the pMOS-type select transistor T22 are both connected to the -Vcc potential. The drain of the pMOS-type select transistor T22 is connected to the -Vcc potential, so that the -Vcc potential is transmitted to the control gate of the pMOS-type signal transmission transistor T3 through the pMOS-type select transistor T22 and the SONOS-type pFLASH programming / erasing transistor T21, thereby realizing the on state of the pMOS-type signal transmission transistor T3.

[0014] In one embodiment, the second operation method for putting the pMOS signal transmission transistor T3 in the on state includes the following steps: (1) simultaneously erasing the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T21; (2) programming the SONOS pFLASH programming / erasing transistor T11; (3) connecting the drain of the pMOS selection transistor T22 to the GND potential, connecting the common control gate of the SONOS pFLASH programming / erasing transistors T11 and T21 to the GND potential, connecting the gate of the pMOS selection transistor T12 and the gate of the pMOS selection transistor T22 to the -Vcc potential, and connecting the drain of the pMOS selection transistor T12 to the -Vcc potential, so that the -Vcc potential is transmitted to the control gate of the pMOS signal transmission transistor T3 through the pMOS selection transistor T12 and the SONOS pFLASH programming / erasing transistor T11, thereby realizing the on state of the pMOS signal transmission transistor T3.

[0015] In one embodiment, the first operation method steps for putting the pMOS signal transmission transistor T3 in the off state are as follows: (1) simultaneously performing an erase operation on the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T21; (2) performing a programming operation on the SONOS pFLASH programming / erasing transistor T11; (3) jointly controlling the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T21. The gate terminal of the pMOS select transistor T22 is connected to the GND potential, the drain terminal of the pMOS select transistor T12 is connected to the -Vcc potential, and the gate terminals of both the pMOS select transistor T12 and the pMOS select transistor T22 are connected to the -Vcc potential. The drain terminal of the pMOS select transistor T12 is connected to the GND potential, so that the GND potential is transmitted to the control gate terminal of the pMOS signal transmission transistor T3 through the pMOS select transistor T12 and the SONOS pFLASH programming / erasing transistor T11, thereby realizing the off state of the pMOS signal transmission transistor T3.

[0016] In one embodiment, the second operation method for putting the pMOS signal transmission transistor T3 in the off state includes the following steps: (1) simultaneously erasing the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T21; (2) programming the SONOS pFLASH programming / erasing transistor T21; and (3) jointly controlling the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T21. The gate terminal of the pMOS select transistor T12 is connected to the GND potential, the drain terminal of the pMOS select transistor T12 is connected to the -Vcc potential, the gate terminals of the pMOS select transistor T12 and the pMOS select transistor T22 are both connected to the -Vcc potential, and the drain terminal of the pMOS select transistor T22 is connected to the GND potential. The GND potential is transmitted to the control gate terminal of the pMOS signal transmission transistor T3 through the pMOS select transistor T22 and the SONOS pFLASH programming / erasing transistor T21, thereby realizing the on state of the pMOS signal transmission transistor T3.

[0017] The high-reliability SONOS-type pFLASH switch cell structure provided in this invention employs an indirect coupling structure, effectively isolating the signal transmission transistor from the programming / erasing transistor, thus enhancing its anti-interference capability. The SONOS-type pFLASH transistor, used as the programming / erasing transistor, has a long charge retention life, further enhancing the reliability of the switch cell. Simultaneously, its signal transmission transistor can be a low-voltage MOSFET, effectively improving its driving capability and increasing the speed of control signal transmission. Using a mirror erase / programming method to realize the on / off state of the signal transmission transistor in the switch cell array can reduce tunnel oxide layer damage, avoid abnormal phenomena caused by over-erasing leading to device failure, and balance the number of programming and erasing cycles experienced by the SONOS-type pFLASH transistor, which is beneficial to improving its durability. The feature size of the SONOS-type pFLASH switch cell can be further reduced, thereby realizing the fabrication of low-power, high-speed, high-reliability, and highly integrated FLASH-type programmable logic devices. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the equivalent structure of a high-reliability SONOS-type pFLASH switch unit provided by the present invention;

[0019] Figure 2 This is a schematic diagram of the first operation method steps and signal transmission path of the pMOS signal transmission transistor T3 in the on state in this invention;

[0020] Figure 3 This is a schematic diagram of the second operation method steps and signal transmission path in which the pMOS signal transmission transistor T3 is in the on state in this invention;

[0021] Figure 4 This is a schematic diagram of the first operation method steps and signal transmission path in which the pMOS signal transmission transistor T3 is in the off state in this invention;

[0022] Figure 5 This is a schematic diagram of the second operation method steps and signal transmission path in which the pMOS signal transmission transistor T3 is in the off state in this invention.

[0023] Figure reference numerals: D3 - drain terminal of pMOS type signal transmission transistor T3, S3 - source terminal of pMOS type signal transmission transistor T3, Vg - gate terminal potential of pMOS type signal transmission transistor T3, Vin - signal input, Vout - signal output. Detailed Implementation

[0024] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the high-reliability SONOS-type pFLASH switch unit structure proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0025] This invention provides a highly reliable SONOS-type pFLASH switch unit structure, such as... Figure 1As shown, it includes two 2T-FLASH transistors and one pMOS signal transmission transistor, with the two 2T-FLASH transistors located in the same well B1. The two 2T-FLASH transistors are designated as 2T-FLASH transistor T1 and 2T-FLASH transistor T2, and the pMOS signal transmission transistor is designated as pMOS signal transmission transistor T3. The 2T-FLASH transistor T1 consists of one pMOS select transistor T12 and one SONOS pFLASH programming / erasing transistor T11. The source terminal of the pMOS select transistor T12 is connected to the drain terminal of the SONOS pFLASH programming / erasing transistor T11, forming a series connection. The 2T-FLASH transistor T2 consists of one pMOS type select transistor T22 and one SONOS type FLASH programming / erasing transistor T21. The source terminal of the pMOS type select transistor T22 is connected to the drain terminal of the SONOS type pFLASH programming / erasing transistor T21, forming a series connection. Furthermore, the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21 share a common control gate terminal CG. The source terminals of the SONOS type pFLASH programming / erasing transistor T11, the SONOS type pFLASH programming / erasing transistor T21, and the control gate terminal of the pMOS type signal transmission transistor T3 are interconnected. The SONOS-type pFLASH programming / erasing transistor T11 and the SONOS-type pFLASH programming / erasing transistor T21 are respectively implemented in the BTBT (band to band tunneling) programming mode and the FN (Fowler-Nordheim) erasing mode to realize their on / off states.

[0026] When the SONOS-type pFLASH programming / erasing transistor T11 is programmed, a specified negative potential is applied to the gate terminal SG1 of the pMOS-type select transistor T12 to turn it on, a specified positive potential is applied to the gate terminal SG2 of the pMOS-type select transistor T22 to turn it off, a specified negative potential is applied to the drain terminal D1 of the pMOS-type select transistor T12, and a specified positive potential is applied to the gate terminal CG of the SONOS-type pFLASH programming / erasing transistor T11. Electrons are introduced into the nitride layer of the SONOS-type pFLASH programming / erasing transistor T11 using the BTBT method.

[0027] When the SONOS-type pFLASH programming / erasing transistor T21 is programmed, a specified negative potential is applied to the gate terminal SG2 of the pMOS-type select transistor T22 to turn it on, a specified positive potential is applied to the gate terminal SG1 of the pMOS-type select transistor T12 to turn it off, a specified negative potential is applied to the drain terminal D2 of the pMOS-type select transistor T22, and a specified positive potential is applied to the gate terminal CG of the SONOS-type FLASH programming / erasing transistor T21. Electrons are introduced into the nitride layer of the SONOS-type FLASH programming / erasing transistor T21 using the BTBT method.

[0028] When the SONOS-type pFLASH programming / erasing transistor T11 and the SONOS-type pFLASH programming / erasing transistor T21 are simultaneously performing an erase operation, a specified positive potential is applied to the gate terminal SG1 of the pMOS-type select transistor T12 and the gate terminal SG2 of the pMOS-type select transistor T22 to keep them in the off state. A specified positive potential is applied to the drain terminal D1 of the pMOS-type select transistor T12 and the drain terminal D2 of the pMOS-type select transistor T22. At the same time, a specified negative potential is applied to the control gate terminal CG of the SONOS-type pFLASH programming / erasing transistor T11 and the SONOS-type pFLASH programming / erasing transistor T21. Electrons are allowed to flow out of the nitride layer of the SONOS-type pFLASH programming / erasing transistor T11 and the SONOS-type pFLASH programming / erasing transistor T21 using the FN method.

[0029] like Figure 2 As shown, the first operation method for the pMOS type signal transmission transistor T3 in the on state includes the following steps: (1) Simultaneously performing erase operations on the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21; (2) Performing a programming operation on the SONOS type pFLASH programming / erasing transistor T21; (3) Connecting the drain terminal D1 of the pMOS type selection transistor T12 to the GND potential, and simultaneously performing an erase operation on the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21. The control gate terminal CG of the SH programming / erasing transistor T21 is connected to the GND potential. The gate terminals SG1 and SG2 of the pMOS type select transistor T12 and the pMOS type select transistor T22 are both connected to the -Vcc potential. The drain terminal D2 of the pMOS type select transistor T22 is connected to the -Vcc potential, so that the -Vcc potential is transmitted to the control gate terminal G of the pMOS type signal transmission transistor T3 through the pMOS type select transistor T22 and the SONOS type pFLASH programming / erasing transistor T21, thereby realizing the on state of the pMOS type signal transmission transistor T3.

[0030] like Figure 3 As shown, the second operation method for the pMOS type signal transmission transistor T3 in the on state includes the following steps: (1) Simultaneously erase the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21; (2) Program the SONOS type pFLASH programming / erasing transistor T11; (3) Connect the drain terminal D2 of the pMOS type selection transistor T22 to the GND potential, and simultaneously erase the SONOS type pFLASH programming / erasing transistors T11 and T21. The control gate terminal CG of transistor 21 is connected to the GND potential. The gate terminals SG1 and SG2 of the pMOS type select transistor T12 and pMOS type select transistor T22 are both connected to the -Vcc potential. The drain terminal D1 of the pMOS type select transistor T12 is connected to the -Vcc potential, so that the -Vcc potential is transmitted to the control gate terminal G of the pMOS type signal transmission transistor T3 through the pMOS type select transistor T12 and the SONOS type pFLASH programming / erasing transistor T11, thereby realizing the on state of the pMOS type signal transmission transistor T3.

[0031] like Figure 4 As shown, the first operation method for the pMOS type signal transmission transistor T3 to be in the off state includes the following steps: (1) Simultaneously performing an erase operation on the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21; (2) Performing a programming operation on the SONOS type pFLASH programming / erasing transistor T11; (3) Connecting the control gate terminal CG of the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21 to the GND potential. The drain terminal D2 of the pMOS type select transistor T22 is connected to the -Vcc potential, and the gate terminals SG1 and SG2 of the pMOS type select transistor T12 are both connected to the -Vcc potential. The drain terminal D1 of the pMOS type select transistor T12 is connected to the GND potential, so that the GND potential is transmitted to the control gate terminal G of the pMOS type signal transmission transistor T3 through the pMOS type select transistor T12 and the SONOS type pFLASH programming / erasing transistor T11, thereby realizing the off state of the pMOS type signal transmission transistor T3.

[0032] like Figure 5As shown, the second operation method for the pMOS type signal transmission transistor T3 to be in the off state includes the following steps: (1) Simultaneously performing an erase operation on the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21; (2) Performing a programming operation on the SONOS type pFLASH programming / erasing transistor T21; (3) Connecting the control gate terminal CG of the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21 to the GND potential. The drain terminal D1 of the pMOS type select transistor T12 is connected to the -Vcc potential, and the gate terminal SG1 of the pMOS type select transistor T12 and the gate terminal SG2 of the pMOS type select transistor T22 are both connected to the -Vcc potential. The drain terminal D2 of the pMOS type select transistor T22 is connected to the GND potential, so that the GND potential is transmitted to the control gate terminal G of the pMOS type signal transmission transistor T3 through the pMOS type select transistor T22 and the SONOS type pFLASH programming / erasing transistor T21, thereby realizing the on state of the pMOS type signal transmission transistor T3.

[0033] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A high-reliability SONOS-type pFLASH switch unit structure, characterized in that, It includes two 2T-FLASH transistors and one pMOS type signal transmission transistor; the two 2T-FLASH transistors are located in the same well; the two 2T-FLASH transistors are 2T-FLASH transistor T1 and 2T-FLASH transistor T2, and the pMOS type signal transmission transistor is pMOS type signal transmission transistor T3; The 2T-FLASH transistor T1 includes a pMOS type select transistor T12 and a SONOS type pFLASH programming / erasing transistor T11. The source terminal of the pMOS type select transistor T12 is connected to the drain terminal of the SONOS type pFLASH programming / erasing transistor T11, forming a series connection. The 2T-FLASH transistor T2 includes a pMOS type select transistor T22 and a SONOS type pFLASH programming / erasing transistor T21. The source terminal of the pMOS type select transistor T22 is connected to the drain terminal of the SONOS type pFLASH programming / erasing transistor T21, forming a series connection. The SONOS-type pFLASH programming / erasing transistor T11 and the SONOS-type pFLASH programming / erasing transistor T21 share a common control gate; the source terminal of the SONOS-type pFLASH programming / erasing transistor T11, the source terminal of the SONOS-type pFLASH programming / erasing transistor T21, and the control gate terminal of the pMOS-type signal transmission transistor T3 are interconnected. When the SONOS-type pFLASH programming / erasing transistor T11 is programmed, a negative potential is applied to the gate terminal of the pMOS-type select transistor T12 to turn it on, a positive potential is applied to the gate terminal of the pMOS-type select transistor T22 to turn it off, a negative potential is applied to the drain terminal of the pMOS-type select transistor T12, and a positive potential is applied to the gate terminal of the SONOS-type pFLASH programming / erasing transistor T11. The band-to-band tunneling programming method is used to allow electrons to enter the nitride layer of the SONOS-type pFLASH programming / erasing transistor T11. When the SONOS-type pFLASH programming / erasing transistor T21 is programmed, a negative potential is applied to the gate terminal of the pMOS-type select transistor T22 to turn it on, a positive potential is applied to the gate terminal of the pMOS-type select transistor T12 to turn it off, a negative potential is applied to the drain terminal of the pMOS-type select transistor T22, and a positive potential is applied to the gate terminal of the SONOS-type pFLASH programming / erasing transistor T21. The band-to-band tunneling programming method is used to allow electrons to enter the nitride layer of the SONOS-type pFLASH programming / erasing transistor T21.

2. The high-reliability SONOS-type pFLASH switch unit structure as described in claim 1, characterized in that, The SONOS-type pFLASH programming / erasing transistor T11 and the SONOS-type pFLASH programming / erasing transistor T21 both adopt the band-to-band tunneling programming method and the Fowler-Nordheim erasing method to realize their on / off states respectively.

3. The high-reliability SONOS-type pFLASH switch unit structure as described in claim 2, characterized in that, When the SONOS-type pFLASH programming / erasing transistor T11 and the SONOS-type pFLASH programming / erasing transistor T21 are simultaneously erased, a positive potential is applied to the gate terminals of the pMOS-type select transistor T12 and the pMOS-type select transistor T22 to turn them off. A positive potential is applied to the drain terminals of the pMOS-type select transistor T12 and the pMOS-type select transistor T22. At the same time, a negative potential is applied to the common control gate terminal of the SONOS-type pFLASH programming / erasing transistors T11 and T21. The Fowler-Nordheim erasing method is used to allow electrons to flow out of the nitride layer of the SONOS-type pFLASH programming / erasing transistors T11 and T21.

4. The high-reliability SONOS-type pFLASH switch unit structure as described in claim 3, characterized in that, The first operation method for the pMOS type signal transmission transistor T3 to be in the on state includes the following steps: (1) simultaneously erasing the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21; (2) programming the SONOS type pFLASH programming / erasing transistor T21. (3) The drain of the pMOS type select transistor T12 is connected to the GND potential, the common control gate of the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21 is connected to the GND potential, the gate of the pMOS type select transistor T12 and the gate of the pMOS type select transistor T22 are both connected to the -Vcc potential, and the drain of the pMOS type select transistor T22 is connected to the -Vcc potential, so that the -Vcc potential is transmitted to the control gate of the pMOS type signal transmission transistor T3 through the pMOS type select transistor T22 and the SONOS type pFLASH programming / erasing transistor T21, thereby realizing the on state of the pMOS type signal transmission transistor T3.

5. The high-reliability SONOS-type pFLASH switch unit structure as described in claim 4, characterized in that, The second operation method for the pMOS type signal transmission transistor T3 in the on state is as follows: (1) Simultaneously erase the SONOS type pFLASH programming / erasing transistor T11 and the SONOS type pFLASH programming / erasing transistor T21; (2) Program the SONOS type pFLASH programming / erasing transistor T11. (3) The drain of the pMOS type select transistor T22 is connected to the GND potential, the common control gate of the SONOS type pFLASH programming / erasing transistors T11 and T21 is connected to the GND potential, the gate of the pMOS type select transistor T12 and the gate of the pMOS type select transistor T22 are both connected to the -Vcc potential, and the drain of the pMOS type select transistor T12 is connected to the -Vcc potential, so that the -Vcc potential is transmitted to the control gate of the pMOS type signal transmission transistor T3 through the pMOS type select transistor T12 and the SONOS type pFLASH programming / erasing transistor T11, thereby realizing the on state of the pMOS type signal transmission transistor T3.

6. The high-reliability SONOS-type pFLASH switch unit structure as described in claim 5, characterized in that, The first operation method for the pMOS signal transmission transistor T3 to be in the off state includes the following steps: (1) Simultaneously performing an erase operation on the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T21; (2) Performing a programming operation on the SONOS pFLASH programming / erasing transistor T11; (3) Connecting the common control gate terminal of the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T21 to G. The drain of the pMOS select transistor T22 is connected to the -Vcc potential, and the gates of both the pMOS select transistor T12 and the pMOS select transistor T22 are connected to the -Vcc potential. The drain of the pMOS select transistor T12 is connected to the GND potential, so that the GND potential is transmitted to the control gate of the pMOS signal transmission transistor T3 through the pMOS select transistor T12 and the SONOS pFLASH programming / erasing transistor T11, thereby realizing the off state of the pMOS signal transmission transistor T3.

7. The high-reliability SONOS-type pFLASH switch unit structure as described in claim 6, characterized in that, The second operation method for the pMOS signal transmission transistor T3 to be in the off state includes the following steps: (1) Simultaneously erase the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T21; (2) Program the SONOS pFLASH programming / erasing transistor T21; (3) Connect the common control gate terminal of the SONOS pFLASH programming / erasing transistor T11 and the SONOS pFLASH programming / erasing transistor T21 to G. The drain of the pMOS select transistor T12 is connected to the -Vcc potential, and the gates of both the pMOS select transistor T12 and the pMOS select transistor T22 are connected to the -Vcc potential. The drain of the pMOS select transistor T22 is connected to the GND potential, so that the GND potential is transmitted to the control gate of the pMOS signal transmission transistor T3 through the pMOS select transistor T22 and the SONOS pFLASH programming / erasing transistor T21, thereby realizing the on state of the pMOS signal transmission transistor T3.

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