Voltage threshold prediction-based memory management

Abstract

This application relates to memory management based on voltage threshold prediction. A method includes: performing a first read operation involving a group of memory cells using a first voltage; determining a number of bits associated with the group of memory cells based on the first read operation; performing a second read operation involving the group of memory cells using a second voltage greater than the first voltage when the number of bits is higher than a threshold number of bits for the group of memory cells; and performing the second read operation involving the group of memory cells using a third voltage less than the first voltage when the number of bits is lower than the threshold number of bits for the group of memory cells.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to memory management based on voltage threshold prediction. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] According to one aspect of this application, a method for memory management based on voltage threshold prediction is provided. The method includes: performing a first read operation involving a group of memory cells using a first voltage; determining a number of bits associated with the group of memory cells based on the first read operation; performing a second read operation involving the group of memory cells using a second voltage greater than the first voltage when the number of bits is higher than a threshold number of bits for the group of memory cells; and performing the second read operation involving the group of memory cells using a third voltage less than the first voltage when the number of bits is lower than the threshold number of bits for the group of memory cells.

[0004] According to another aspect of this application, an apparatus for memory management based on voltage threshold prediction is provided. The apparatus includes: a voltage threshold prediction component configured to: perform a first read operation involving the group of memory cells using a first threshold voltage targeting specific memory cells from a group of memory cells; determine a number of bits in the group of memory cells based on the first read operation using the first threshold voltage; determine a first threshold number of bits in the group of memory cells based on the first threshold voltage; determine a second threshold number of bits in the group of memory cells based on the first threshold voltage; determine a second threshold voltage to be used for a second read operation based on a comparison between the determined number of bits and the first and second threshold number of bits; and perform the second read operation using the second threshold voltage.

[0005] According to another aspect of this application, a system for memory management based on voltage threshold prediction is provided. The system includes: a plurality of memory components arranged to form a stacked cross-grid array of interleaved NAND memory cells; and a processing means coupled to the plurality of memory components, the processing means being configured to perform operations including: performing a first single-level cell (SLC) read involving a group of memory cells using a first threshold voltage to target a specific memory cell in the group of memory cells; determining the number of bits in the group of memory cells based on the first SLC read using the first threshold voltage; determining an upper bit count threshold and a lower bit count threshold for the group of memory cells based on the first threshold voltage; and performing a set of SLC reads involving the group of memory cells using a set of threshold voltages, wherein the set of threshold voltages: includes a set of positive offsets when the determined number of bits is greater than the upper bit count threshold; includes a set of negative offsets when the determined number of bits is less than the lower bit count threshold; or includes a combination of positive and negative offsets, or any combination thereof, when the determined number of bits is between the upper bit count threshold and the lower bit count threshold. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of the various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart corresponding to a method for memory management based on voltage threshold prediction, according to some embodiments of this disclosure.

[0009] Figure 3 This is a flowchart corresponding to a method for memory management based on voltage threshold prediction, according to some embodiments of this disclosure.

[0010] Figure 4 This document describes an example of voltage threshold prediction for a set of memory cells according to some embodiments of the present disclosure.

[0011] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0012] This disclosure relates to error recovery operations in memory subsystems, and more specifically, to memory subsystems including voltage threshold prediction components. A memory subsystem may be a storage system, a storage device, a memory module, or a combination thereof. An example of a memory subsystem is a storage system, such as a solid-state drive (SSD). The following is combined with… Figure 1 And other examples describing storage devices and memory modules. Generally, a host system may utilize a memory subsystem containing one or more components, such as memory devices, that store data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] The memory device can be a non-volatile memory device. An example of a non-volatile memory device is a NAND flash memory device (also known as flash memory). The following section combines... Figure 1 Other examples of non-volatile memory devices are described below. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be divided into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A block, hereinafter, refers to a unit of memory device used to store data and may contain a group of memory cells, a group of word lines, a word line, or individual memory cells. For some memory devices, a block (hereinafter also referred to as a “memory block”) is the smallest erasable area. Pages cannot be erased individually; only the entire block can be erased.

[0014] Each memory device may contain one or more arrays of memory cells. Depending on the cell type, a cell may store one or more binary information bits and has various logic states related to the number of bits stored. These logic states may be represented by binary values ​​such as "0" and "1" or combinations of such values. Various types of cells exist, such as single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC may store one information bit and have two logic states.

[0015] Some NAND memory devices employ a floating gate architecture, where memory access is controlled based on the relative voltage variation between the bit lines and word lines. Other instances of NAND memory devices may employ an alternative gate architecture, which may include a word line layout that allows charges corresponding to data values ​​to be trapped within the memory cells based on the properties of the materials used to construct the word lines.

[0016] During operation, the memory subsystem can introduce errors that can affect the quality and / or accuracy of data written to and stored by the memory subsystem. Such errors may include loss or gain of charge associated with memory cells, read interference, write interference, and / or degradation of data / cell quality due to the number of programming / erase cycles experienced by the cells. As the memory subsystem ages, these errors can become increasingly difficult to correct and / or mitigate, especially in mobile computing system architectures where the amount of physical space available for hardware components may be limited. Furthermore, these errors can become more pronounced and / or more frequent over time (e.g., as the memory subsystem ages), which can further affect the quality and / or accuracy of data written to and stored by the memory subsystem. Moreover, such errors can become difficult to mitigate and / or correct under edge conditions, such as when the memory subsystem is experiencing stress conditions, for example, when the memory subsystem is exposed to frequent and / or rigorous end-of-life (EOL) test operations to ensure the operational viability of the memory subsystem.

[0017] Some methods attempt to mitigate the type of error described above by performing a series (or at least a portion of a series) of error handling processes (e.g., read error handling (REH) procedures) to correct such errors and / or determine whether the correction of such errors was successful. Such methods may sequentially perform different operations as part of performing a series of error handling processes to determine whether any of these operations can remedy the detected error. As an example, some methods may attempt to read memory cells with various retry voltage offsets. For instance, some methods may identify specific parameters that include a threshold voltage for a set of memory cells (e.g., word lines, portions of word lines, etc.). In this example, the various retry voltage offsets may include voltages greater than the threshold voltage and voltages less than the threshold voltage (V) in an oscillating manner. T Assertions about the voltage of a signal. For example, in memory access operations, a voltage greater than V... T The voltage can be asserted, followed by less than V. T The assertion of voltage, followed by a voltage greater than the previous voltage (which is greater than V). T The voltage can be asserted to be less than the previous voltage (which is less than V). T Assertions about the voltage of the memory cell, etc. In this way, some methods attempt to identify whether the threshold voltage of the group of memory cells has shifted by utilizing various retry voltage offsets. However, such methods can be time-consuming and computationally intensive.

[0018] For example, in some methods, each of a variety of retry voltage offsets may be tried to determine whether one of the various retry voltage offsets allows a set of memory cells to be decoded. This can be a computationally intensive process because some methods arbitrarily test the set of memory cells using both voltage offsets greater than and less than a voltage threshold for the set of memory cells, without considering the inherent behavior of the memory cells. Therefore, in such methods, testing various retry voltage offsets can be expensive in terms of both time and computational resources.

[0019] This disclosure predicts a threshold voltage (V) based on memory access operations (e.g., read or write operations) involving a set of memory cells. T The movement of the voltage (V) addresses the aforementioned and other drawbacks. In some embodiments, the number of bits stored or written to a set of memory cells can be determined using a threshold voltage. Therefore, above or below the applied V T The number of bits can be determined, and can be found in V. T The assertion is based on the behavior of the group of memory cells over time. As will be understood, the threshold voltage of the group of memory cells may correspond to a specific read level of the group of memory cells. As used herein, "read level" generally refers to a specific voltage applied to one or more memory cells to perform a memory access involving the physical location of the memory device. In this way, the applied read or write voltage can be used to predict the number of bits exhibiting voltage drift characteristics relative to the threshold voltage (e.g., the number of bits associated with word lines that have experienced time or degradation based on other voltages). This information can be used to determine the number of threshold bits that have experienced access voltage drift, such that it can be made that the threshold voltage to be applied to one or more of the group of memory cells is in the positive direction (e.g., greater than the initial V). T The access voltage is still in the negative direction (e.g., less than the initial V). T The prediction of the shift in the access voltage.

[0020] In some embodiments, V T This can correspond to a specific voltage within a voltage distribution associated with a set of memory cells, which corresponds to V that, when applied to a specific memory cell or a set of memory cells, returns the accurate data value stored by said memory cell or set of memory cells. T Valleys within the distribution. As described in this paper, the charge stored by a memory cell or a group of memory cells can "drift" (e.g., shift) over time. When the previous V T When it has changed over time, use the previous V. T The memory access operation performed may no longer fall under V. TThe voltages within the valleys of the distribution are correlated. In this way, a fault can occur, or when a previous voltage... T When applied to a specific memory cell or a set of memory cells, inaccurate data can be returned. For example, the previous V value may have been "offset". T The read voltage may not be the optimized read level for a specific memory cell or a set of memory cells (e.g., it may not be V). T (Valuation valley). Therefore, the embodiments described herein may attempt to optimize the read voltage for subsequent read operations such that the subsequent read operations use V values ​​that fall within the valley of the voltage distribution after the charge stored by the memory cell or set of memory cells has undergone voltage drift. T implement.

[0021] This disclosure addresses the aforementioned and other drawbacks by allowing a reduction in the number of offsets that can be tested during memory cell decoding. For example, by performing the operations described herein, memory subsystem performance can be improved compared to the methods described above because fewer offsets can be tested to determine the voltage at which a set of memory cells can be decoded. In some embodiments, half the offset can be used to identify the voltage threshold for decoding a set of memory cells. For example, instead of using both positive and negative retest voltage offsets to determine whether the voltage threshold of a set of memory cells has moved in the positive or negative direction, this method can base its determination on the number of threshold bits and the specific V value obtained from a read or write operation. T A comparison between a predetermined number of successfully (or unsuccessfully) decoded bits limits the offset to either all positive or all negative. In some embodiments, the prediction of the threshold voltage shift can be made using a single-level read operation of a set of memory cells (e.g., corresponding to a single V). T This is accomplished by asserting the signal. In this way, the offset opposite to the movement of the voltage indicating the accurate read or write of a set of memory cells (or the constituent memory cells contained within the set of memory cells) may not need to be tested, and thus the performance of error recovery operations can be improved.

[0022] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device such as a desktop computer, server, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing device.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0026] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110 (for example) to write data to and read data from the memory subsystem 110.

[0027] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize NVM High Speed ​​(NVMe) interface access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-situ write memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on volume resistance variations combined with a stackable cross-gate format data access array. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 and 140 may include one or more arrays of memory cells. For example, a type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] Although non-volatile memory components such as three-dimensional cross-point arrays of non-volatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND) have been described, memory device 130 may be based on any other type of non-volatile memory or storage device, such as (e.g.) read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 may be a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already Figure 1 The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may handle other operations such as wear leveling, discard item collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing memory devices 130 and / or 140, and can also translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the memory subsystem controller 115 to access memory devices 130 and / or 140.

[0037] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] The memory subsystem 110 may include a voltage threshold prediction component 113. Although not explicitly stated... Figure 1 The diagram is shown to avoid confusion, but the voltage threshold prediction-based memory management component 113 may include various circuitry to facilitate determining the number of bits associated with a set of memory cells based on a first read operation and performing a second read operation based on the determined number of bits. In some embodiments, the voltage threshold prediction-based memory management component 113 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry that allows the voltage threshold prediction-based memory management component 113 to orchestrate and / or perform operations to selectively perform media management operations for memory device 130 and / or memory device 140 (e.g., to determine V) based at least on the number of programmed bits in a set of memory cells. T drift).

[0039] In some embodiments, the memory subsystem controller 115 includes at least a portion of a voltage threshold prediction-based memory management component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 to perform the operations described herein. In some embodiments, the voltage threshold prediction-based memory management component 113 is part of the memory subsystem 110, an application program, or an operating system.

[0040] In a non-limiting example, the device (e.g., computing system 100) may include a memory management component 113 based on memory subsystem voltage threshold prediction. The memory management component 113 based on memory subsystem voltage threshold prediction may reside on memory subsystem 110. As used herein, the term "resides on" means something physically located on a particular component. For example, "resides on" memory management component 113 based on memory subsystem voltage threshold prediction means that the hardware circuitry including the memory management component 113 is physically located on memory subsystem 110. In this document, the term "resides on" may be used interchangeably with other terms such as "deployed on" or "located on".

[0041] The memory management component 113, based on memory subsystem voltage threshold prediction, can perform (or cause to perform) a first read operation involving said group of memory cells using a first threshold voltage that targets a specific memory cell from a group of memory cells. In some instances, the group of memory cells includes word lines of a NAND memory device. In some embodiments, the first read operation may be a single-level cell (SLC) read operation of a word line of a NAND memory device. The first read operation involving the group of memory cells may utilize an identified voltage threshold assigned to the group of memory cells. For example, the voltage threshold may be a parameter of the group of memory cells. In some embodiments, the first read operation may be performed using a first voltage corresponding to a first read level of the group of memory cells. For example, the threshold voltage may be a voltage that targets a specific physical location within the group of memory cells. In this example, the read level may be a specific physical location within the group of memory cells targeted by the threshold voltage.

[0042] The memory management component 113, based on memory subsystem voltage threshold prediction, can determine (or cause to make a determination about the number of bits) the number of bits in a set of memory cells based on a first read operation using a first threshold voltage. As used herein, "number of bits" generally refers to the counted number of binary information stored by a set of memory cells or a portion of a set of memory cells. In some embodiments, the number of bits associated with a set of memory cells may be a portion of the total number of bits associated with a set of memory cells. For example, the first voltage may be a voltage that targets the physical location of a particular memory cell corresponding to a specific location or several specific locations of the memory cells. In this example, a first portion of a set of memory cells may be located on a first side of a particular memory cell, and a second portion of a set of memory cells may be located on a second side of a memory cell. In this example, the number of bits can be determined by reading the first portion or the second portion of a set of memory cells. As further described herein, the threshold number of successfully (or unsuccessfully) decoded bits may be determined based on the first voltage and whether the first portion or the second portion of a set of memory cells was read by the first read operation. As used herein, for example, the "threshold" for the number of threshold bits generally refers to a specified number of programmed bits within a portion of a set of memory cells.

[0043] The memory management component 113, based on memory subsystem voltage threshold prediction, can be configured to predict threshold voltage (V). T A first threshold number of bits for a set of memory cells is determined. In some embodiments, the first threshold number of bits for a set of memory cells may include an upper threshold number of bits for the set of memory cells. For example, the first threshold number of bits may be a threshold that indicates that the threshold voltage of the set of memory cells has shifted in a particular direction and therefore more bits than predicted have been read when a determined number of bits is exceeded.

[0044] The memory management component 113, which predicts a memory subsystem voltage threshold, can be configured to determine a second threshold number of bits for a set of memory cells based on a threshold voltage. In some embodiments, the second threshold number of bits for a set of memory cells may include a lower threshold number of bits for the set of memory cells. For example, the second threshold number of bits may be a threshold that indicates that the threshold voltage of the set of memory cells has shifted in a particular direction and therefore fewer bits have been read than predicted when an undetermined number of bits is exceeded.

[0045] As described herein, shifting the threshold voltage can be used to select a specific set of offset voltages to be used for subsequent read operations. In some embodiments, a first set of offset voltages greater than a first threshold voltage can be selected when the number of bits is greater than the first threshold, and a second set of offset voltages less than the first threshold voltage can be selected when the number of bits is less than a second threshold. In some embodiments, when the number of bits is between the first threshold number of bits and the second threshold number of bits, a third set of offset voltages may include portions of voltages greater than the first threshold voltage and portions of voltages less than the first threshold voltage. In some embodiments, when the determined number of bits is between the first threshold number of bits and the second threshold number of bits, an error recovery operation may revert to a previous set of offset voltages for testing.

[0046] The memory management component 113, based on memory subsystem voltage threshold prediction, can be configured to determine a second threshold voltage to be used for a second read operation based on a comparison between a determined number of bits and first and second threshold bit numbers. As described herein, the determined number of bits from the first read operation can be compared with the first threshold bit number and the second threshold bit number. As described herein, the first threshold voltage can be changed to the second threshold voltage based on the comparison. For example, where the comparison identifies a number of bits greater than the first threshold bit number, the second threshold voltage can be greater than the first threshold voltage. In different instances, when the comparison identifies a number of bits less than the second threshold bit number, the second threshold voltage can be less than the first threshold voltage. In this way, the second threshold voltage can be changed to a voltage determined to be closer to the threshold voltage that can be used to decode a set of memory cells. Additionally, subsequent threshold voltages that are unlikely to be used to decode a set of memory cells can be avoided or not used to perform read operations.

[0047] Memory management component 113, based on memory subsystem voltage threshold prediction, can be configured to perform a second read operation using a second threshold voltage. In some embodiments, the second threshold voltage may be a first offset voltage utilized during an error recovery operation. As described herein, subsequent offset voltages may be selected based on comparisons between the number of bits determined using the first read operation. That is, when the number of bits is greater than a first threshold number of bits, a subsequent offset voltage greater than the first threshold voltage may be selected, and when the number of bits is less than a second threshold number of bits, a subsequent offset voltage less than the first threshold voltage may be selected. This avoids using offset voltages that move away from a specific threshold voltage relative to the first threshold voltage. In some embodiments, the second threshold voltage is greater than the first threshold voltage when the determined number of bits is greater than the first threshold number of bits. In other embodiments, the second threshold voltage is less than the first threshold voltage when the determined number of bits is less than the second threshold number of bits.

[0048] In some embodiments, the voltage threshold prediction-based memory management component 113 may be configured to perform a second read operation using a second threshold voltage greater than the first threshold voltage when the determined number of bits is between a first threshold number of bits and a second threshold number of bits, and to perform a third read operation using a third threshold voltage less than the first threshold voltage. In some embodiments, the determined number of bits from the first read operation between the first threshold number of bits and the second threshold number of bits may indicate a threshold or a voltage for decoding a set of memory cells that is relatively close to the first threshold voltage. In these embodiments, a set of offsets relatively close to the first threshold voltage may be selected. For example, a second threshold voltage greater than the first threshold voltage may be selected, and a third threshold voltage less than the first threshold voltage may be selected.

[0049] In some embodiments, the voltage threshold prediction-based memory management component 113 may be configured to determine that a plurality of subsequent threshold voltages will be greater than the first threshold voltage when the determined number of bits is greater than a first threshold number of bits. As described herein, when a threshold voltage or a voltage to be selected as a threshold voltage is determined to be greater than the first threshold voltage, only offset voltages greater than the first threshold voltage may be used. In this way, offset voltages that may not be used to decode a set of memory cells can be avoided, which can save time and computational resources.

[0050] In some embodiments, the voltage threshold prediction-based memory management component 113 may be configured to determine that a plurality of subsequent threshold voltages are less than a first threshold voltage when the determined number of bits is less than a second threshold number of bits. Similarly, when a threshold voltage, or a voltage to be selected as a threshold voltage, is determined to be less than the first threshold voltage, only offset voltages less than the first threshold voltage may be used. In this way, offset voltages that might not be used to decode a set of memory cells can be avoided, saving time and computational resources.

[0051] In some embodiments, the voltage threshold-based memory management component 113 may be configured to perform only positive read offsets when the determined number of bits is greater than a first threshold number of bits and only negative read offsets when the determined number of bits is less than a second threshold number of bits. As used herein, a positive read offset may include a voltage change in a positive direction from a specific voltage (e.g., a voltage increase from a first voltage). Similarly, a negative read offset may include a voltage change in a negative direction from a specific voltage (e.g., a voltage decrease from a first voltage).

[0052] Figure 2This is a flowchart corresponding to method 221 for memory management based on voltage threshold prediction, according to some embodiments of this disclosure. Method 221 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 221 is performed by... Figure 1 The voltage threshold prediction-based memory management component 113 performs the operation. Although shown in a specific order or sequence, the order of the processes is modifiable unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0053] As described herein, a set of memory cells may be degraded or changed after time and / or use. In some embodiments, the threshold voltage used to decode a set of memory cells can be shifted to a different voltage through this degradation. When a set of memory cells is degraded or changed after a period of time, an error recovery operation can be utilized. In some methods, when the error recovery operation is initiated, multiple offset voltages are tested in both positive and negative directions to determine a voltage that can be used as the updated threshold voltage. As described herein, performing multiple reads using alternating positive and negative offset voltages can be time- and resource-intensive. Therefore, method 221 can use a single read operation to predict whether a positive or negative offset should be used. In this way, approximately half the process can be used to find the updated threshold voltage for a set of memory cells.

[0054] In operation 222, a first read operation involving a set of memory cells can be performed using a first voltage. In some embodiments, the first threshold voltage may be a threshold voltage defined for a set of memory cells by parameters or other settings. In some embodiments, the first threshold voltage may target a specific location or memory cell within the set of memory cells. In these embodiments, the predicted number of bits may be determined based on the specific location or memory cell targeted by the first threshold voltage. For example, the predicted number of bits may be the number of bits that should be read if the first threshold voltage targets the correct location or memory cell within the set of memory cells. In this example, the correct location or memory cell may be a location or memory cell defined by parameters of the set of memory cells utilizing the first threshold voltage.

[0055] In operation 223, the number of bits associated with a set of memory cells can be determined based on the first read operation. As described herein, the first read operation can be used to count or determine the number of bits in a set of memory cells. In some embodiments, the set of memory cells may include a first portion of memory cells that can be targeted by a voltage greater than a first threshold voltage and a second portion of memory cells that can be targeted by a voltage less than the first threshold voltage. In some embodiments, the first read operation may read either the first portion or the second portion of the memory cells. In this way, the number of bits determined by the first read operation can be used to identify whether the first threshold voltage should be increased or decreased by comparing the determined number of bits with a threshold number of bits.

[0056] In operation 224, when the number of bits is greater than a threshold number of bits for a set of memory cells, a second read operation involving a set of memory cells can be performed using a second voltage greater than a first voltage. In some embodiments, when the number of bits is greater than a threshold number of bits, a determination is made that the threshold voltage for a set of memory cells has been shifted to a voltage greater than the first voltage. In other words, the voltage used to target a read level for a set of memory cells may need to be greater than the first voltage. In these instances, the first voltage may be the voltage initially used to target a read level for a set of memory cells. In these instances, the threshold number of bits may be a specified number of bits exceeding the predicted number of bits for the read level of the read operation for a set of memory cells. That is, the threshold voltage for a set of memory cells can target a specific read level for a set of memory cells and includes a corresponding number of bits that can be read at the specific read level. A number of bits greater than the corresponding number of bits that can be read at the specific read level can indicate that the threshold voltage for a set of memory cells is greater than the first voltage. This can indicate that the threshold voltage for the memory cells has been shifted to a voltage more positive than the first voltage or that the first voltage targets cells in the negative direction of the set of memory cells.

[0057] As described herein, prior methods determine that a threshold voltage has shifted and use various offset voltages greater than the previous voltage and voltages less than the previous voltage to determine the voltage for decoding a set of memory cells and identify the voltage as an updated threshold voltage or threshold voltage for the set of memory cells. These prior methods can be more time-consuming and resource-intensive than predicting the offset direction of the threshold voltage based on the number of bits read at a specific read level of a set of memory cells. That is, in some embodiments, the predicted direction of the threshold voltage relative to the first voltage allows the memory management component 113 based on voltage threshold prediction to use either a positive offset or a negative offset instead of both.

[0058] In some embodiments, method 221 may include avoiding the use of a second voltage when the number of bits is less than a threshold number of bits for a set of memory cells. In some embodiments, avoiding the use of a second voltage when the number of bits is less than a threshold number of bits for a set of memory cells may include not using a voltage offset greater than the first voltage and / or the second voltage. That is, method 221 may include avoiding testing or utilizing an offset voltage greater than the first voltage when the number of bits is less than a threshold number of bits, and since the second voltage is greater than the first voltage in this example, method 221 may include avoiding the use of the second voltage.

[0059] In operation 226, when the number of bits is less than a threshold number of bits for a set of memory cells, a second read operation involving a set of memory cells can be performed using a third voltage less than the first voltage. As described herein, the threshold number of bits for a set of memory cells can be based on the read level of the first voltage, such that the number of read bits less than the threshold number of bits for a set of memory cells can indicate that the threshold voltage has moved to a voltage lower than the first voltage. In this way, method 221 can include the operation of performing a second read operation using a third voltage instead of a second voltage when the number of bits is less than the threshold number of bits used with the first voltage.

[0060] In some embodiments, method 221 may include operations that avoid using a third voltage when the number of bits is higher than a threshold number of bits for a set of memory cells. As described herein, method 221 may include determining whether the threshold voltage for a set of memory cells has increased or decreased based on the number of bits read using a first voltage. When the number of bits is higher than the threshold number of bits, method 221 may include operations that avoid using a third voltage less than the first voltage. Additionally, method 221 may include operations that avoid using a voltage less than the third voltage or a voltage between the first voltage and the third voltage. In this way, method 221 may utilize only a positive voltage offset from the first voltage when the threshold voltage is determined to be greater than the first voltage, and only a negative voltage offset when the threshold voltage is determined to be less than the first voltage.

[0061] In some embodiments, method 221 may include determining a threshold bit count of a set of memory cells based on a specific memory cell or subset of memory cells targeted by a first voltage. In these embodiments, the specific memory cell or subset of memory cells is a specific physical location within a set of memory cells. As described herein, the threshold bit count may be based on a specific first voltage and / or a specific physical location within a set of memory cells targeted by the first voltage. For example, the first voltage may represent a first read level targeting a first location within a set of memory cells. In this example, there may be a first plurality of read levels at corresponding locations that can be targeted by corresponding voltages greater than the first voltage. Additionally, there may be a second plurality of read levels at corresponding locations that can be targeted by corresponding voltages less than the first voltage. In this example, a read operation may read the first plurality of read levels, and the threshold bit count may be based on the number of bits present within the first plurality of read levels. In this way, the threshold bit count can be used to determine whether a voltage threshold is at the first voltage, whether the voltage threshold is shifted to a target voltage within the first plurality of read levels or the first plurality of read levels, or whether the voltage threshold is shifted to a target voltage within the second plurality of read levels or the first plurality of read levels. In this way, when the number of bits is less than the threshold number of bits, the first plurality of read levels can be used as the offset voltage of the target, and when the number of bits exceeds the threshold number of bits, the second plurality of read levels can be used as the offset voltage of the target.

[0062] In a non-limiting example, when a particular physical location is situated between a first portion comprising approximately 3 / 8 of the bits in a set of memory cells and a second portion comprising approximately 5 / 8 of the bits in a set of memory cells, the threshold bit count is 5 / 8 of the total number of bits. As described herein, the threshold bit count can be based on a particular physical location targeted by a first voltage. In this particular example, the particular location can be situated between a first portion comprising approximately 3 / 8 of the total number of bits in a set of memory cells and a second portion comprising approximately 5 / 8 of the total number of bits in a set of memory cells. In this manner, a read operation can be performed on the second portion of a set of memory cells to determine the number of bits in the set of memory cells. If the determined number of bits is greater than 5 / 8, then the threshold voltage has been moved toward the first portion, and if the determined number of bits is less than 5 / 8, then the threshold voltage has been moved toward the second portion. Therefore, depending on the determined direction of the threshold voltage, the offset voltage can be selected in a positive or negative direction based on the number of bits read during the read operation.

[0063] Figure 3This is a flowchart corresponding to a method 330 for memory management based on voltage threshold prediction, according to some embodiments of this disclosure. Method 330 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 330 is performed by… Figure 1 The voltage threshold memory management component 113 performs the process. Although shown in a specific order or sequence, the order of the processes is modifiable unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0064] As described herein, a set of memory cells may be degraded or changed after time and / or use. In some embodiments, the threshold voltage used to decode a set of memory cells can be shifted to a different voltage through this degradation. When a set of memory cells is degraded or changed after a period of time, an error recovery operation can be utilized. In some methods, when the error recovery operation is initiated, multiple offset voltages are tested in both positive and negative directions to determine a voltage that can be used as the updated threshold voltage. As described herein, performing multiple reads using alternating positive and negative offset voltages can be time- and resource-intensive. Therefore, method 330 can use a single read operation to predict whether a positive or negative offset should be used. In this way, approximately half the process can be used to find the updated threshold voltage for a set of memory cells.

[0065] In operation 331, a first single-level cell (SLC) read involving a set of memory cells can be performed using a first threshold voltage to target a specific memory cell within the set of memory cells. As described herein, the first SLC read can read a portion of the set of memory cells from a specific memory cell in a single direction. In some embodiments, the first SLC read can be used to determine the number of bits associated with a portion of the set of memory cells.

[0066] In operation 332, the number of bits in a set of memory cells can be determined based on a first SLC read using a first threshold voltage. As described herein, the first SLC read can be used to determine the number of bits associated with a set of memory cells and / or a specific portion of the set of memory cells. As described herein, the first threshold voltage can be a voltage defined by parameters of the set of memory cells. In some embodiments, the defined parameters may also include specific memory cells from the set of memory cells that are targeted when the first SLC read is performed using the first threshold voltage.

[0067] In some embodiments, the number of bits includes the number of bits at a physical location that is targeted by a positive offset of a particular memory cell targeted by a first threshold voltage. For example, the number of bits includes bits associated with cells from a group of memory cells targeted by the first threshold voltage and bits associated with cells in a particular direction such that the positive offset would target bits in that particular direction. As described herein, a particular memory cell targeted by the first threshold voltage may include a first proximate portion of the cell and a second proximate portion of the cell. In some embodiments, the number of bits may be associated with either the first proximate portion or the second proximate portion.

[0068] In operation 333, an upper bit count threshold and a lower bit count threshold for a set of memory cells can be determined based on a first threshold voltage. As described herein, the predicted number of bits to be read using the first threshold voltage can be used to determine the upper bit count threshold and the lower bit count threshold. In some embodiments, the upper bit count threshold can be an indicator of the number of bits whose first threshold voltage is lower than the threshold voltage of the decodeable set of memory cells, and the lower bit count threshold can be an indicator of the number of bits whose first threshold voltage is higher than the threshold voltage of the decodeable set of memory cells. In this way, the upper bit count threshold and the lower bit count threshold can be used to identify offsets in the threshold voltage of the decodeable set of memory cells and / or to identify offset voltages for testing subsequent read operations.

[0069] In operation 334, a set of SLC reads involving a set of memory cells can be performed using a set of threshold voltages, wherein the set of threshold voltages includes a set of positive offsets when the determined number of bits is greater than an upper limit bit count threshold; includes a set of negative offsets when the determined number of bits is less than a lower limit bit count threshold; or includes a combination of positive and negative offsets, or any combination thereof, when the determined number of bits is between the upper and lower limit bit count thresholds. As described herein, a set of positive offsets may be a set of threshold voltages greater than a first threshold voltage, and a set of negative offsets may be a set of threshold voltages less than a first threshold voltage.

[0070] In some embodiments, method 330 may include avoiding the use of negative offsets when the determined number of bits is greater than an upper limit bit count threshold. That is, when the determined number of bits is greater than the upper limit bit count threshold, a set of positive offsets will only include offset voltages greater than a first threshold voltage. In some embodiments, method 330 may include avoiding the use of positive offsets when the determined number of bits is less than a lower limit bit count threshold. That is, when the determined number of bits is less than the lower limit bit count threshold, a set of negative offsets will only include offset voltages less than a first threshold voltage.

[0071] In some embodiments, method 330 may include operations of changing an upper bit count threshold and a lower bit count threshold based on a specified read level. In these embodiments, the upper bit count threshold and the lower bit count threshold increase as the threshold voltage decreases, and decrease as the threshold voltage increases. As described herein, the upper bit count threshold and / or the lower bit count threshold may be determined based on a read level of a first threshold voltage. For example, the first threshold voltage may target a specific physical location or a specific memory cell within a set of memory cells. In this example, the upper bit count and / or the lower bit count may be based on the predicted number of bits to be read when the first threshold voltage is an acceptable threshold voltage for a set of memory cells. As used herein, an acceptable threshold voltage for a set of memory cells is generally referred to as a threshold voltage for a decodeable set of memory cells.

[0072] Figure 4 This section describes an example of voltage threshold prediction for a group of memory cells 440-1, 440-2, 440-3 according to some embodiments of the present disclosure. In some embodiments, a group of memory cells 440-1 may be described as having a first threshold voltage 443 capable of decoding a group of memory cells 440-1 at a specific location (e.g., cell 0). Although in Figure 4 The document describes multiple cells, but multiple additional memory cells can be added. For example, multiple memory cells 441-1 can be located on the negative side of cell 0, and multiple memory cells 442-2 can be located on the positive side of cell 0. As used herein, the negative side of cell 0 can indicate that a voltage lower than the first threshold voltage 443 will be used to target the cells on the negative side of cell 0. Similarly, the positive side of cell 0 can indicate that a voltage higher than the first threshold voltage 443 will be used to target the cells on the positive side of cell 0.

[0073] In some embodiments, a read operation may be performed using a first threshold voltage 443. In these embodiments, the read operation may be a single-level read operation for reading the positive side of cell 0. In this example, the read operation may determine the number of bits 444 associated with a set of memory cells 440-1. In some embodiments, the number of bits 444 may correspond to the correct number of bits when the first threshold voltage 443 is capable of decoding a set of memory cells 440-1. That is, the number of bits 444 may include the number of bits determined when a set of memory cells 440-1 is programmed and the first threshold voltage 443 targets the position of cell 0. In some embodiments, the number of bits 444 may be used to determine an upper threshold and / or a lower threshold of bits. As described herein, the threshold bit count may be used to identify the direction in which the first threshold voltage 443 has been shifted.

[0074] As described herein, a set of memory cells 440-1 may be degraded or changed after time and / or use. In some embodiments, a first threshold voltage 443 for decoding a set of memory cells 440-1 may be shifted to a different voltage through this degradation. In some embodiments, a set of memory cells 440-2 may represent a first degradation, and a set of memory cells 440-3 may represent a second degradation of a set of memory cells 440-1. A set of memory cells 440-2 and a set of memory cells 440-3 may comprise a set of identical or similar memory cells. For example, a set of memory cells 440-2 may include a plurality of additional memory cells 441-2 in the negative direction and a plurality of additional memory cells 442-2 in the positive direction. Similarly, a set of memory cells 440-3 may include a plurality of additional memory cells 441-3 in the negative direction and a plurality of additional memory cells 442-3 in the positive direction.

[0075] As illustrated by a set of memory cells 440-2, a first threshold voltage 443 has shifted from cell 0 to cell +2. This can occur over a period of time or during use, as described herein. In some embodiments, the first threshold voltage 443 can be used to perform a read operation on a set of memory cells 440-2. As described herein, the read operation can be used to determine the number of bits 446 in the set of memory cells 440-2. In some embodiments, the number of bits 446 may be less than the number of bits 444. In some embodiments, the number of bits 446 may be less than a determined lower threshold of bits, as described herein. In these embodiments, the number of bits 446 may include bit +2, multiple bits 442-2, and bits up to bit +N+N.

[0076] As described herein, the number of bits 446 will be less than the number of bits 444 from a set of memory cells 440-1. In this way, memory management components based on voltage threshold prediction (e.g., Figure 1 The memory management component 113 (or similar) based on voltage threshold prediction described herein can determine that the first threshold voltage 443 has moved in the positive direction and the threshold voltage is less than the first threshold voltage 443. For example, the first threshold voltage 443 may drop to a second threshold voltage 445. In this example, the lower limit of the second threshold voltage 445 may target cell 0 and cause a set of memory cells 440-2 to be decoded.

[0077] As illustrated by a set of memory cells 440-3, a first threshold voltage 443 has shifted from cell 0 to cell -2. This can occur over a period of time or during use, as described herein. In some embodiments, the first threshold voltage 443 can be used to perform a read operation on a set of memory cells 440-3. As described herein, the read operation can be used to determine the number of bits 448 in the set of memory cells 440-3. In some embodiments, the number of bits 448 may be greater than the number of bits 444. In some embodiments, the number of bits 448 may be greater than a determined upper limit threshold for bits, as described herein. In these embodiments, the number of bits 448 may include bit -2, multiple bits 442-3, and bits up to bit +N+N.

[0078] As described herein, the number of bits 448 will be greater than the number of bits 444 from a set of memory cells 440-1. In this way, memory management components based on voltage threshold prediction (e.g., Figure 1 The memory management component 113 (or similar) based on voltage threshold prediction described herein can determine that the first threshold voltage 443 has moved in the negative direction and that the threshold voltage will be greater than the first threshold voltage 443. For example, the first threshold voltage 443 can be increased to a third threshold voltage 447. In this example, a larger third threshold voltage 447 can target cell 0 and cause a set of memory cells 440-3 to be decoded.

[0079] Figure 5 This is a block diagram of an example computer system 500 in which embodiments of this disclosure may operate. For example, Figure 5 This describes an example machine of a computer system 500, in which a set of instructions for causing a machine to perform any or more of the methodologies discussed herein can be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the voltage threshold prediction-based memory management component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0080] A machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while individual machines have been described, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0081] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 518, which communicate with each other via a bus 530.

[0082] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or several processors implementing combinations of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0083] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which one or more sets of instructions 526 or software embodying any or more of the methodologies or functions described herein are stored. The instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage media. The machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0084] In one embodiment, instruction 526 includes a memory management component corresponding to voltage threshold prediction (e.g., Figure 1The machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methodologies of this disclosure. The term "machine-readable storage medium" should accordingly be considered as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0085] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, in this document and generally, considered to be self-consistent sequences of operations that lead to desired results. An operation is an operation that requires physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient, primarily for the sake of convention, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or similar terms.

[0086] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device, which manipulate or transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0087] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0088] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may be proven convenient to construct more specialized devices to implement the methods. The structures for various such systems will appear as described below. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure described herein.

[0089] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0090] In the foregoing description, embodiments thereof have been described with reference to specific examples of this disclosure. It should be understood that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of this disclosure set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory management method based on voltage threshold prediction, comprising: A first read operation involving a set of memory cells is performed using a first voltage; The number of bits associated with the group memory cell is determined based on the first read operation; Based on the execution of the first read operation and the number of bits associated with the group memory cell determined by the first read operation, predict the offset of the voltage threshold associated with the group memory cell, and; In response to determining that the number of bits is higher than a threshold number of bits for the group memory cell based on a predicted offset of the voltage associated with the group memory cell, a second read operation involving the group memory cell is performed using a second voltage greater than the first voltage; and In response to the prediction of the number of bits being less than the threshold number of bits of the group memory cell based on the voltage associated with the group memory cell, a second read operation involving the group memory cell is performed using a third voltage less than the first voltage.

2. The method of claim 1, further comprising avoiding the use of the second voltage in response to determining that the number of bits is lower than the threshold number of bits of the group of memory cells.

3. The method of claim 1, further comprising avoiding the use of the third voltage in response to determining that the number of bits is higher than the threshold number of bits of the group of memory cells.

4. The method according to any one of claims 1 to 3, wherein the group memory cell comprises word lines of a NAND memory device.

5. The method according to any one of claims 1 to 3, comprising: The number of threshold bits of the group of memory cells is determined based on a specific memory cell or subset of memory cells targeted by the first voltage, wherein the specific memory cell or subset of memory cells is a specific physical location within the group of memory cells.

6. The method of claim 5, wherein in response to determining that the particular physical location is located between a first portion of approximately 3 / 8 of the bits of the group memory cell and a second portion of approximately 5 / 8 of the bits of the group memory cell, the threshold number of bits is 5 / 8 of the number of bits.

7. A device for memory management based on voltage threshold prediction, comprising: Voltage threshold prediction component, configured to: A first read operation involving the group of memory cells is performed using a first threshold voltage that targets a specific memory cell from a group of memory cells. The number of bits in the group memory cell is determined based on the first read operation using the first threshold voltage; The number of first threshold bits of the group memory cells is determined based on the first threshold voltage; The number of second threshold bits of the group memory cells is determined based on the first threshold voltage; Based on the execution of the first read operation using the first threshold voltage that targets the specific memory cell from the group of memory cells, the offset of the voltage threshold associated with the group of memory cells is predicted; A second threshold voltage to be used for the second read operation is determined based on a comparison between the determined number of bits and the first threshold number of bits and the second threshold number of bits, and based on a predicted offset of the voltage associated with the group memory cell obtained from the execution of the first read operation using the first threshold voltage. and The second read operation is performed using the second threshold voltage.

8. The device of claim 7, wherein when the determined number of bits is greater than the first threshold number of bits, the second threshold voltage is greater than the first threshold voltage.

9. The device of claim 7, wherein when the determined number of bits is less than the second threshold number of bits, the second threshold voltage is less than the first threshold voltage.

10. The device according to any one of claims 7 to 9, wherein the voltage threshold prediction component is configured to perform the second read operation using a second threshold voltage greater than the first threshold voltage and to perform the third read operation using a third threshold voltage less than the first threshold voltage when the determined number of bits is between the first threshold number of bits and the second threshold number of bits.

11. The device according to any one of claims 7 to 9, wherein the voltage threshold prediction component is configured to determine that a plurality of subsequent threshold voltages are greater than the first threshold voltage when the determined number of bits is greater than the first threshold number of bits.

12. The device according to any one of claims 7 to 9, wherein the voltage threshold prediction component is configured to determine that a plurality of subsequent threshold voltages are less than the first threshold voltage when the determined number of bits is less than the second threshold number of bits.

13. The device according to any one of claims 7 to 9, wherein the voltage threshold prediction component is configured to perform only a positive read offset when the determined number of bits is greater than the first threshold number of bits and only a negative read offset when the determined number of bits is less than the second threshold number of bits.

14. A system for memory management based on voltage threshold prediction, comprising: Multiple memory components arranged to form a stacked cross-grid array of interleaved NAND memory cells; and A processing device coupled to the plurality of memory components, the processing device being configured to perform operations including: A first single-level cell SLC read involving a group of memory cells is performed using a first threshold voltage to target a specific memory cell in the group of memory cells. The number of bits in the group of memory cells is determined based on the first single-level cell SLC read using the first threshold voltage; The upper limit bit count threshold and the lower limit bit count threshold of the group of memory cells are determined based on the first threshold voltage. Based on performing the first single-level cell SLC involving the group memory cell using the first threshold voltage, predict the offset of the voltage threshold associated with the group memory cell; Based on a predicted offset of the voltage threshold associated with the group memory cell determined by performing the first single-level cell (SLC) involving the group memory cell using the first threshold voltage, a first set of SLC reads involving the group memory cell is performed using a first set of threshold voltages, wherein the set of threshold voltages: When the determined number of bits is greater than the upper limit bit count threshold, a set of positive offsets is included; When the determined number of bits is less than the lower limit bit count threshold, a set of negative offsets is included; or When the determined number of bits is between the upper limit bit count threshold and the lower limit bit count threshold, it includes a combination of positive and negative offsets, or any combination thereof.

15. The system of claim 14, wherein the processing means is used to avoid using negative offsets when the determined number of bits is greater than the upper limit bit count threshold.

16. The system of claim 14, wherein the processing means is used to avoid using a positive offset when the determined number of bits is less than the lower bit count threshold.

17. The system according to any one of claims 14 to 16, wherein the group memory cell comprises a single word line of a NAND memory cell.

18. The system according to any one of claims 14 to 16, wherein the processing means is configured to change the upper limit bit count threshold and the lower limit bit count threshold based on a specified read level.

19. The system of claim 18, wherein the upper limit counting threshold and the lower limit counting threshold increase when the first threshold voltage decreases to the second threshold voltage, and the upper limit counting threshold and the lower limit counting threshold decrease when the first threshold voltage increases to the third threshold voltage.

20. The system according to any one of claims 14 to 16, wherein the number of bits includes the number of bits at a physical location targeted by the positive offset of the particular memory cell targeted by the first set of threshold voltages.

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