A semiconductor device and a method of manufacturing the same

Abstract

This invention discloses a semiconductor device and its fabrication method. The method includes: sequentially stacking a silicon layer, a metal layer, and a hard mask layer on a substrate where an active region and word lines have been formed to form a stacked layer; removing the stacked layer except for the areas where bit lines and memory node contact regions need to be formed, and filling the removed areas with an insulating material, wherein the memory node contact regions are the areas where the active region needs to contact the memory node; removing the hard mask layer of the memory node contact regions to form pad holes, and filling the pad holes with a metal material to form landing pads.

Description

Technical Field

[0001] This invention relates to the field of semiconductor contacts, and more particularly to a semiconductor device and its fabrication method. Background Technology

[0002] Memory typically includes capacitors and transistors. The capacitors store data, and the transistors control access to the data stored in the capacitors. Specifically, the word line of the memory is connected to the gate of the transistor, and the word line controls the switching of the transistor. The source of the transistor is connected to the bit line to form a current transmission path. Simultaneously, the drain of the transistor is connected to the capacitor to achieve data storage or output. When connecting the memory node contact area to the memory capacitor, a memory node contact is typically formed on the memory node contact area to establish an electrical connection between the memory node contact area and the memory capacitor.

[0003] However, current memory fabrication methods are quite cumbersome, and the poor quality of the contacts in the fabricated memory nodes will greatly affect the quality of the resulting memory. Summary of the Invention

[0004] This application provides a semiconductor device and a fabrication method that solves the technical problems of cumbersome fabrication methods and poor quality of contacts in existing memory technologies. It simplifies the memory fabrication process and improves the contact resistance of memory nodes, thereby increasing production efficiency and improving product quality.

[0005] Firstly, this application provides the following technical solution through an embodiment of the application:

[0006] A method for fabricating a semiconductor device, comprising:

[0007] A silicon layer, a metal layer, and a hard mask layer are sequentially stacked on a substrate where active regions and word lines have been formed to form a stacked layer.

[0008] Remove the superimposed layer outside the area where the bit line and memory node contact area need to be formed, and fill the removed area with insulating material, wherein the memory node contact area is the area where the active region needs to contact the memory node;

[0009] The hard mask layer of the storage node contact area is removed to form pad holes, and the pad holes are filled with metal material to form landing pads.

[0010] Optionally, the step of sequentially stacking a silicon layer, a metal layer, and a hard mask layer on the substrate where the active region and word line have been formed includes:

[0011] A metal barrier layer and a metal thin film are sequentially stacked on the silicon layer to form the metal layer.

[0012] Optionally, the metal barrier layer is titanium or a nickel-titanium alloy.

[0013] Optionally, the metal film is tungsten metal.

[0014] Optionally, removing the overlay layer outside the contact area between the bit line and the memory node, and filling the removed area with insulating material, includes:

[0015] The superimposed layer is etched to form multiple linear regions and trenches, and the trenches are filled with a first insulating material to isolate the multiple linear regions; wherein the multiple linear regions correspond to a first linear region of a bit line region and a second linear region of a memory node contact region, and the first linear region and the second linear region are parallel to each other;

[0016] The second linear region is etched to form an insulating hole, and the insulating hole is filled with a second insulating material. Optionally, the first insulating material is a material with a low dielectric constant.

[0017] Optionally, the low dielectric constant material includes at least one material selected from SiCN, SiCNH, SiCO, and SiCOH, or a combination of multiple materials.

[0018] Optionally, the second insulating material is silicon nitride; the metal material is tungsten metal.

[0019] Optionally, the area of ​​the active region that needs to contact the storage node is the area of ​​the drain electrode of the transistor in the active region.

[0020] Secondly, this application provides the following technical solution through one embodiment:

[0021] A semiconductor device, wherein the semiconductor device is a dynamic random access memory, comprising:

[0022] A substrate having a plurality of spaced-apart active regions formed thereon;

[0023] Parallel word lines are located within the substrate and intersect and connect with the active region;

[0024] Parallel bit lines are located on the substrate and connected to the active region;

[0025] A capacitor structure and a spaced-out pad structure, wherein the pad structure connects the active region to the capacitor structure;

[0026] The pad structure is surrounded by a first insulating material and the adjacent bit lines are filled with a first insulating material; the parallel bit lines include a silicon layer and a metal layer, and there is a capping layer on the parallel bit lines; the pad structure includes a silicon layer, a first metal layer and a second metal layer.

[0027] Optionally, there are insulating holes between adjacent pad structures; the insulating holes have a structure that is larger at the top and smaller at the bottom, and are filled with a second insulating material.

[0028] Optionally, the second metal layer has a structure that is larger on top and smaller on the bottom.

[0029] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0030] The semiconductor device and fabrication method provided in this application include: sequentially stacking a silicon layer, a metal layer, and a hard mask layer on a substrate with an active region and word lines to form a stacked layer; removing the stacked layer except for the area where bit lines and memory node contact regions need to be formed, and filling the removed area with insulating material, wherein the memory node contact region is the area where the active region needs to contact the memory node; bit lines and memory node contacts can be formed simultaneously, simplifying the process of forming bit lines and memory node contacts, and thus enabling rapid formation of bit lines and memory node contacts. Removing the hard mask layer in the memory node contact region to form pad holes, and filling the pad holes with metal material to form landing pads, allows for the fabrication of memory node contacts with a larger cross-sectional area, resulting in lower resistance and improved memory node quality. Therefore, this method solves the technical problems of cumbersome memory fabrication methods and poor quality of fabricated memory node contacts in the prior art, achieving a simplified memory fabrication process and improving the technical effect of memory node contact resistance, thereby improving production efficiency and product quality. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a flowchart of the semiconductor device fabrication method in the embodiments of this application;

[0033] Figure 2 This is a top perspective view of the substrate in an embodiment of this application;

[0034] Figure 3 This is a process illustration of the semiconductor device fabrication method in the embodiments of this application. Figure 1 ;

[0035] Figure 4 This is a process illustration of the semiconductor device fabrication method in the embodiments of this application. Figure 2 ;

[0036] Figure 5 This is a process illustration of the semiconductor device fabrication method in the embodiments of this application. Figure 2 A sectional view along the AB direction;

[0037] Figure 6 This is a process illustration of the semiconductor device fabrication method in the embodiments of this application. Figure 3 ;

[0038] Figure 7 This is a process illustration of the semiconductor device fabrication method in the embodiments of this application. Figure 3 A sectional view along the CD direction;

[0039] Figure 8 This is a process illustration of the semiconductor device fabrication method in the embodiments of this application. Figure 4 ;

[0040] Figure 9 This is a process illustration of the semiconductor device fabrication method in the embodiments of this application. Figure 4 A sectional view along the AB direction;

[0041] Figure 10 This is a structural diagram of the semiconductor device in the embodiments of this application. Detailed Implementation

[0042] This application provides a semiconductor device and a fabrication method that solves the technical problems of cumbersome fabrication methods and poor quality of contacts in existing memory technologies. It simplifies the memory fabrication process and improves the contact resistance of memory nodes, thereby increasing production efficiency and improving product quality.

[0043] The technical solution of this application embodiment is to solve the above-mentioned technical problems, and the general idea is as follows:

[0044] This application provides a method for fabricating a semiconductor device, comprising: sequentially stacking a silicon layer, a metal layer, and a hard mask layer on a substrate on which active regions and word lines have been formed to form a stacked layer; removing the stacked layer except for the areas where bit lines and memory node contact regions need to be formed, and filling the removed areas with an insulating material, wherein the memory node contact regions are the areas where the active regions need to contact the memory nodes; removing the hard mask layer of the memory node contact regions to form pad holes, and filling the pad holes with a metal material to form landing pads.

[0045] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0046] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0047] In this embodiment, a method for fabricating a semiconductor device is provided, such as... Figure 1 As shown, it includes:

[0048] Step S101: On the substrate where the active region and word line have been formed, a silicon layer, a metal layer and a hard mask layer are sequentially stacked to form a stacked layer.

[0049] Step S102: Remove the superimposed layer outside the contact area between the bit line and the storage node, and fill the removed area with insulating material, wherein the contact area between the storage node and the active region is the area where the active region needs to contact the storage node.

[0050] Step S103: Remove the hard mask layer of the contact area of ​​the storage node to form pad holes, and fill the pad holes with metal material to form landing pads.

[0051] Specifically, the semiconductor device is DRAM (Dynamic Random Access Memory), typically arranged in a two-dimensional matrix with a capacitor and a transistor as each unit. Word lines are connected to the gates of the transistors, controlling their switching; the sources of the transistors are connected to bit lines to form current transmission paths; and the drains of the transistors are connected to the capacitors to achieve data storage or output. Of course, the semiconductor device also includes circuitry or memory chips incorporating DRAM.

[0052] Below, in conjunction with Figures 2-9 This embodiment provides a detailed description of the fabrication method for the semiconductor device.

[0053] First, such as Figure 2 As shown, a substrate 100 is prepared, in which a plurality of active regions 110 are formed, and word line structures 150 are formed on the substrate 100. Optionally, the substrate 100 is a glass substrate or other insulating dielectric substrate. For example, the substrate 100 can be a silicon substrate or a germanium substrate, etc., without limitation, and not listed one by one.

[0054] Then, as Figure 3 As shown, a silicon layer 120, a metal layer 130, and a hard mask layer 140 are sequentially stacked on a substrate 100 where the active region 110 and word line 150 have been formed, to form a stacked layer 200. Specifically, the silicon layer 120 and the hard mask layer 140 can be formed using processes such as epitaxy, electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering, and are not limited thereto. The metal layer 130 includes a metal barrier layer and a metal thin film, and can be formed in two steps. First, the metal barrier layer is formed using processes such as electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering, and then the metal thin film is formed using a thin film deposition process.

[0055] In optional embodiments, the metal barrier layer can be titanium nitride, titanium metal, or a nickel-titanium alloy, and the metal thin film can be tungsten metal. The material of the hard mask layer 140 can be at least one material or a combination of multiple materials including SiN and SiO2, to facilitate formation using existing semiconductor fabrication processes and reduce process difficulty. Of course, the material of the hard mask layer 140 can also be other inorganic materials, which are not limited here and will not be listed one by one.

[0056] Next, the superimposed layer outside the bit line and memory node contact area is removed, and the removed area is filled with insulating material, wherein the memory node contact area is the area where the active region needs to contact the memory node. In a specific implementation, the area where the active region needs to contact the memory node is the area of ​​the drain electrode of the transistor in the active region, so that the capacitor subsequently fabricated on the memory node contact is electrically connected to the drain electrode of the transistor in the active region.

[0057] Specifically, the superimposed layer is first etched to form multiple linear regions and trenches. A first insulating material is then filled into the trenches 220 to isolate the multiple linear regions. These linear regions correspond to a first linear region 230 in the bitline region and a second linear region 210 in the memory node contact region, with the first linear region 230 and the second linear region 210 being parallel to each other. Next, the second linear region 210 is etched to form an insulating hole 311, which is then filled with a second insulating material.

[0058] In the specific implementation process, such as Figure 4 , Figure 5 , Figure 6 and Figure 7As shown. First, the superimposed layer outside the first linear region 230 where the bit line needs to be formed and the second linear region 210 where the memory node contacts are located is removed by an etching process to form a trench 220. The unetched areas retained during the formation of the trench 220 include two parts: one is the first linear region 230, below which the sources of the transistors in the active region are arranged in a linear fashion; the other is the second linear region 210, below which the drains of the transistors in the active region are arranged in a linear fashion. Next, the first insulating material is filled by a chemical vapor deposition or physical vapor deposition process to insulate and isolate the first linear region 230 from the second linear region 210, thereby forming the bit line and the linear region where the memory node contacts need to be formed. Then, the first insulating material deposited on the surface of the unfilled area is removed by grinding and polishing, specifically by a CMP (Chemical Mechanical Polishing) process. Next, the superimposed layer in the second linear region 210, excluding the area where the memory node contact region needs to be formed, is removed by etching, grinding, or a combination of both to form an insulating via 311. Then, the second insulating material is filled using chemical vapor deposition or physical vapor deposition to insulatingly isolate the linearly arranged memory node contacts, forming the memory node contact area. Alternatively, electron beam evaporation, pulsed laser deposition, atomic layer deposition, or magnetron sputtering can also be used to fill the second insulating material; these methods are not limited here and will not be listed exhaustively. Finally, the second insulating material deposited on the surface of the unfilled area is removed by grinding and polishing, specifically by a CMP process.

[0059] In an optional embodiment, the first insulating material can be a material with a low dielectric constant, which can reduce the leakage current of the semiconductor device, reduce the capacitance effect between the wires, and reduce the heat generation of the semiconductor device. The material with a low dielectric constant includes at least one or a combination of materials selected from SiCN, SiCNH, SiCO, and SiCOH, and is not limited thereto, nor is it listed exhaustively.

[0060] In an optional embodiment, the second insulating material is silicon nitride. Silicon nitride has excellent insulation and electrical breakdown resistance, and it is also resistant to oxidation at high temperatures and thermal shock, enabling semiconductor devices to maintain good performance under high and low temperature environments. Of course, the second insulating material can also be other ceramic structural materials, such as ceramic substrates, glass-ceramic substrates, or resin substrates, etc., which are not limited here and will not be listed one by one.

[0061] Next, such as Figure 8 and Figure 9 As shown, the hard mask layer 320 of the storage node contact area is removed, and the removed area 321 is filled with metal material.

[0062] In the specific implementation process, the hard mask layer 320 of the memory node contact area is first removed by etching to form a pit. Then, the metal material is filled by chemical vapor deposition or physical vapor deposition to form the memory node contact. Of course, the second insulating material can also be filled by electron beam evaporation, pulsed laser deposition, atomic layer deposition, or magnetron sputtering, etc., without limitation or enumeration. Finally, the metal material deposited on the surface of the unfilled area is removed by grinding and polishing, specifically by CMP process.

[0063] In an optional embodiment, the metal material is tungsten. Tungsten has an extremely high melting point and great hardness, providing a stable base for the capacitor formed on the tungsten metal, thereby improving the lifespan of the semiconductor device. Of course, the metal material can also be one or a combination of conductive metals selected from silver, copper, gold, aluminum, and iron; no limitation is imposed, nor are they listed here.

[0064] In this embodiment, a semiconductor device is also provided, such as... Figure 10 As shown, the semiconductor device is a dynamic random access memory, including:

[0065] Substrate 100, wherein a plurality of active regions 110 are arranged at intervals;

[0066] Parallel word lines 150 are located within the substrate 100 and intersect and connect with the active region 110;

[0067] Parallel bit line 230 is located on substrate 100 and connected to active region 110;

[0068] The capacitor structure 160 and the spaced pad structure 210, wherein the pad structure 210 connects the active region 110 and the capacitor structure 160.

[0069] The pad structure 210 is surrounded by a first insulating material 220 and the adjacent bit lines 230 are filled with a first insulating material 220. The parallel bit lines 230 include a silicon layer 120 and a metal layer 130, and a capping layer 140 is provided on the parallel bit lines. The pad structure includes a silicon layer 170, a first metal layer 180 and a second metal layer 190.

[0070] Optionally, there are insulating holes between adjacent pad structures; the insulating holes have a structure that is larger at the top and smaller at the bottom, and are filled with a second insulating material.

[0071] Optionally, the second metal layer has a 190° top-large and bottom-small structure.

[0072] The technical solutions described in the embodiments of this application have at least the following technical effects or advantages:

[0073] The semiconductor device and fabrication method provided in this application include: sequentially stacking a silicon layer, a metal layer, and a hard mask layer on a substrate with an active region and word lines to form a stacked layer; removing the stacked layer except for the area where bit lines and memory node contact regions need to be formed, and filling the removed area with insulating material, wherein the memory node contact region is the area where the active region needs to contact the memory node; bit lines and memory node contacts can be formed simultaneously, simplifying the process of forming bit lines and memory node contacts, and thus enabling rapid formation of bit lines and memory node contacts. Removing the hard mask layer in the memory node contact region to form pad holes, and filling the pad holes with metal material to form landing pads, allows for the fabrication of memory node contacts with a larger cross-sectional area, resulting in lower resistance and improved memory node quality. Therefore, this method solves the technical problems of cumbersome memory fabrication methods and poor quality of fabricated memory node contacts in the prior art, achieving a simplified memory fabrication process and improving the technical effect of memory node contact resistance, thereby improving production efficiency and product quality.

[0074] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0075] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A silicon layer, a metal layer, and a hard mask layer are sequentially stacked on a substrate where active regions and word lines have been formed to form a stacked layer. Remove the superimposed layer outside the area where the bit line and memory node contact area need to be formed, and fill the removed area with insulating material, wherein the memory node contact area is the area where the active region needs to contact the memory node; The hard mask layer of the storage node contact area is removed to form pad holes, and the pad holes are filled with metal material to form landing pads.

2. The method as described in claim 1, characterized in that, The process of sequentially stacking a silicon layer, a metal layer, and a hard mask layer on a substrate where active regions and word lines have already been formed includes: A metal barrier layer and a metal thin film are sequentially stacked on the silicon layer to form the metal layer.

3. The method as described in claim 2, characterized in that, The metal barrier layer is made of titanium or a nickel-titanium alloy.

4. The method as described in claim 2, characterized in that, The metal film is tungsten metal.

5. The method as described in claim 1, characterized in that, The removal of the superimposed layer outside the contact area between the bit line and the memory node, and the filling of the removed area with insulating material, includes: The superimposed layer is etched to form multiple linear regions and trenches, and the trenches are filled with a first insulating material to isolate the multiple linear regions; wherein the multiple linear regions correspond to a first linear region of a bit line region and a second linear region of a memory node contact region, and the first linear region and the second linear region are parallel to each other; The second linear region is etched to form an insulating hole, and the insulating hole is filled with a second insulating material.

6. The method as described in claim 5, characterized in that, The first insulating material is a material with a low dielectric constant.

7. The method as described in claim 6, characterized in that, The low dielectric constant material includes at least one material selected from SiCN, SiCNH, SiCO, and SiCOH, or a combination of multiple materials.

8. The method as described in claim 5, characterized in that, The second insulating material is silicon nitride; the metal material is tungsten metal.

9. The method as described in claim 1, characterized in that, The area of ​​the active region that needs to contact the storage node is the area of ​​the drain electrode of the transistor in the active region.

10. A semiconductor device, characterized in that, The semiconductor device is prepared by the method for preparing a semiconductor device according to any one of claims 1 to 9, and the semiconductor device is a dynamic random access memory, comprising: A substrate having a plurality of spaced-apart active regions formed thereon; Parallel word lines are located within the substrate and intersect and connect with the active region; Parallel bit lines are located on the substrate and connected to the active region; A capacitor structure and a spaced-out pad structure, wherein the pad structure connects the active region to the capacitor structure; The pad structure is surrounded by a first insulating material and the adjacent bit lines are filled with a first insulating material; the parallel bit lines include a silicon layer and a metal layer, and there is a capping layer on the parallel bit lines; the pad structure includes a silicon layer, a first metal layer and a second metal layer.

11. The semiconductor device as claimed in claim 10, characterized in that, include: There are insulating holes between adjacent pad structures; The insulating hole has a structure that is larger at the top and smaller at the bottom, and is filled with a second insulating material.

12. The semiconductor device as claimed in claim 10, characterized in that, The second metal layer has a structure that is larger on top and smaller on the bottom.

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