Semiconductor memory structure

Abstract

A semiconductor memory structure includes a semiconductor substrate, a bit line disposed on the semiconductor substrate, and a capacitor contact disposed on one side of the bit line. The capacitor contact includes a semiconductor plug disposed on the semiconductor substrate, a metal plug disposed on the semiconductor plug, a metal silicide liner extending along the sidewall and bottom of the metal plug, and a nitride layer disposed on the metal silicide liner. The top surface of the metal silicide liner is lower than the top surface of the metal plug. The nitride layer surrounds the top of the metal plug.

Description

Technical Field

[0001] The invention relates to a semiconductor memory structure, and in particular to a dynamic random access memory contact structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) devices are widely used in consumer electronic products. In order to increase the device density within the DRAM device and improve its overall performance, the current DRAM device manufacturing technology continues to strive towards miniaturization of device size.

[0003] However, as device size continues to shrink, many challenges arise. For example, in the semiconductor manufacturing process, due to the small contact area between the semiconductor plug and the metal plug, a larger capacitance value is generated between the bit lines. Currently, the industry is still working hard to improve the manufacturing method of dynamic random access memory devices to overcome the problems caused by the shrinking device size. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor memory structure, comprising a semiconductor substrate, a bit line disposed on the semiconductor substrate, and a capacitor contact disposed on one side of the bit line. The capacitor contact comprises a semiconductor plug disposed on the semiconductor substrate, a metal plug disposed on the semiconductor plug, a metal silicide liner extending along the sidewall and bottom of the metal plug, and a nitride layer disposed on the metal silicide liner. The top surface of the metal silicide liner is lower than the top surface of the metal plug. The nitride layer surrounds the top of the metal plug.

[0005] The embodiment of the present invention can reduce the resistance of the capacitor contact and the capacitance value of the bit line by extending the metal silicide liner to the sidewalls of both sides of the metal plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the features and advantages of the present invention more clearly understood, different embodiments are specifically described below with reference to the accompanying drawings as follows:

[0007] Figure 1 FIG. 4 is a schematic top view of a semiconductor memory structure according to some embodiments of the present invention.

[0008] Figure 2-Figure 11 Schematic diagrams of cross-sections of forming a semiconductor memory structure at different stages according to some embodiments of the present invention are shown.

[0009] Fig.12 FIG. 4 is a schematic top view of a semiconductor memory structure according to some embodiments of the present invention.

[0010] Figure 13-14 FIG. 4 is a cross-sectional view of a semiconductor memory structure at different stages according to another embodiment of the present invention.

[0011] Fig.15 FIG. 4 is a schematic top view of a semiconductor memory structure according to some embodiments of the present invention.

[0012] Figure 16-Figure 18 FIG. 4 is a cross-sectional view of a semiconductor memory structure at different stages according to another embodiment of the present invention.

[0013] 100:Semiconductor memory structure

[0014] 102:Semiconductor substrate

[0015] 102A: Active Zone

[0016] 102B: Quarantine Area

[0017] 104: Isolation components

[0018] 1041: Isolation liner

[0019] 1042: Isolation filler

[0020] 106: Word Line

[0021] 108: Bit line contact

[0022] 109: Spacer

[0023] 110: Covering layer

[0024] 112: Oxide layer

[0025] 114: Nitride layer

[0026] 120: bit line

[0027] 122,123: Conductive layer

[0028] 121,124,125: Dielectric layer

[0029] 130: Dielectric liner

[0030] 131: Nitride liner

[0031] 132: Oxide liner

[0032] 133: Nitride liner

[0033] 140: Capacitor contact

[0034] 141,141',141":Semiconductor materials

[0035] 142:Semiconductor plug

[0036] 1420: Notch

[0037] 143: Nitride material layer

[0038] 144: Nitride layer

[0039] 146: Metal silicide liner

[0040] 147: Adhesion layer

[0041] 148:Metal plug

[0042] 150: Protective layer

[0043] 152: Dielectric layer

[0044] 154: Conductive barrier layer

[0045] 160: Capacitor structure

[0046] 162: Electrode layer

[0047] 164: Dielectric layer

[0048] 166: Electrode layer

[0049] D1,D2,D3,Z: Direction

[0050] W N ,W N1 ,W N2 ,W M ,W M1 ,W M2 ,W S :width DETAILED DESCRIPTION

[0051] Figure 1 FIG. 1 is a schematic top view of a semiconductor memory structure 100 according to some embodiments of the present invention. In some embodiments, the semiconductor memory structure 100 is a portion of a dynamic random access memory (DRAM) array. In some embodiments, the semiconductor memory structure 100 includes a semiconductor substrate 102, a word line 106, a bit line contact 108, a bit line 120, a dielectric liner 130, and a capacitor contact 140.

[0052] The semiconductor substrate 102 includes an active region 102A and an isolation region 102B surrounding the active region 102A. The dielectric liner 130 includes a pair of nitride liners 131 and 133 and an oxide liner 132 sandwiched between the pair of nitride liners 131 and 133. The capacitor contact 140 includes a metal plug 144 and an adhesion layer 147 and a nitride layer 148 surrounding the metal plug 144. It should be noted that Figure 1 The top view shown only shows part of the device.

[0053] In this embodiment, the word line 106 extends along a first direction D1, the bit line 120 extends along a second direction D2, and the active region 102A extends along a third direction D3. In this embodiment, the first direction D1 is perpendicular to the second direction D2, and the third direction D3 (i.e., the extension direction of the active region 102A) is at an angle of about 10-40° to the second direction D2, such as 20°, to improve the integration of the device.

[0054] It should be noted that Figure 1 Only some of the DRAM devices are shown to simplify the diagram. Figure 2 The cross-sectional schematic diagram shown by the section line AA′ (a plane formed by the first direction D1 and the height direction Z) is used to facilitate explanation of the method for forming a semiconductor memory structure.

[0055] Figure 2-Figure 11 1 is a schematic cross-sectional view of a semiconductor memory structure 100 at different stages of forming the semiconductor memory structure 100 according to some embodiments of the present invention.

[0056] like Figure 2 As shown, a semiconductor substrate 102 is provided. In some embodiments, the semiconductor substrate 102 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate.

[0057] exist Figure 2 In the embodiment, the semiconductor substrate 102 includes active regions 102A and isolation regions 102B, which are alternately arranged.

[0058] exist Figure 2 In the embodiment, an isolation component 104 is disposed in an isolation region 102B of a semiconductor substrate 102 , and includes an isolation liner 1041 and an isolation filler 1042 .

[0059] In some embodiments, the isolation liner 1041 and the isolation filler 1042 may include nitride or oxide, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination thereof. The formation of the isolation liner 1041 and the isolation filler 1042 may include a patterning process, a deposition process, and a planarization process.

[0060] In some embodiments, a word line (not shown) is buried in the active region of the semiconductor substrate. In some embodiments, the word line serves as a gate and includes a gate dielectric layer, a gate liner, and a gate electrode (not shown). Figure 1 The word line 106 in FIG. 1 extends along the first direction D1, and the section line AA' does not contact the word line 106. Figure 2 There is no word line in the picture.

[0061] exist Figure 2 In the embodiment, the bit line contact 108 is partially buried in the active region 102A of the semiconductor substrate 102 to facilitate subsequent electrical connection with the bit line 120. In some embodiments, spacers 109 are disposed on both sides of the bit line contact 108 to prevent the bit line contact from being connected to the subsequently formed capacitor contact and forming a short circuit.

[0062] In some embodiments, the bit line contact 108 is a conductive material including doped polysilicon, metal, or metal nitride, etc. In some embodiments, the formation of the bit line contact 108 includes using the aforementioned deposition process and patterning process, which will not be described in detail herein.

[0063] In some embodiments, the bit line contact 108 is polysilicon with dopants to reduce the contact resistance with the subsequently formed bit line. The dopants may include n-type or p-type dopants, such as nitrogen, arsenic, phosphorus, antimony ions or boron, aluminum, gallium, indium, boron trifluoride (BF 3+ ).

[0064] In some embodiments, the spacer 109 is a dielectric material including a nitride, such as silicon nitride. In some embodiments, the formation of the spacer 109 includes using the aforementioned deposition process and etching process, which will not be described in detail herein.

[0065] Please continue to refer to Figure 2 The cap layer 110 is formed on the semiconductor substrate 102 to protect the devices in the semiconductor substrate from being damaged by subsequent manufacturing processes. In some embodiments, the cap layer 110 includes an oxide layer 112 and a nitride layer 114.

[0066] In some embodiments, the oxide layer 112 includes a silicon oxide layer formed from tetraethylorthosilicate (TEOS). In some embodiments, the nitride layer 114 includes silicon nitride (SiN) or silicon oxynitride (SiON). In some embodiments, the oxide layer 112 and the nitride layer 114 can be formed sequentially by the deposition process described above.

[0067] Then, if Figure 2As shown, forming the bit line 120 on the semiconductor substrate 102 also includes forming the bit line 120 on the bit line contact 108. In some embodiments, the bit line 120 on the bit line contact 108 includes conductive layers 122 and 123 on the bit line contact 108, and dielectric layers 124 and 125 on the conductive layers 122 and 123. The bit line 120 on the isolation member 104 includes a dielectric layer 121 on the cap layer 110, conductive layers 122 and 123 on the dielectric layer 121, and dielectric layers 124 and 125 on the conductive layers 122 and 123. The uppermost dielectric layers 144 and 145 can protect the underlying film layers (e.g., the conductive layers 122 and 123) from being damaged in subsequent manufacturing processes.

[0068] In some embodiments, the conductive layers 122 and 123 include doped polysilicon, metal, or metal nitride, such as tungsten (W), titanium (Ti), and titanium nitride (TiN). In some embodiments, the dielectric layers 121, 124, and 125 include nitride or oxide, such as silicon nitride or silicon oxide.

[0069] In some embodiments, the formation of the bit line 120 includes the deposition process and the patterning process as described above, and thus will not be described in detail herein.

[0070] Then, if Figure 2 As shown, the dielectric liner 130 is formed on both sidewalls and the top surface of the bit line 120 and on the cap layer 110 to prevent the bit line 120 from directly contacting with the subsequently formed capacitor contact and forming a short circuit.

[0071] In some embodiments, the dielectric liner 130 located on both sidewalls of the bit line 120 includes a nitride liner 131 and a nitride liner 133, and an oxide liner 132 disposed therebetween, so as to prevent parasitic capacitance from being generated between the bit line 120 and a subsequently formed capacitor contact. In an alternative embodiment, the oxide liner 132 may also be replaced by an air gap.

[0072] In some embodiments, the dielectric liner 130 on the top surface of the bit line 120 and on the cap layer 110 only includes a nitride liner 133 to protect the underlying film layers from being affected by subsequent manufacturing processes.

[0073] In some embodiments, a nitride liner 131 and an oxide liner 132 are first deposited by a deposition process, and then the nitride liner 131 and the oxide liner 132 located on the top surface of the bit line 120 and the top surface of the cap layer are removed by an etch-back process. Finally, a nitride liner 133 is deposited by a deposition process, so that the oxide liner 132 is sandwiched between the nitride liners 131 and 133.

[0074] then, Figure 3-Figure 10 1 and 2 are cross-sectional views of different stages of forming a capacitor contact 140 on one side of a bit line 120 .

[0075] like Figure 3 As shown, the cap layer 110 and the semiconductor substrate 102 (including the etched spacer 109 ) are recessed along the sidewalls of the dielectric liner 120 by an etch-back process, so that the capacitor contact formed subsequently is electrically connected to the active region 102A of the semiconductor substrate 102 .

[0076] Then, if Figure 4-Figure 5 As shown, the semiconductor material 141 is deposited by a deposition process, and then the semiconductor material 141 is etched back by an etch-back process, so that the top surface of the semiconductor material 141' is lower than the top surface of the bit line 120. In some embodiments, the semiconductor material 141 includes doped polysilicon.

[0077] Then, if Figure 6-Figure 7 As shown, a nitride material layer 143 is conformally deposited by a deposition process, and then the nitride material layer 143 located on the top surface of the semiconductor material 141' and the top surface of the dielectric liner 130 is etched by an etching process until a portion of the top surface of the semiconductor material 141' is exposed, leaving the nitride layer 144 on both sides of the bit line 120.

[0078] In some embodiments, the top surface of the nitride layer 144 is flush with the top surface of the dielectric liner 130 , so that the nitride layer 144 has a finer pattern, which is beneficial for the subsequent definition of the metal silicide liner. In addition, the sidewalls of the nitride layer 144 directly contact the sidewalls of the dielectric liner 130 .

[0079] Then, if Figure 8 As shown, the nitride layer 144 is used as an etching mask to etch the semiconductor material 141' by an etching process to form a semiconductor material 141" having a recess 1420. Figure 8 In the embodiment, the semiconductor material 141 ″ is U-shaped and surrounds the recess 1420 , and at least a portion of the semiconductor material 141 ″ will be converted into a metal silicide liner later.

[0080] Then, if Fig. 9 As shown, the semiconductor material 141 ″ along the recess 1420 is transformed into a metal silicide liner 146 by a silicidation process to reduce the contact resistance with a subsequent metal plug (not shown).

[0081] Specifically, the semiconductor material 141″ directly below the nitride layer 144 and along the notch is completely transformed into the metal silicide liner 146, while the semiconductor material 141″ below the notch is only partially transformed into the metal silicide liner 146, and the remaining semiconductor material 141″ serves as the semiconductor plug 142. In other words, the silicided semiconductor material 141″ is replaced by the semiconductor plug 142 and the metal silicide liner 146, wherein the semiconductor plug 142 only directly contacts the lower side wall of the dielectric liner 130, and the metal silicide liner 146 only directly contacts the upper side wall of the dielectric liner 130.

[0082] In some embodiments, the metal silicide liner 146 is U-shaped and the top surface of the metal silicide liner 146 directly contacts the bottom surface of the nitride layer 144. In some embodiments, both sidewalls of the nitride layer 144 are flush with both sidewalls of the metal silicide liner 146 to effectively reduce the bit line capacitance. In other words, the width of the nitride layer 144 is the same as the width of the metal silicide liner 146.

[0083] In some embodiments, the silicide process includes first depositing a metal (e.g., cobalt) on the semiconductor plug 142, performing an annealing process on the metal, and then removing the unreacted portion of the metal using a wet etching process to form a metal silicide liner 146. In some embodiments, the metal silicide liner 146 includes cobalt silicon (CoSi).

[0084] Next, an adhesion layer material is formed along the surface of the metal silicide liner 146 by a deposition process and a planarization process, and a metal material is formed on the adhesion layer material. Then, a redundant portion is removed by a planarization process to form an adhesion layer 147 and a metal plug 148, and the following is obtained: Fig.10 In some embodiments, the top surface of the adhesion layer 147 , the top surface of the metal plug 148 , and the top surface of the nitride layer 144 are flush.

[0085] In some embodiments, the adhesion layer 147 can increase the adhesion between the metal silicide liner 146 and the metal plug 148 .

[0086] In some embodiments, since the adhesion layer 147 is formed along the sidewall and the bottom of the metal silicide liner 146 , the adhesion layer 147 has a U-shape and surrounds the metal plug 148 .

[0087] In some embodiments, the adhesion layer 147 is disposed between the metal silicide liner 146 and the metal plug 148. In some embodiments, the adhesion layer 147 extends along the sidewalls of the nitride layer 144 and the sidewalls and bottom of the metal silicide liner, and directly contacts the nitride layer 144 and the metal silicide liner 146. In some embodiments, the adhesion layer 147 includes titanium (Ti) or titanium nitride (TiN).

[0088] In some embodiments, the metal silicide liner 146 is located below the nitride layer 144 , and the metal plug 148 is flush with the nitride layer 144 , so the top surface of the metal silicide liner 146 is lower than the top surface of the metal plug 148 .

[0089] In some embodiments, a top portion of the metal plug 148 is surrounded by the nitride layer 144 , and a bottom portion and a sidewall of the metal plug 148 are surrounded by a metal silicide liner 146 .

[0090] Compared to the implementation of only disposing a metal silicide liner at the bottom of the metal plug, the embodiment of the present invention further disposes a metal silicide liner 146 on the sidewall of the metal plug 148 to increase the contact area and reduce the resistance of the capacitor contact.

[0091] In some embodiments, the bottom surface of the metal plug 148 is not lower than the bottom surface of the conductive layer 123 in the bit line 120 , and the metal plug 148 is separated from the conductive layer 123 by the metal silicide liner 146 to reduce the capacitance between the bit line 120 and the capacitor contact 140 .

[0092] In some embodiments, the width W of the nitride layer 144 is N is the width W of the metal plug 148 M When the thickness is greater than the above range, the contact area between the metal plug 148 and the capacitor formed subsequently is too small, resulting in a large contact resistance and affecting performance. When the thickness is less than the above range, the nitride layer 144 is easily corroded during the patterning process, making it difficult to define the U-shaped metal silicide liner 146.

[0093] In some embodiments, the semiconductor substrate 102 below the bit line contact 108 has a doped region (not shown) that can serve as a source, and the semiconductor substrate 102 below the capacitor contact 170 also has a doped region (not shown) that can serve as a drain. Figure 1 In any active region 102A extending along the third direction D3, the arrangement order is capacitor contact 140, word line 106, bit line contact 108, word line 106, capacitor contact 140, which can be used as drain, gate, source, gate, drain respectively. In other words, two sets of transistor structures in the active region 102A share the same source, and the layout can be more effectively utilized to save manufacturing costs.

[0094] Next refer to Fig.11 , a dielectric layer 152 , a conductive barrier layer 154 and a capacitor structure 160 are formed on the capacitor contact 140 and the bit line 120 .

[0095] In some embodiments, the dielectric layer 152 and the conductive barrier layer 154 are arranged alternately. The conductive barrier layer 154 is located directly above the capacitor contact 140 and crosses to the dielectric liner 130. In some embodiments, the conductive barrier layer 154 includes a material that can block the penetration of etching solution, such as tungsten or copper.

[0096] In some embodiments, the capacitor structure 160 includes electrode layers 162 and 166 and a dielectric layer 164 sandwiched therebetween. In some embodiments, the electrode layer 162 is formed on the conductive barrier layer 154 and has a U-shaped cross-sectional profile. In some embodiments, the dielectric layer 164 extends along the electrode layer 162 and the conductive barrier layer 154 and is a continuous film layer. It should be noted that Fig.11 The capacitor structure is only an example, and those skilled in the art may also use different Fig.11 The capacitor structure is on the capacitor contact 140.

[0097] In some embodiments, the dielectric layer 164 may include silicon nitride (Si3N4), aluminum oxide (Al2O3), yttrium oxide (Y2O3), titanium oxide (TiO), hafnium dioxide (HfO2) or zirconium dioxide (ZrO2), etc. In some embodiments, the electrode layers 162 and 166 may include silicon germanium (SiGe), titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, etc., so as to reduce leakage current.

[0098] It should be noted that after forming the capacitor structure 160 , additional components such as metal layers and dielectric layers may still be formed to complete the fabrication of a memory device such as a dynamic random access memory (DRAM).

[0099] In summary, the embodiment of the present invention can reduce the resistance of the capacitor contact and the capacitance of the bit line by extending the metal silicide liner along the sidewall of the metal plug.

[0100] Fig.12 FIG. 1 is a schematic top view of a semiconductor memory structure according to some embodiments of the present invention. It should be noted that in order to highlight the structure of the capacitor contact 140, Fig.12 The top view shown only shows part of the device.

[0101] In detail, Fig.12The capacitor contact 140 includes a metal plug 148, an adhesion layer 147 surrounding the metal plug 148, and a metal silicide liner 146. The metal silicide liner 146 is located at the outer circle, while the adhesion layer 147 is located at the inner circle to prevent the metal plug 144 from being peeled off from the surface of the metal silicide liner 146.

[0102] Figure 13-14 FIG. 4 is a cross-sectional view of a semiconductor memory structure at different stages according to another embodiment of the present invention.

[0103] Undertake Figure 8 By widening the width of the nitride layer 144 or shortening the time of the silicidation manufacturing process, only a portion of the semiconductor material 141″ directly below the nitride layer 144 can be transformed into the metal silicide liner 146, and the remaining semiconductor material 141″ serves as the semiconductor plug 142. In other words, the semiconductor plug 142 is U-shaped and surrounds the metal silicide liner 146, and the dielectric liner 130 is disposed on both sidewalls of the semiconductor plug 142.

[0104] In some embodiments, the top surface of the semiconductor plug 142 is flush with the top surface of the metal silicide liner 146 and directly contacts the bottom surface of the nitride layer 144. In some embodiments, the sidewalls of the nitride layer 144 are collinear with the semiconductor plug 142 and the metal silicide liner 146, that is, the sidewalls of the nitride layer 144 are flush with the sidewalls of the semiconductor plug 142 and the metal silicide liner 146, respectively.

[0105] The semiconductor plug 142 is further disposed on the sidewall of the metal silicide liner 146 to increase the production capacity.

[0106] Next, similar to the above manufacturing process, an adhesion layer 147 and a metal plug 148 are formed, and the following can be obtained: Fig.14 Semiconductor memory structure.

[0107] In some embodiments, the width W of the metal silicide liner 146 is S The width W of the nitride layer 144 N The proportion is not less than 30%, for example, Fig.13 Medium Width W S With width W N The ratio is 30% - less than 100%, or Fig.10 Medium Width W S With width W N The ratio is 100%, which can reduce the contact resistance at a lower cost. Since the nitride layer 144 is used to define the shape of the semiconductor material (or the metal silicide liner), the above ratio is unlikely to exceed 100%.

[0108] Fig.15 FIG. 1 is a schematic top view of a semiconductor memory structure according to some embodiments of the present invention. It should be noted that in order to highlight the structure of the capacitor contact 140, Fig.15 The top view shown only shows part of the device.

[0109] Fig.15 Similar to Fig.12 , the difference lies in the capacitor contact 140. Specifically, Fig.15 The capacitor contact 140 is disclosed to include a metal plug 148, an adhesion layer 147 surrounding the metal plug 148, a metal silicide liner 146, and a semiconductor plug 142. Moreover, with the metal plug 148 as the center, from the inside to the outside are the adhesion layer 147, the metal silicide liner 146, and the semiconductor plug 142. That is, in the capacitor contact 140, the outermost circle is the semiconductor plug 142 to reduce the capacitance value of the bit line.

[0110] Figure 16-Figure 18 FIG. 4 is a cross-sectional view of a semiconductor memory structure at different stages according to another embodiment of the present invention.

[0111] Fig.16 Undertake Figure 6 In some embodiments, by adjusting the etching conditions, for example, making the etching rate of the upper part of the nitride layer 144 faster than that of the lower part, the nitride layer 144 presents a trapezoidal shape with a narrow upper part and a wide lower part.

[0112] then, Fig.17 Similar to Figure 8 , using the bottom of the nitride layer 144 as an etching mask, the semiconductor material 141 ′ is etched by an etching process to form a semiconductor plug 142 having a notch 1420 .

[0113] Next, by using a manufacturing process similar to the above, a metal silicide liner 146, an adhesion layer 147 and a metal plug 148 are formed, and the following can be obtained: Fig.18 The semiconductor memory structure. Fig.17 In the example, due to the width W of the top surface of the nitride layer 144 N1 Width W of bottom surface N2 narrow, so the top W of the formed metal plug 148 is M1 The width of the metal plug 148 is greater than the bottom W M2 Thereby, the contact resistance between the metal plug 148 and the upper device (such as a capacitor) is reduced.

[0114] In summary, the embodiments of the present invention can reduce the resistance of the capacitor contact and the capacitance of the bit line by extending the metal silicide liner to the sidewalls of the metal plug. In addition, by forming a semiconductor plug around the metal silicide liner, the capacitance of the bit line can be further reduced. In addition, by using a metal plug with an uneven width (e.g., wide at the top and narrow at the bottom), the contact resistance with the upper device can be reduced while reducing the capacitance of the bit line.

Claims

1. A semiconductor memory structure, characterized in that: include: a semiconductor substrate; a bit line disposed on the semiconductor substrate; as well as A capacitor contact is disposed on one side of the bit line, wherein the capacitor contact comprises: A semiconductor plug is disposed on the semiconductor substrate; A metal plug is disposed on the semiconductor plug; a metal silicide liner extending along the sidewall and bottom of the metal plug, wherein a top surface of the metal silicide liner is lower than a top surface of the metal plug; and A nitride layer is disposed on the metal silicide liner, and the nitride layer surrounds the top of the metal plug.

2. The semiconductor memory structure according to claim 1, wherein: A top surface of the nitride layer is flush with a top surface of the metal plug.

3. The semiconductor memory structure according to claim 1, wherein: The sidewall of the nitride layer is flush with the sidewall of the semiconductor plug.

4. The semiconductor memory structure according to claim 1, wherein: The invention further comprises a dielectric liner disposed between the bit line and the capacitor contact, wherein the top surface of the nitride layer is flush with the top surface of the dielectric liner.

5. The semiconductor memory structure according to claim 4, characterized in that: The nitride layer is located between the dielectric liner and the metal plug and directly contacts the dielectric liner.

6. The semiconductor memory structure according to claim 1, wherein: The invention further comprises an adhesion layer disposed between the metal silicide liner and the metal plug.

7. The semiconductor memory structure according to claim 6, characterized in that: A top surface of the adhesion layer is flush with a top surface of the metal plug.

8. The semiconductor memory structure according to claim 1, wherein: The semiconductor plug is U-shaped and surrounds the metal plug.

9. The semiconductor memory structure according to claim 1, wherein: In the cross-sectional view, the ratio of the width of the metal silicide liner to the width of the nitride layer is 30%-100%.

10. The semiconductor memory structure according to claim 1, wherein: In the cross-sectional view, the width of the nitride layer is 5%-20% of the width of the metal plug.

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