semiconductor devices

Abstract

The present invention provides a semiconductor device comprising: at least one transistor, a shallow well region, a guard ring, and a plurality of first doped regions and a plurality of second doped regions. The at least one transistor is located on a substrate, and the at least one transistor comprises a source structure, a gate structure, and a drain structure. The shallow well region surrounds the at least one transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has a first conductivity type. The first doped region and the second doped region are arranged within the guard ring and surround the shallow well region. The first doped region and the second doped region are alternately arranged to form a ring. Each of the first doped regions and each of the second doped regions have opposite conductivity types.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly, to integrated circuits having guard rings for electrostatic discharge systems. Background Art

[0002] Semiconductor devices can be used in a variety of applications, such as display driver ICs, power management ICs (or high-power power management ICs), discrete power devices, sensing devices, fingerprint sensor ICs, and memory devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate. The various material layers are then patterned using photolithography techniques to form circuit components and elements on the semiconductor substrate.

[0003] The continued scaling of semiconductor devices presents numerous challenges. For example, semiconductor devices may be damaged by electrostatic discharge (ESD) during processing, manufacturing, assembly, shipping, packaging, testing, or operation. Therefore, semiconductor devices require ESD protection to prevent potential ESD damage and improve device reliability. While existing ESD protection for semiconductor devices generally meets these requirements, it is not entirely satisfactory in all respects. Summary of the Invention

[0004] An embodiment of the present invention provides a semiconductor device, comprising: at least one transistor on a substrate, the at least one transistor including a source structure, a gate structure, and a drain structure; a shallow well region surrounding the at least one transistor, wherein the shallow well region has a first conductivity type; a guard ring surrounding the shallow well region, wherein the guard ring has the first conductivity type; and a plurality of first doped regions and a plurality of second doped regions arranged within the guard ring and surrounding the shallow well region, wherein the first doped regions and the second doped regions are alternately arranged to form a ring, and each of the first doped regions and each of the second doped regions have opposite conductivity types. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The embodiments of the present invention are best understood by the following detailed description in conjunction with the accompanying drawings. In accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of various elements may be arbitrarily increased or decreased to clearly illustrate the features of the embodiments of the present invention.

[0006] Figure 1 FIG. 1 is a schematic top view illustrating a layout of a semiconductor device according to some embodiments of the present invention.

[0007] Figure 2 FIG2 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0008] Figure 3 A schematic top view of the layout of a comparative example is shown.

[0009] Figure 4A and Figure 4B Graphs are shown showing the transmission line pulse test and leakage test results of a comparative example and an example of the present invention.

[0010] Explanation of symbols

[0011] 10: semiconductor devices;

[0012] 100: substrate;

[0013] 101: buried layer;

[0014] 102: shallow well area;

[0015] 104: protection ring;

[0016] 105a, 105b, 105c, 106a, 106b, 107a, 107b, 107c: well area;

[0017] 111: first doped region;

[0018] 112: second doped region;

[0019] 113: third doped region;

[0020] 114: Source structure;

[0021] 115: Gate structure;

[0022] 118: drain structure;

[0023] 119: transistor;

[0024] 120,122,124: quarantine area;

[0025] 121,123: doped regions;

[0026] 20: Semiconductor device. DETAILED DESCRIPTION

[0027] The following disclosure provides many embodiments or examples for implementing different elements of the embodiments of the present invention. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to represent the relationship between the different embodiments and / or configurations discussed.

[0028] Furthermore, in some embodiments of the present invention, terms related to bonding and connection, such as "connect," "interconnect," and the like, unless otherwise specified, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with another structure positioned between the two structures. Furthermore, such terms related to bonding and connection may also include situations where both structures are movable or both structures are fixed. Furthermore, the term "coupled" includes direct or indirect electrical connection by any means.

[0029] Furthermore, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used to facilitate describing the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or in other orientations, the spatially relative adjectives used will also be interpreted based on the orientation after the rotation.

[0030] The terms "about," "approximately," and "substantially" as used herein generally mean within ±20%, preferably within ±10%, and more preferably within ±5%, or within ±3%, or within ±2%, or within ±1%, or within ±0.5% of a given value. The numerical values ​​given herein are approximate. Unless otherwise specified, a given numerical value may imply the meaning of "about," "approximately," or "substantially."

[0031] Some embodiments of the present invention are described below. Additional steps may be provided before, during, and / or after the stages described in these embodiments. Some of the stages described may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor devices of the embodiments of the present invention. Some of the components described below may be replaced or deleted in different embodiments. Although some embodiments are discussed as performing operations in a specific order, these operations may also be performed in another logical order.

[0032] An embodiment of the present invention provides a semiconductor device. Multiple doped regions of opposite conductivity types are alternately arranged on a guard ring of the semiconductor device. This arrangement can improve electrostatic discharge protection and semiconductor device reliability while reducing the area occupied by the guard ring.

[0033] For ease of explanation, some embodiments of the present invention are described using a metal oxide semiconductor (MOS) device. However, the present invention is not limited thereto. Embodiments of the present invention may also be applied to various semiconductor devices, such as a laterally diffused metal oxide semiconductor (LDMOS) device, a lateral insulated gate bipolar transistor (LIGBT), a vertically diffused metal oxide semiconductor (VDMOS) device, an extended-drain metal oxide semiconductor (EDMOS) device, or other semiconductor devices. In addition, embodiments of the present invention may also be applied to other types of semiconductor devices, such as a diode, an insulated gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), or other semiconductor devices.

[0034] Reference Figure 1 , according to some embodiments of the present invention, a schematic top view of the layout of the semiconductor device 10 is depicted. It should be noted that, Figure 1 The three dots in the figure indicate that the components described below can be repeated according to the design or requirements of the desired device. The semiconductor device 10 includes: at least one transistor 119, a shallow well region 102, a guard ring 104, and a plurality of first doped regions 111 and a plurality of second doped regions 112 on a substrate 100. For clarity, the substrate 100 is not shown in FIG. Figure 1, and will be illustrated in the cross-sectional views described below. The substrate 100 may be a doped (e.g., doped with p-type or n-type dopants) or undoped semiconductor substrate. For example, the substrate 100 may include: an elemental semiconductor including silicon or germanium; a compound semiconductor including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor including silicon-germanium (SiGe) alloy, gallium arsenic phosphide (GaAsP) alloy, aluminum indium arsenic (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, indium gallium arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and / or gallium indium arsenic phosphide (GalnAsP) alloy, or a combination of the foregoing materials.

[0035] In some embodiments, the substrate 100 may also be a semiconductor-on-insulator (SIO) substrate, such as a silicon-on-insulator (SOI) substrate or a silicon-germanium-on-insulator (SGOI) substrate. In other embodiments, the substrate 100 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide (Al2O3) substrate (also known as a sapphire substrate), or other substrates. In other embodiments, the substrate 100 may include a ceramic substrate and a pair of barrier layers respectively disposed on the upper and lower surfaces of the ceramic substrate. The ceramic substrate may include a ceramic material, and the ceramic material includes an inorganic metal material. For example, the ceramic substrate may include silicon carbide, aluminum nitride, a sapphire substrate, or other suitable materials. The aforementioned sapphire substrate may be aluminum oxide.

[0036] Transistor 119 is disposed on substrate 100 and may include a source structure 114, a gate structure 115, and a drain structure 118. In some embodiments, each of source structure 114 and each of drain structure 118 include a doped region, and the doped region of source structure 114 and the doped region of drain structure 118 have the same conductivity type. The doping concentration of the doped region of source structure 114 and the doped region of drain structure 118 may be approximately 1E+19 cm -3 to 1E+21cm -3. The method of forming the doped region of the source structure 114 includes (but is not limited to): using a photolithography process and an etching process to form a patterned mask layer (not shown) on the substrate 100, wherein the patterned mask layer exposes the predetermined area where the doped region is to be formed and covers the remaining area of ​​the substrate 100; implanting dopants into the predetermined area where the doped region is to be formed; and removing the patterned mask layer. The patterned mask layer can be a hard mask or a photoresist. In an embodiment where an n-type doped region is to be formed, the dopant can be an n-type dopant, such as phosphorus, arsenic, or antimony. In an embodiment where a p-type doped region is to be formed, the dopant can be a p-type dopant, such as boron, indium, or BF2. The method of forming the doped region of the drain structure 118 is similar to the method of forming the doped region of the source structure 114. In some embodiments, the doping concentration of the source structure 114 can be the same as the doping concentration of the drain structure 118. In one embodiment, the source structure 114 and the drain structure 118 can be formed in the same process step.

[0037] The gate structure 115 may include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. In some embodiments, the method for forming the gate structure 115 includes sequentially depositing a blanket dielectric material layer (for forming the gate dielectric layer) and a blanket conductive material layer (for forming the gate electrode) on the dielectric material layer, and then patterning the dielectric material layer and the conductive material layer through photolithography and etching processes to form the gate dielectric layer and the gate electrode, respectively. In some embodiments, the source structure 114 and the drain structure 118 may be disposed on both sides of the gate structure 115.

[0038] Reference Figure 1 The shallow well region 102 surrounds the transistor 119. In some embodiments, the shallow well region 102 has a first conductivity type, which is the same conductivity type as the doped region 114 of the source structure S and the doped region 118 of the drain structure D. The guard ring 104 surrounds the shallow well region 102. In some embodiments, the guard ring 104 has a first conductivity type. The doping concentration of the guard ring 104 can be approximately 1E+16 cm -3 to 1E+17cm -3 The method of forming the shallow well region 102 and the method of forming the guard ring 104 may be similar to the method of forming the source structure 114 .

[0039] A plurality of first doping regions 111 and a plurality of second doping regions 112 are formed in the guard ring 104 and surround the shallow well region 102. In the top view, the first doping regions 111 and the second doping regions 112 are arranged alternately in a ring shape. The method of forming the plurality of first doping regions 111 includes (but is not limited to): forming a patterned mask layer (not shown) on the guard ring 104 using a photolithography process and an etching process, wherein the patterned mask layer exposes a predetermined area where the first doping region 111 is to be formed and covers the remaining area; implanting dopants into the predetermined area where the first doping region 111 is to be formed; and removing the patterned mask layer. The patterned mask layer can be a hard mask or a photoresist. The method of forming the second doping region 112 is similar to the method of forming the first doping region 111. According to some embodiments of the present invention, each of the first doping regions 111 and each of the second doping regions 112 have opposite conductivity types. For example, in an embodiment where the first doping region 111 is n-type, the dopant used to implant the second doping region 112 is a p-type dopant (e.g., boron, indium, or BF2) to form a p-type second doping region 112; in an embodiment where the first doping region 111 is p-type, the dopant used to implant the second doping region 112 is an n-type dopant (e.g., phosphorus, arsenic, or antimony). The doping concentration of the first doping region 111 and the doping concentration of the second doping region 112 can be approximately 1E+19 cm -3 to 1E+21cm -3 In some embodiments, the first doping regions 111 and the second doping regions 112 have the same doping concentration. In some embodiments, the number of the second doping regions 112 is equal to the number of the first doping regions 111. In alternative embodiments, the number of the second doping regions 112 may not be equal to the number of the first doping regions 111.

[0040] In some embodiments, the length of the first doping region 111 is smaller than the length of the second doping region 112. Figure 1 As shown. In such an embodiment, if the first doping region 111 is n-type and the second doping region 112 is p-type, the first doping region 111 and the second doping region 112 form a silicon controlled rectifier (SCR) structure with a PNP path, and the first doping region 111 is used to provide a potential, so a very large first doping region 111 is not required. In some embodiments, the length ratio of the first doping region 111 to the second doping region is approximately 1 / 10. However, in other embodiments, the length of the first doping region 111 may be greater than or equal to the length of the second doping region 112. According to some embodiments of the present invention, the first doping region 111 and the second doping region 112 form a rectangular shape, as shown. Figure 1As shown. In addition, each side of the rectangular shape has at least one first doping region 111 and at least one second doping region 112. However, in other embodiments, the shape formed by the first doping region 111 and the second doping region 112 is not limited. For example, the first doping region 111 and the second doping region 112 can form an oval or a stadium track shape. This shape can be adjusted according to actual needs. The first doping region 111 and the second doping region 112 can prevent damage from electrostatic discharge. In some embodiments, each of the first doping regions 111 and each of the second doping regions 112 are spaced apart and separated from each other. For example, each of the first doping regions 111 and each of the second doping regions 112 can be separated by a guard ring 104. The distance between the first doping region 111 and the adjacent second doping region 112 can be adjusted according to actual needs. In some embodiments, the doping concentration of the first doping region 111 is equal to the doping concentration of the second doping region 112. In some embodiments, the doping concentration of the first doping region 111 and the doping concentration of the second doping region 112 are greater than the doping concentration of the guard ring 104. For example, the doping concentration of the first doping region 111 is about 1E+19 cm -3 to 1E+21cm -3 The doping concentration of the second doping region 112 is about 1E+19 cm -3 to 1E+21cm -3 , and the doping concentration of the guard ring 104 is about 1E+16cm -3 to 1E+17cm -3 According to some embodiments of the present invention, the first doped region 111 , the second doped region 112 , and the drain structure 118 are electrically connected.

[0041] Reference Figure 1 In some embodiments, the semiconductor device 10 further includes at least two third doping regions 113, respectively disposed on both sides of the transistor 119, and at least two third doping regions 113 have a second conductivity type opposite to the first conductivity type. The doping concentration of the third doping region 113 is approximately 1E+19 cm -3 to 1E+21cm -3 . In some embodiments, the second doping region 112 and the third doping region 113 have the same doping concentration. In some embodiments, the third doping region 113 can be used to form a PNPN path in the device. The function of the PNPN path will be described in more detail below. In some embodiments, the at least two third doping regions 113, the source structure 114, the gate structure 115, and the shallow well region 102 are electrically connected. In other embodiments, the at least two third doping regions 113, the source structure 114, the gate structure 115, and the shallow well region 102 are electrically connected to ground. In some embodiments, at least one third doping region 113 is adjacent to the source structure 114.

[0042] According to some embodiments of the present invention, the semiconductor device 10 includes a plurality of transistors 119. Figure 1 As shown, each of the transistors 119 includes a source structure 114 and a gate structure 115. In addition, a drain structure 118 is disposed between two adjacent transistors 119, such that the two adjacent transistors 119 share the drain structure 118. In some embodiments, the drain structure 118, the first doped region 111, and the second doped region 112 are electrically connected. Figure 1 As shown, in some embodiments, the third doped region 113 is disposed on both sides of the plurality of transistors 119 and between adjacent source structures 114 in the plurality of transistors 119. In some embodiments, the third doped region 113, the source structures 114 and gate structures 115 in the plurality of transistors 119, and the shallow well region 102 are electrically connected. In other embodiments, the third doped region 113, the source structures 114 and gate structures 115 in the plurality of transistors 119, and the shallow well region 102 are electrically connected to ground.

[0043] Figure 2 According to some embodiments of the present invention, a semiconductor device 10 is shown along Figure 1 It should be understood that for the sake of clarity, Figure 2 Some parts in the Figure 1 As shown in the figure. Figure 2 As shown, the semiconductor device 10 includes a buried layer 101 disposed on a substrate 100. In some embodiments, the buried layer 101 has a first conductivity type. The doping concentration of the buried layer 101 may be approximately 1E+16 cm -3 to 1E+17cm -3 .

[0044] Reference Figure 2 , semiconductor device 10 includes well regions 105a, 105b, 105c, 106a, 106b, 107a, 107b, and 107c. In some embodiments, well regions 105a, 105b, 105c, 107a, 107b, and 107c have the second conductivity type, and well regions 106a and 106b have the first conductivity type. The doping concentration of well regions 105a, 105b, 105c, 106a, and 106b may be approximately 1E+17 cm -3 to 1E+19cm -3 The doping concentration of the well regions 107a, 107b, and 107c may be approximately 1E+18 cm -3 to 1E+20cm -3The method for forming these well regions is similar to the method for forming the doped regions of the source structure 114 described above. Well regions 105a, 105b, 105c, 106a, and 106b are disposed on the buried layer 101. Each of the well regions 106a and 106b includes a drain structure 118 disposed therein. Well regions 107a, 107b, and 107c are disposed in the well regions 105a, 105b, and 105c, respectively. The shallow well region 102 is disposed in the well regions 107a and 107c, and each of the well regions 107a and 107c includes a third doped region 113 and a source structure 114 disposed therein. The well region 107b includes two source structures 114 and a third doped region 113 disposed between the two source structures 114. A gate structure 115 is disposed on the well regions 106a and 106b and between adjacent source structures 114 and drain structures 118 to form a transistor 119. As described above, two adjacent transistors 119 share a drain structure 118 disposed therebetween. For example, a transistor 119 is formed by a source structure 114 in the well region 107a, a drain structure 118 in the well region 106a, and a gate structure 115 between the source and drain structures 114 and 118. Another transistor 119 is formed by a source structure 114 in the well region 107b and adjacent to the drain structure 118 in the well region 106a, the drain structure 118 in the well region 106a, and a gate structure 115 between the source and drain structures 114 and 118. Thus, the two adjacent transistors 119 share the drain structure 118 in the well region 106a. In some embodiments, the first doped region 111, the second doped region 112, and the drain structure 118 are electrically connected to a first voltage, such as a power supply voltage VCC. In some embodiments, the shallow well region 102, the third doped region 113, the source structure 114, and the gate structure 115 are electrically connected to a second voltage, such as a power supply VSS or a ground GND. In some embodiments, the first voltage is the power supply voltage and the second voltage is ground. In some embodiments, the first voltage is greater than the second voltage. In other embodiments, the first voltage is less than the second voltage. In some embodiments, the gate structure 115 is disposed on the well regions 105a and 106a, the drain structure 118 is disposed in the well region 106a, and the source structure 114, the shallow well region 102, and at least one third doped region 113 are disposed in the well region 105a. In some embodiments, the guard ring 104, the well regions 105a, 105b, and 105c are directly connected to the buried layer. In some embodiments, the well region 107a (or 107c) in the well region 105a (or 105c) surrounds the corresponding source structure 114, the shallow well region 102, and the at least one third doped region 113. In some embodiments, the semiconductor 10 may further include a field plate 117 disposed on the gate structure 115 and a dielectric layer 116 disposed between the field plate 117 and the gate structure 115. Figure 2 shown.

[0045] In some embodiments, where the well regions 105a, 105c, 107a, 107c, and the second doped region 112 have the second conductivity type, and the shallow well region 102 and the guard ring 104 have the first conductivity type, a PNPN path can be formed from the second doped region 112 to the shallow well region 102, or from the shallow well region 102 to the second doped region 112. For example, if the first conductivity type is n-type and the second conductivity type is p-type, the second doped region 112 (p-type), the guard ring 104 (n-type), the well regions 105a and 107a (p-type), and the shallow well region 102 (n-type) form a PNPN path. Similarly, the second doped region 112 (p-type), the guard ring 104 (n-type), the well regions 105c and 107c (p-type), and the shallow well region 102 (n-type) form a PNPN path. Conversely, if the first conductivity type is p-type and the second conductivity type is n-type, shallow well region 102 (p-type), well regions 105a and 107a (n-type), guard ring 104 (p-type), and second doped region 112 (n-type) form a PNPN path. This PNPN path in the semiconductor device can prevent electrostatic discharge damage. The above description is merely one objective of the present invention and is not intended to limit the scope of the invention.

[0046] In some embodiments, the semiconductor device 10 includes an isolation region (not in the Figure 1 ), such as isolation regions 120, 122, and 124. Isolation region 120 is disposed between the shallow well region 102 and the guard ring 104. Isolation region 122 is disposed between the shallow well region 102 and the third doped region 113 in the well regions 107a and 107c, and isolation region 124 is disposed between the third doped region 113 in the well region 107b and the source structure 114. In some embodiments, isolation region 122 is disposed between a corresponding shallow well region 102 and one of the third doped regions 113 adjacent to the shallow well region 102. The isolation region may include shallow trench isolation (STI), local oxidation of silicon (LOCOS), or a combination thereof. In some embodiments, the process of forming shallow trench isolation includes: forming a mask layer (not shown) on the corresponding well region and patterning the mask layer, etching a trench (or multiple trenches) in the substrate using the patterned mask layer as an etching mask, performing a deposition process to fill the trench (or multiple trenches) with an isolation material, and performing a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, to remove excess portions of the isolation material. The isolation material may include oxides, nitrides, or oxynitrides, such as silicon oxide (SiO2), carbon-doped silicon oxide (SiO xC), silicon oxynitride (SiON), silicon-oxy-carbonnitride (SiOCN), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon nitride (Si x N y or SiN), silicon oxycarbide (SiCO), any other suitable material, or any combination thereof. In some embodiments, the silicon local oxidation process for forming the isolation region may include: depositing a mask layer (e.g., a silicon nitride layer) on the corresponding well region, patterning the mask layer using photolithography and etching processes to expose a portion of the corresponding well region, thermally oxidizing the exposed portion of the corresponding well region to form a silicon oxide layer, and removing the patterned mask layer. The isolation regions may be formed in the same process or in different processes.

[0047] One or more embodiments of the present invention provide many advantages to semiconductor devices. For example, compared to Figure 3 The doped regions 121 and 123 in the comparative example shown are arranged parallel to and around the shallow well region 102 of the semiconductor device 20. The embodiment of the present invention provides a more space-saving layout by alternating the doped regions 111 and 112 in the guard ring 104 surrounding the shallow well region 102 of the semiconductor 10. The device obtained by the embodiment of the present invention passed the 8kV Human-Body Model (HBM) test, while the comparative example failed the HBM test at more than 1kV. In addition, referring to Figure 4A and Figure 4B , which respectively shows the transmission line pulse (TLP) test results of a comparative example and an example of the present invention. The bottom horizontal axis represents the transmission line pulse voltage, the top horizontal axis represents the leakage current on a logarithmic scale, and the vertical axis represents the transmission line pulse current. Compared to the comparative example, in substantially the same transmission line pulse current range, the example of the present invention has a relatively stable leakage current and provides stable results. An embodiment of the present invention provides a semiconductor device with significantly better human body model test results (passing 8kV) and stable leakage current to improve electrostatic discharge protection and device reliability. Due to the better turn-on efficiency of the silicon-controlled rectifier, the present invention is more reliable for electrostatic discharge self-protection. The advantages described above are examples of the purpose of the present invention and are not intended to limit the scope of the invention.

[0048] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the embodiments of the present invention. Those skilled in the art will understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: At least one transistor, on a substrate, the at least one transistor including a source structure, a gate structure, and a drain structure; a shallow well region surrounding the at least one transistor, wherein the shallow well region has a first conductivity type; a guard ring surrounding the shallow well region, wherein the guard ring has the first conductivity type; as well as A plurality of first doping regions and a plurality of second doping regions are arranged in the guard ring and surround the shallow well region, wherein the first doping regions and the second doping regions are alternately arranged to form a ring, and each of the first doping regions and each of the second doping regions has opposite conductivity types, wherein the doping concentration of the first doping region and the doping concentration of the second doping region are greater than the doping concentration of the guard ring, and each of the first doping regions is separated from each of the second doping regions.

2. The semiconductor device according to claim 1, wherein The length of the first doping region is less than or equal to the length of the second doping region.

3. The semiconductor device according to claim 1, wherein Also includes: At least one third doped region is adjacent to the source structure and disposed on at least one side of the transistor.

4. The semiconductor device according to claim 3, wherein The second doping region and the at least one third doping region have the same doping concentration.

5. The semiconductor device according to claim 1, wherein Also includes: A buried layer is disposed on the substrate, wherein the buried layer has the first conductivity type.

6. The semiconductor device according to claim 5, wherein Also includes: at least one third doped region adjacent to the source structure and disposed on at least one side of the transistor; and a first well region having the first conductivity type and a second well region having a second conductivity type opposite to the first conductivity type, wherein the gate structure is disposed on the first well region and the second well region, the drain structure is disposed in the first well region, and the source structure, the shallow well region and the at least one third doped region are disposed in the second well region.

7. The semiconductor device according to claim 6, wherein: The guard ring and the second well region are directly connected to the buried layer.

8. The semiconductor device according to claim 6, wherein Also includes: A third well region is disposed in the second well region and surrounds the source structure, the shallow well region and the at least one third doped region.

9. The semiconductor device according to claim 8, wherein The second doped region, the guard ring, the second well region, the third well region, and the shallow well region form a PNPN structure.

10. The semiconductor device according to claim 1, wherein The drain structure, the first doping region, and the second doping region are electrically connected.

11. The semiconductor device according to claim 1, wherein The at least one transistor is a plurality of transistors, each of the transistors includes the source structure and the gate structure, wherein two adjacent transistors share the drain structure disposed therebetween.

12. The semiconductor device according to claim 11, wherein Also includes: At least two third doped regions are respectively disposed on two sides of the transistor, wherein the at least two third doped regions have a second conductivity type opposite to the first conductivity type.

13. The semiconductor device according to claim 12, wherein: Also includes: An isolation region is disposed between the shallow well region and one of the third doped regions adjacent to the shallow well region.

14. The semiconductor device according to claim 12, wherein The drain structure, the first doped region, and the second doped region are electrically connected to a first voltage.

15. The semiconductor device according to claim 14, wherein The at least two third doped regions, the source structure, the gate structure, and the shallow well region are electrically connected to a second voltage.

16. The semiconductor device according to claim 15, wherein The first voltage is greater than the second voltage.

17. The semiconductor device according to claim 1, wherein Also includes: An isolation region is disposed between the shallow well region and the first doping region and the second doping region.

18. The semiconductor device according to claim 1, wherein Also includes: A field plate is disposed on the gate structure, and a dielectric layer is disposed between the field plate and the gate structure.

Images