Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: source-drain doped layers located on the protrusions on both sides of the gate structure and the gate side wall and in contact with the end portions of the channel structure layer, and in the device unit area, the source-drain doped layers located on the adjacent end portions of the channel structure layer are spaced apart; source-drain plugs located on the protrusions and in contact with the source-drain doped layers, the source-drain plugs cover the end surface of the source-drain doped layers along the extension direction of the channel layer, which is beneficial to increase the contact area between the source-drain plug and the source-drain doped layer, thereby reducing the contact resistance between the source-drain plug and the source-drain doped layer, and also beneficial to increase the forming space of the source-drain plug, thereby reducing the resistance of the source-drain plug, and optimizing the performance of the semiconductor structure.

Claims

1. A semiconductor structure, characterized in that, include: The substrate comprises multiple discrete device cell regions; Multiple protrusions are distributed on the substrate of the device unit region; A channel structure layer is located above and spaced apart from the protrusion, and the channel structure layer includes one or more channel layers arranged at intervals in sequence; An isolation layer is located on the substrate and surrounds the protrusion, exposing the channel structure layer; A gate structure is located on the isolation layer and the protrusion, the gate structure spans the channel structure layer and surrounds the channel layer; Gate sidewalls are located on both sides of the gate structure and expose the ends of the channel structure layer extending in the direction of extension. The source and drain doped layers are located on both sides of the gate structure and the gate sidewall and are in contact with the ends of the channel structure layer. In the device cell region, the source and drain doped layers located on the ends of adjacent channel structure layers are spaced apart. A source / drain plug is located on the protrusion and in contact with the source / drain doped layer, the source / drain plug covering the end surface of the source / drain doped layer along the extension direction of the channel layer.

2. The semiconductor structure as described in claim 1, characterized in that, In the device cell region, the source / drain plugs are filled between the gate sidewalls of adjacent gate structure sidewalls and between the source / drain doped layers on adjacent channel structure layers along the channel layer extension direction.

3. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a silicide layer located between the source / drain doped layer and the source / drain plug.

4. The semiconductor structure as described in claim 1, characterized in that, The number of the channel layers is multiple, and in the same channel structure layer, the source and drain doped layers at the ends of adjacent channel layers are spaced apart; The source / drain plug is also filled between adjacent channel layers in the same channel structure layer.

5. The semiconductor structure as described in claim 4, characterized in that, The first portion is the portion of the gate structure located between adjacent channel layers or between the channel layer and the protrusion. Along the extension direction of the channel layer, the sidewall of the first portion is recessed relative to the sidewall of the channel layer; the semiconductor structure further includes: an inner sidewall located between adjacent channel layers, or between a channel layer and a protrusion, and the inner sidewall covers the sidewall of the first portion; The source / drain plug is filled between adjacent channel layers in the same channel structure layer and contacts the inner sidewall.

6. The semiconductor structure as described in claim 1, characterized in that, The number of channel layers is multiple, and in the same channel structure layer, the source and drain doped layers at the ends of adjacent channel layers are in contact.

7. The semiconductor structure as described in claim 6, characterized in that, In the same channel structure layer, a recess is formed between the source and drain doped layers at the ends of adjacent channel layers; The source plug fills the recess.

8. The semiconductor structure as described in claim 1, characterized in that, The top surface of the isolation layer is lower than the top surface of the protrusion; The semiconductor structure further includes: a bottom doped layer embedded in the protrusions exposed by the isolation layer; The source / drain plug contacts the top of the bottom doped layer and covers the end surface of the source / drain doped layer along the channel layer extension direction.

9. The semiconductor structure as described in claim 1, characterized in that, The substrate material includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the protrusion includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the channel layer includes one or more of single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon germanium oxide.

10. The semiconductor structure as claimed in claim 1, characterized in that, The gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer; The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, comprising a plurality of discrete device cell regions, wherein a plurality of protrusions and an initial stacked structure are formed on the substrate of the device cell regions, including a plurality of channel stacks stacked sequentially from bottom to top, each channel stack including a sacrificial layer and a channel layer on the sacrificial layer; an isolation layer is also formed on the substrate surrounding the protrusions and exposing the initial stacked structure. Multiple pseudo-gate structures spanning the initial stacked structure are formed on the isolation layer of the device cell region; Grooves are formed in the initial stacked structures on both sides of the pseudo-gate structure, and the remaining initial stacked structures are used as stacked structures. Source and drain doped layers are formed on the channel layer of the groove sidewall, and in the device cell region, the source and drain doped layers of the groove sidewall located between adjacent pseudo-gate structures are spaced apart; A source / drain plug is formed in contact with the source / drain doped layer, the source / drain plug covering the end surface of the source / drain doped layer along the extension direction of the channel layer; Remove the pseudo-gate structure to form a gate opening; Remove the sacrificial layer exposed by the gate opening to form a through trench; A gate structure is formed in the gate opening and the through-slot, the gate structure surrounding the channel layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the dummy gate structure and before forming the groove, the method for forming the semiconductor structure further includes: forming a gate sidewall on the sidewall of the dummy gate structure; In the step of forming the source / drain plug, the source / drain plug covers the gate sidewall and the end surface of the source / drain doped layer along the extension direction of the channel layer, and in the device cell region, the source / drain plug fills between the source / drain doped layers at the end of the channel layer in adjacent stacked structures and between adjacent gate sidewalls.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The source / drain plugs are formed after the source / drain doped layers are formed and before the dummy gate structure is removed. The method for forming the semiconductor structure further includes: after forming the dummy gate structure and before forming the groove, forming a gate sidewall on the sidewall of the dummy gate structure; The step of forming the source / drain plug includes: forming a source / drain plug on the protrusion that covers the sidewall of the gate sidewall and the end surface of the source / drain doped layer along the extension direction of the channel layer, and in the device cell region, the source / drain plug fills the groove and the gate sidewall of the adjacent pseudo-gate structure sidewall.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the gate structure, the source / drain plugs are formed; The method for forming the semiconductor structure further includes: forming a gate sidewall on the sidewall of the dummy gate structure after forming the dummy gate structure and before forming the groove; forming an interlayer dielectric layer on the isolation layer covering the gate sidewall and the source / drain doped layer after forming the source / drain doped layer and before removing the dummy gate structure; and forming source / drain contact holes in the interlayer dielectric layers on both sides of the gate structure after forming the gate structure and before forming the source / drain plug, thereby exposing the surface of the source / drain doped layer that is not in contact with the channel layer. The step of forming the source / drain plug includes: forming the source / drain plug in the source / drain contact hole.

15. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing a substrate, the number of channel layers in the initial stacked structure is multiple; In the step of forming the source / drain doped layers, the source / drain doped layers on the ends of adjacent channel layers in the same stacked structure are spaced apart; the source / drain plugs are also filled between the source / drain doped layers on the ends of adjacent channel layers in the same stacked structure.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, After forming the trench and before forming the source / drain doped layer in the trench, the method for forming the semiconductor structure further includes: etching a portion of the sacrificial layer along the extension direction of the channel layer, so that a trench is formed between adjacent channel layers and the sacrificial layer, or between the protrusion and the channel layer adjacent to the protrusion and the sacrificial layer; and forming an inner sidewall in the trench. In the step of forming the source / drain plug, the source / drain plug is in contact with the inner wall.

17. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing a substrate, the initial stacked structure contains a plurality of channel stacks; In the step of forming the source / drain doped layers, the source / drain doped layers on the ends of adjacent channel layers in the same stacked structure are in contact.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, In the same stacked structure, a recess is formed between the source and drain doped layers at the ends of adjacent channel layers; In the step of forming the source / drain plug, the source / drain plug is filled into the recess.

19. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the semiconductor structure further includes: forming a silicide layer on the exposed surface of the source / drain doped layer after forming the source / drain doped layer and before forming the source / drain plug; The source / drain plug covers the silicide layer.

20. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing the substrate, the isolation layer also exposes a portion of the sidewall of the protrusion; In the step of forming the groove, the groove is also located in the protrusion exposed by the insulating layer; The method for forming the semiconductor structure further includes, in the step of forming the source / drain doped layer, forming a bottom doped layer on the protrusions at the bottom and sidewalls of the trench; In the step of forming the source / drain plug, the source / drain plug contacts the top of the bottom doped layer and covers the end surface of the source / drain doped layer along the channel layer extension direction.

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