Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same. The semiconductor device includes a gallium nitride-based material layer; and a P-type gate structure including a P-type doped layer and a protective layer sequentially stacked on the gallium nitride-based material layer, the protective layer having a higher thermal stability than the P-type doped layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Gallium nitride material can form heterojunction with ternary alloy material (such as AlGaN, InGaN, InAlN, etc.), and the piezoelectric polarization and spontaneous polarization generated thereby can form high-concentration two-dimensional electron gas (2DEG) at the heterojunction interface formed by the gallium nitride material and the ternary alloy material. In order to deplete the 2DEG at the heterojunction interface to realize the normally-off characteristics of the corresponding device, a P-type gate technology can be used, that is, a P-type doped layer is arranged between the barrier layer and the cap layer to deplete the 2DEG. However, the surface of the P-type gate structure is easy to be damaged in the high-temperature annealing process, thereby introducing surface defects.

[0003] SUMMARY

[0004] Therefore, the present application provides a semiconductor device and a preparation method thereof, which solve the problem that the P-type gate structure is easy to introduce surface defects in the high-temperature annealing process.

[0005] The first aspect of the present application provides a semiconductor device, comprising: a gallium nitride-based material layer; and a P-type gate structure comprising a P-type doped layer and a protective layer which are sequentially stacked on the gallium nitride-based material layer, and the thermal stability of the protective layer is higher than that of the P-type doped layer. Since the thermal stability of the protective layer is higher than that of the P-type doped layer, the damage to the surface of the P-type gate structure in the high-temperature annealing process can be reduced by arranging the protective layer.

[0006] In one embodiment, the protective layer is an intrinsic semiconductor layer. By selecting an intrinsic semiconductor material with higher thermal stability than the P-type doped layer to form the protective layer, only a single film layer needs to be prepared on the P-type doped layer, and the process is simple and easy to implement.

[0007] In one embodiment, the material of the protective layer is AlGaN, and the semiconductor substrate of the P-type doped layer is GaN. The thermal stability of the protective layer formed by the AlGaN material is higher than that of the P-type doped GaN layer, so that the damage to the surface of the P-type gate structure in the high-temperature annealing process can be reduced by using the protective layer.

[0008] In one embodiment, the protective layer is a doped layer. The doped layer is used to form a protective layer with higher thermal stability than the P-type doped layer, so that the damage to the surface of the P-type gate structure in the high-temperature annealing process can be reduced by using the protective layer.

[0009] In one embodiment, the protective layer includes p-type impurities, and the concentration of p-type impurities in the protective layer is higher than that in the p-type doped layer. Utilizing a high concentration of p-type impurities to form a protective layer with higher thermal stability than the p-type doped layer allows for the reduction of surface damage to the p-type gate structure during high-temperature annealing.

[0010] In one embodiment, the concentration of p-type impurities in the protective layer is greater than 5E19 cm⁻³.

[0011] In one embodiment, the p-type impurities in the protective layer and the p-type doped layer are the same. By setting the p-type impurities in the protective layer and the p-type doped layer to be the same, the same impurity material source can be selected for the protective layer and the p-type doped layer during the fabrication of the semiconductor device, without the need to change the impurity material source, thereby simplifying the fabrication process and improving production efficiency.

[0012] In one embodiment, the semiconductor substrate of the protective layer and the semiconductor substrate of the p-type doped layer are made of the same material. By setting the semiconductor substrate in the protective layer and the p-type doped layer to be the same, the same intrinsic semiconductor material source can be selected for the protective layer and the p-type doped layer during the fabrication of the semiconductor device, without the need to change the intrinsic semiconductor material source, thereby simplifying the fabrication process and improving production efficiency.

[0013] In one embodiment, the semiconductor substrate of the protective layer is made of GaN.

[0014] In one embodiment, the protective layer includes an n-type impurity. By incorporating an n-type impurity into the protective layer, the Schottky barrier height between the protective layer and the first conductive structure above it (i.e., the gate) can be increased, thereby reducing gate leakage.

[0015] In one embodiment, the n-type impurity includes carbon.

[0016] In one embodiment, the concentration of carbon is greater than 1E17 cm⁻³.

[0017] In one embodiment, the semiconductor device further includes: a first conductive structure, a second conductive structure, and a third conductive structure, wherein the first conductive structure is located on the side of the protective layer away from the gallium nitride-based material layer, and the second and third conductive structures are located on the gallium nitride-based material layer and on both sides of the P-type gate structure, respectively.

[0018] A second aspect of this application provides a method for fabricating a semiconductor device, comprising: forming a p-type doped layer in a first region on the surface of a gallium nitride-based material layer; forming a protective layer on the p-type doped layer, wherein the thermal stability of the protective layer is higher than that of the p-type doped layer; and forming a first conductive structure, a second conductive structure, and a third conductive structure in a second region and a third region on the surface of the protective layer and the surface of the gallium nitride-based material layer, respectively.

[0019] According to the semiconductor device and its fabrication method provided in this application, by using a protective layer with higher thermal stability than the p-type doped layer to form the surface of the p-type gate structure, the surface damage caused by high-temperature annealing is reduced compared with directly using the p-type doped layer to form the surface of the p-type gate structure. Attached Figure Description

[0020] Figure 1 A schematic diagram of a semiconductor device provided for a first exemplary embodiment of this application.

[0021] Figure 2 A schematic diagram of a semiconductor device provided for a second exemplary embodiment of this application.

[0022] Figure 3 A schematic diagram of a semiconductor device provided for a third exemplary embodiment of this application.

[0023] Figure 4 A schematic diagram of a semiconductor device provided for a fourth exemplary embodiment of this application.

[0024] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical means, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings.

[0026] Figure 1 A schematic diagram of a semiconductor device provided for a first exemplary embodiment of this application. (As shown...) Figure 1 As shown, the semiconductor device 10 includes a gallium nitride-based material layer 11 and a p-type gate structure 12. The p-type gate structure 12 includes a p-type doped layer 121 and a protective layer 122 sequentially stacked on the gallium nitride-based material layer 11. The thermal stability of the protective layer 122 is higher than that of the p-type doped layer 121.

[0027] The p-type doped layer 121 refers to a semiconductor film layer doped with p-type impurities. The p-type doped layer 121 includes a semiconductor substrate and a p-type impurity, wherein the semiconductor substrate is an intrinsic semiconductor layer. The p-type impurity is represented by a hollow circle (hereinafter the same). In one embodiment, the material of the semiconductor substrate of the p-type doped layer 121 is selected from any one of GaN, AlGaN, InAlN, and AlN. In one embodiment, the p-type impurity of the p-type doped layer 121 is magnesium.

[0028] Thermal stability refers to the heat resistance of a material, that is, its ability to deform under the influence of temperature. The smaller the deformation, the higher the thermal stability. Since the thermal stability of the protective layer 122 is higher than that of the p-type doped layer 121, the deformation of the protective layer 122 during high-temperature annealing is less than that of the p-type doped layer 121. According to the semiconductor device provided in this embodiment, by using the protective layer 122 to form the surface of the p-type gate structure 12, compared to using the p-type doped layer 121 to form the surface of the p-type gate structure 12, surface defects of the p-type gate structure 12 can be reduced, and the surface flatness of the p-type gate structure 12 can be improved.

[0029] Gallium nitride-based materials refer to a class of compounds formed by Al, Ga, and In elements of Group IIIA and nitrogen elements of Group VA in the periodic table, such as AlGaN, GaN, InGaN, GaN, InAlGa, GaN, and InAlN. Gallium nitride-based material layer 11 refers to a composite film structure formed by stacking at least two of the above-mentioned gallium nitride-based materials.

[0030] According to the semiconductor device provided in this embodiment, by using a protective layer 122 with higher thermal stability than the p-type doped layer 121 to form the surface of the p-type gate structure 12, the surface damage caused by the p-type gate structure during high-temperature annealing is reduced, and the reliability of the device is improved.

[0031] In one embodiment, such as Figure 1 As shown, the protective layer 122 is an intrinsic semiconductor layer. In this case, the thermal stability of the protective layer 122 is higher than that of the p-type doped layer 121, meaning that the thermal stability of the intrinsic semiconductor layer is higher than that of the p-type doped layer 121. When the protective layer 122 is an intrinsic semiconductor layer, the protective layer 122 can be directly formed using an intrinsic semiconductor layer with higher thermal stability than the p-type doped layer 121, which reduces surface damage caused by high-temperature annealing and simplifies the fabrication process.

[0032] In this case, in one embodiment, the intrinsic semiconductor material forming the protective layer 122 and the semiconductor substrate material forming the p-type doped layer 121 are different. For example, the intrinsic semiconductor material forming the protective layer 122 is AlGaN, and the semiconductor substrate material of the p-type doped layer 121 is GaN.

[0033] Figure 2 A schematic diagram of a semiconductor device provided for a second exemplary embodiment of this application. Figure 2 As shown, semiconductor device 20 and Figure 1 The difference in the semiconductor device 10 shown is that the protective layer 222 is not an intrinsic semiconductor layer, but an n-type doped layer.

[0034] Specifically, such as Figure 2As shown, the protective layer 222 includes a semiconductor substrate and an n-type impurity, wherein the semiconductor substrate is an intrinsic semiconductor layer. The n-type impurity is represented by a solid circle (the same below). In this case, the thermal stability of the protective layer 222 is higher than that of the p-type doped layer 121. It can be the entire semiconductor substrate after incorporating the n-type impurity, that is, the thermal stability of the protective layer 222 is higher than that of the p-type doped layer 121; or it can be that the thermal stability of the semiconductor substrate of the protective layer 222 is higher than that of the p-type doped layer 121.

[0035] In one embodiment, the semiconductor substrate of the protective layer 222 is made of AlGaN. In one embodiment, the n-type impurity is carbon. In one embodiment, the concentration of carbon is greater than 1E17 cm⁻³.

[0036] According to the semiconductor device 20 provided in this embodiment, a protective layer 222 is formed by using an n-type doped layer. On the one hand, a protective layer 222 with higher thermal stability than the p-type doped layer 121 is obtained, thereby reducing surface damage to the p-type gate structure. On the other hand, the holes in the semiconductor substrate of the protective layer 222 are captured by the n-type impurities, reducing the hole concentration in the protective layer 222, thereby increasing the Schottky barrier height between the protective layer 222 and the first conductive structure 13, and further reducing the leakage current of the first conductive structure 13.

[0037] Figure 3 A schematic diagram of a semiconductor device provided for a third exemplary embodiment of this application. (As shown) Figure 3 As shown, semiconductor device 30 and Figure 2 The difference in the semiconductor device 20 shown is that the impurities in the protective layer 322 are p-type impurities. In this case, the thermal stability of the protective layer 322 is higher than that of the p-type doped layer 121. It can be the entire semiconductor substrate after p-type impurities are incorporated, that is, the thermal stability of the protective layer 322 is higher than that of the p-type doped layer 121; or it can be that the thermal stability of the semiconductor substrate of the protective layer 322 is higher than that of the p-type doped layer 121.

[0038] In one embodiment, the semiconductor substrate of the protective layer 322 and the semiconductor substrate of the p-type doped layer 121 are made of the same material. This eliminates the need to change the material source of the semiconductor substrate during the growth of the semiconductor device, simplifying the process. In one embodiment, the semiconductor substrate material of the protective layer 322 is selected from any one of GaN, AlGaN, InAlN, and AlN.

[0039] In one embodiment, the p-type impurities in the protective layer 322 and the p-type doped layer 121 are the same, for example, magnesium. This eliminates the need to change the impurity material source during the growth of the semiconductor device, simplifying the process. In one embodiment, the concentration of the p-type impurity in the protective layer 322 is greater than 5E19 cm⁻³.

[0040] In one embodiment, the semiconductor substrate of the protective layer 322 and the semiconductor substrate of the p-type doped layer 121 are made of the same material, and the p-type impurities in the protective layer 322 and the p-type doped layer 121 are the same, but the concentration of p-type impurities in the protective layer 322 is higher than that in the p-type doped layer 321. In this case, the semiconductor substrate of the p-type gate structure can be formed using the same material layer, and a doping gradient can be formed in the semiconductor substrate to obtain a p-type doped layer 121 with a lower doping concentration and a protective layer 322 with a higher doping concentration. Since the former has lower thermal stability than the latter, the protective layer 322 can be used to protect the entire p-type gate structure to reduce surface defects caused by high-temperature annealing.

[0041] According to the semiconductor device provided in this embodiment, a protective layer 322 is formed by using a p-type doped layer. On the one hand, a protective layer 322 with higher thermal stability than the p-type doped layer 121 is obtained, thereby reducing surface damage to the p-type gate structure. On the other hand, by selecting the same p-type impurity for the protective layer 322 and the p-type doped layer 121, there is no need to change the impurity source during the preparation process, thereby improving the preparation efficiency.

[0042] Figure 4 A schematic diagram of a semiconductor device provided for a fourth exemplary embodiment of this application. (As shown...) Figure 4 As shown, the protective layer 422 in the semiconductor device 40 includes both p-type and n-type impurities. In this case, the thermal stability of the protective layer 422 is higher than that of the p-type doped layer 121. It can be the entire semiconductor substrate doped with both p-type and n-type impurities, i.e., the protective layer 422, which has higher thermal stability than the p-type doped layer 121; it can also be the semiconductor substrate doped with p-type impurities, which has higher thermal stability than the p-type doped layer 121; or it can be the semiconductor substrate of the protective layer 422, which has higher thermal stability than the p-type doped layer 121.

[0043] In one embodiment, the semiconductor substrate of the protective layer 422 and the semiconductor substrate of the p-type doped layer 121 are made of the same material. The p-type impurities in the protective layer 422 and the p-type doped layer 121 are the same, but the concentration of the p-type impurities in the protective layer 422 is higher than that in the p-type doped layer 121. For example, the p-type impurity is magnesium. In one embodiment, the concentration of the p-type impurities in the protective layer 322 is greater than 5E19 cm⁻³.

[0044] In one embodiment, the n-type impurity is carbon. In one embodiment, the concentration of carbon is greater than 1E17cm⁻³.

[0045] According to the semiconductor device 40 provided in this embodiment, p-type impurities and n-type impurities are simultaneously doped into the semiconductor substrate to obtain a protective layer 422. On the one hand, a protective layer 422 with higher thermal stability than the p-type doped layer 121 is obtained, thereby reducing surface damage to the p-type gate structure. On the other hand, the n-type impurities can trap holes in the protective layer 422, thereby reducing the hole concentration in the protective layer 422. When the hole concentration in the protective layer 422 decreases, the Schottky barrier height between the protective layer 422 and the first conductive structure 13 can be increased, thereby reducing leakage current in the first conductive structure 13.

[0046] In the semiconductor device provided in any of the above embodiments, the gallium nitride-based material layer 11 includes a heterojunction 110, and the semiconductor structure 10 further includes a first conductive structure 13, i.e., a gate, stacked on the side of the p-type gate structure 12 away from the gallium nitride-based material layer 11. The p-type gate structure 12 disposed between the heterojunction 110 and the gate can consume the high concentration of two-dimensional electron gas at the heterojunction 110, thereby realizing the normally-off characteristic of the semiconductor device.

[0047] Specifically, with Figure 1 Taking the semiconductor device 10 as an example, the gallium nitride-based material layer 11 includes a substrate 111, and a channel layer 112 and a barrier layer 113 sequentially stacked on the substrate 111. The interface between the channel layer 112 and the barrier layer 113 forms a heterojunction 110. The substrate 111 includes any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate. In one embodiment, the material of the channel layer 112 is GaN, and the material of the barrier layer 113 is AlGaN. In one embodiment, the gallium nitride-based material layer 11 further includes a stop layer 114, i.e., a buffer layer, located between the substrate 111 and the channel layer 112. In one embodiment, the material of the stop layer 114 is GaN.

[0048] like Figure 1 As shown, based on the first conductive structure 13, the semiconductor device 10 further includes a second conductive structure 14 and a third conductive structure 15. The second conductive structure 14 and the third conductive structure 15 are stacked on the gallium nitride-based material layer 11, respectively disposed on both sides of the P-type gate structure 12, and are insulated from each other. The second conductive structure 14 and the third conductive structure 15 are used to form the source and drain, respectively.

[0049] In this embodiment, a metal with a high work function is used to fabricate the first conductive structure 13. For example, the first conductive structure 13 includes a stacked Ni metal layer and an Au metal layer. A metal with a low work function is used to fabricate the second conductive structure 14 and the third conductive structure 15. For example, the second conductive structure 14 and the third conductive structure 15 respectively include a stacked Ti metal layer, an Al metal layer, and a Ti metal layer.

[0050] According to the semiconductor device provided in this embodiment, the holes introduced by the P-type impurities in the p-type doped layer 121 are used to consume the 2DEG at the heterojunction 110 to achieve the normally-off characteristic of the corresponding device.

[0051] This application also provides a method for fabricating a semiconductor device. Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Figure 5 As shown, the semiconductor device fabrication method 500 includes:

[0052] Step S510: A p-type doped layer is formed in the first region on the surface of the gallium nitride-based material layer.

[0053] Step S520: A protective layer is formed on the p-type doped layer. The thermal stability of the protective layer is higher than that of the p-type doped layer.

[0054] In step S530, a first conductive structure, a second conductive structure, and a third conductive structure are formed on the surface of the protective layer and in the second and third regions on the surface of the gallium nitride-based material layer, respectively.

[0055] For example, for Figure 1 For the semiconductor device 10 shown, the semiconductor device fabrication method 500 specifically includes: according to step S510, in the reaction chamber of a metal-organic chemical vapor deposition (MOCVD) apparatus, firstly, a gallium nitride-based material layer 11 is grown on a substrate; secondly, a first semiconductor substrate is grown on the gallium nitride-based material layer 11, and p-type doping is performed simultaneously to obtain a p-type doped layer 121. Next, according to step S520, a second semiconductor substrate is grown in a first region on the p-type doped layer 121 to form a protective layer 122. The second semiconductor substrate is different from the first semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are selected from any one of GaN, AlGaN, InAlN, and AlN, respectively. In one embodiment, the first semiconductor substrate is GaN, and the second semiconductor substrate is AlGaN. Subsequently, a p-type gate structure is obtained by annealing activation. Finally, according to step S530, a first conductive structure 13 is prepared on the surface of the protective layer, and then a second conductive structure 14 and a third conductive structure 15 are prepared in the second and third regions on the surface of the gallium nitride-based material layer 11, respectively.

[0056] Figure 2 The fabrication process of the semiconductor device 20 shown is compared to Figure 1Regarding the fabrication process of the semiconductor device 10 shown, the only difference lies in step S520, where n-type doping is performed simultaneously with the growth of the second semiconductor substrate on the first region of the p-type doped layer 121 to form a protective layer 222. Subsequently, an annealing activation process is used to obtain a p-type gate structure. In this case, the second semiconductor substrate may be the same as or different from the first semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are selected from GaN, AlGaN, InAlN, and AlN, respectively. In one embodiment, the first semiconductor substrate is GaN, and the second semiconductor substrate is AlGaN. In another embodiment, both the first semiconductor substrate and the second semiconductor substrate are AlGaN.

[0057] For example, regarding Figure 3 For the semiconductor device 30 shown, the semiconductor device fabrication method 500 specifically includes: according to step S510, growing a semiconductor substrate on a gallium nitride-based material layer 11, and simultaneously performing p-type doping on the semiconductor substrate to obtain a p-type doped layer 121. According to step S520, continuing to grow the semiconductor substrate and increasing the p-type doping concentration to obtain a protective layer 322. Subsequently, annealing activation is performed to obtain a p-type gate structure. In this case, the second semiconductor substrate is the same as the first semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are respectively selected from GaN, AlGaN, InAlN, and AlN. In one embodiment, both the first semiconductor substrate and the second semiconductor substrate are AlGaN.

[0058] Figure 4 The fabrication process of the semiconductor device 40 shown is compared to Figure 3 The only difference in the fabrication process of the semiconductor device 30 shown is that while performing high-concentration p-type doping on the semiconductor substrate, n-type doping is also performed to obtain the protective layer 422. In this case, the second semiconductor substrate is the same as the first semiconductor substrate. The first and second semiconductor substrates are selected from GaN, AlGaN, InAlN, and AlN, respectively. In one embodiment, both the first and second semiconductor substrates are AlGaN. In one embodiment, the p-type impurities in the protective layer 422 and the p-type doped layer 121 are the same, but the concentration of p-type impurities in the protective layer 422 is higher than the concentration of p-type impurities in the p-type doped layer 121.

[0059] The semiconductor device fabrication method and the semiconductor device provided in the embodiments of this application belong to the same inventive concept. Details not specifically described in the fabrication method section can be found in the semiconductor device embodiments, and the same technical effects are achieved. They will not be repeated here.

[0060] It should be understood that the qualifying terms "first", "second", "third" and "fourth" used in the description of the embodiments of this application are only used to more clearly illustrate the technical solutions and are not intended to limit the scope of protection of this application.

[0061] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications or equivalent substitutions made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: Gallium nitride-based material layer; and The P-type gate structure includes a P-type doped layer and a protective layer sequentially stacked on the gallium nitride-based material layer, wherein the thermal stability of the protective layer is higher than that of the P-type doped layer. The protective layer includes p-type impurities and n-type impurities, and the n-type impurities include carbon.

2. The semiconductor device according to claim 1, characterized in that, The protective layer is made of AlGaN; the semiconductor substrate of the P-type doped layer is made of GaN.

3. The semiconductor device according to claim 1, characterized in that, The concentration of p-type impurities in the protective layer is higher than the concentration of p-type impurities in the p-type doped layer.

4. The semiconductor device according to claim 1, characterized in that, The concentration of the p-type impurity in the protective layer is greater than 5E19 cm⁻³.

5. The semiconductor device according to claim 1, characterized in that, The protective layer and the p-type doped layer contain the same p-type impurity; and / or The semiconductor substrate of the protective layer and the semiconductor substrate of the P-type doped layer are made of the same material.

6. The semiconductor device according to claim 5, characterized in that, The semiconductor substrate of the protective layer is made of GaN.

7. The semiconductor device according to claim 1, characterized in that, The concentration of carbon is greater than 1E17 cm⁻³.

8. The semiconductor device according to claim 1, characterized in that, It also includes a first conductive structure, a second conductive structure, and a third conductive structure; the first conductive structure is located on the side of the protective layer away from the gallium nitride-based material layer, and the second and third conductive structures are located on the gallium nitride-based material layer and on both sides of the P-type gate structure, respectively.

9. A method for fabricating a semiconductor device, characterized in that, include: A p-type doped layer is formed in the first region on the surface of the gallium nitride-based material layer; A protective layer is formed on the p-type doped layer, the protective layer having higher thermal stability than the p-type doped layer, wherein the protective layer includes p-type impurities and n-type impurities, and the n-type impurities include carbon elements; A first conductive structure, a second conductive structure, and a third conductive structure are formed on the surface of the protective layer and in the second and third regions on the surface of the gallium nitride-based material layer, respectively.

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