A distributed amplifier circuit adopting a current multiplexing structure and a unilateralization technique

Abstract

The present invention relates to the field of wireless communication technologies, and discloses a distributed amplifier circuit adopting a current reuse structure and a unilateralization technique, including a gate transmission line with a load having an impedance of Z o , a drain transmission line with a load having an impedance of Z o , and n gain units adopting a current reuse structure combined with a unilateralization technique. A first transistor M 1i is connected between the gate transmission line and the i-th gain unit. Before and after the connection point where the gate of each first transistor M 1i is connected to the gate transmission line, first sub-distributed inductors of L G / 2 are connected in series respectively. The drain of the first transistor M 1i is coupled with a first peaking inductor L D1 and a first distributed inductor downstream of the connection point where the gate transmission line is connected to the gate of the first transistor of this gain unit; the drain transmission line is connected to the i-th gain unit through the drain of a second transistor M 2i in series with a second peaking inductor L D2 . The present invention improves the gain of the distributed amplifier.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communication, and particularly to a distributed amplifier circuit adopting a current reuse structure and a unilateralization technique. Background Art

[0002] In applications such as optical communication, test instruments, software radio, broadband wireless communication, high-rate data transmission, and electronic countermeasure, a large number of broadband high-performance amplifiers are required. The distributed amplifier utilizes the parasitic capacitance of transistors combined with distributed inductance to construct an artificial transmission line, which can achieve a very wide bandwidth and is often used to design broadband amplifiers that meet the above bandwidth requirements. Common distributed amplifiers are divided into common-source distributed amplifiers and common-source-cascode distributed amplifier structures according to different gain unit circuits. Compared with the common-source amplifier unit, since the common-source-cascode amplifier unit circuit reduces the influence of the Miller capacitance and increases the voltage swing at the same time, the common-source-cascode distributed amplifier has higher gain bandwidth and output power capabilities than the common-source distributed amplifier. In order to further improve the performance of the distributed amplifier, some distributed amplifier circuits also improve the gain and bandwidth of the distributed amplifier by adopting gain units with smaller parasitic parameters including Darlington structures and introducing peaking inductors into traditional gain units. However, generally speaking, distributed amplifiers generally suffer from the deficiencies of low gain and high power consumption. Summary of the Invention

[0003] The present invention provides a distributed amplifier circuit adopting a current reuse structure and a unilateralization technique. By adopting the current reuse structure, the DC power consumption can be effectively reduced while the gain of the distributed amplifier is significantly improved; and by adopting the unilateralization technique, the high-frequency gain bandwidth of the distributed amplifier is expanded. As an alternative solution for a distributed amplifier, the present invention can effectively solve the problems of low gain, small gain bandwidth, and high DC power consumption existing in the existing distributed amplifier circuits.

[0004] The present invention is realized by the following technical solutions:

[0005] A distributed amplifier circuit adopting a current reuse structure and a unilateralization technique includes a gate transmission line with one end as a signal input end and the other end as a first grounding end (defined as the terminal of the gate transmission line) and a drain transmission line with one end as a signal output end and the other end as a second grounding end (defined as the terminal of the drain transmission line). Loads with an impedance of Z o are respectively connected in series to the gate transmission line at the first grounding end and the drain transmission line at the second grounding end. Between the gate transmission line and the drain transmission line, there are n gain units adopting a current reuse structure combined with a unilateralization technique. nis a positive integer greater than or equal to 2. The gate transmission line is the signal input transmission line. The gate transmission line is connected to the i th gain unit through a first transistor M 1i ; i = 1, 2… n The gate of the first transistor M 1i is connected to the gate transmission line. On the gate transmission line, in front of and behind the connection point where each first transistor M 1i is connected to the gate transmission line, there are first sub-distributed inductors with an inductance value of L G / 2 in series respectively. The two first sub-distributed inductors located between two gain units form a first distributed inductor L G ; Between the signal input end of the gate transmission line and the first distributed inductor adjacent to the signal input end of the gate transmission line, and between the load Z o provided at the terminal of the gate transmission line and the first sub-distributed inductor adjacent to the load Z o at the terminal of the gate transmission line, there are DC-blocking capacitors connected in series respectively C ; The drain transmission line is connected to the i th gain unit through the drain of a second transistor M 2i connected in series with a second peaking inductor L D2 ; i = 1, 2… n On the drain transmission line, in front of and behind the connection point where each second peaking inductor L D2 is connected to the drain transmission line, there are second sub-distributed inductors with an inductance value of L D / 2 in series respectively. The two second sub-distributed inductors located between two gain units form a second distributed inductor L D ; Between the signal output end of the drain transmission line and the second sub-distributed inductor adjacent to the signal output end of the drain transmission line, and between the load provided at the terminal of the drain transmission line and the second sub-distributed inductor adjacent to the load at the terminal of the drain transmission line, there are DC-blocking capacitors C connected in series respectively.

[0006] As an optimization, each gain unit includes a first transistor M 1i and a second transistor M2i The drain of the first transistor M 1i and the source of the second transistor M 2i are sequentially connected in series with a first peaking inductor L D1 and a choke inductor L 1.

[0007] As an optimization, the gate of the second transistor M 2i is connected to the connection point between the first peaking inductor L D1 and the choke inductor L 1 through a series-connected first capacitor C 1.

[0008] As an optimization, the drain of the second transistor M 2i is connected to the drain transmission line through a series-connected second peaking inductor L D2 .

[0009] As an optimization, the source of the first transistor M 1i is grounded.

[0010] As an optimization, the source of the second transistor M 2i is grounded through a series-connected second capacitor C 2.

[0011] The signal is output from the drain of the first transistor and passes through the first peaking inductor L D1 . Due to the presence of the choke inductor L 1, the signal will not enter the source of the second transistor M 2i but is coupled to the gate of the second transistor through the first capacitor C 1. The first capacitor C 1 is introduced to ensure that the second transistor is biased in a specific state. The first capacitor C 1 is essentially a DC-blocking capacitor. A second capacitor M 2i is provided at the source of the second transistor C 2. The second capacitor C 2 provides a RF ground for the RF signal. Therefore, the signal passes from the second transistor M 2iAfter the signal enters the gate, it is equivalent to a common-source amplifier. Under the same conditions, the gain of the common-source amplifier is greater than that of the common-gate amplifier. Therefore, the gain unit proposed by the present invention can achieve a higher gain compared to the existing cascode gain unit.

[0012] As an optimization, in the gain unit that is not close to the terminal of the gate transmission line, the first peaking inductor L D1 is coupled with the first distributed inductor downstream of the connection point where the gate transmission line is connected to the gate of the first transistor of this gain unit M 1i . In the gain unit close to the terminal of the gate transmission line, the first peaking inductor L G is coupled with the first sub-distributed inductor downstream of the connection point where the gate transmission line is connected to the gate of the first transistor of this gain unit L D1 . M 1i L G

[0013] Due to the parasitic capacitance, i.e., the Miller capacitance, between the gate and the drain of the first transistor M 1i , after the signal is amplified by the first transistor M 1i and reaches the drain of the first transistor, it will feedback to the signal input end through the Miller capacitance, and the signal at the signal input end will also directly feed forward to the signal output end (the drain of the first transistor M 1i ) without being amplified by the first transistor through the Miller capacitance. Because the Miller capacitance is relatively small and has a greater impact on high-frequency signals, both the negative feedback and the feed forward will affect the high-frequency gain of the amplifier. However, the present invention can effectively solve the influence brought by the Miller capacitance through the unilateralization technique (the first peaking inductor at the drain of the first transistor L D1 is coupled with the first distributed inductor downstream of the connection point where the gate of this first transistor is connected to the gate transmission line L G ). Specifically, the introduced first peaking inductor L D1 can reduce the signal directly feeding forward from the input end to the output end, thus weakening the reduction of the amplifier gain caused by the feed forward; at the same time, the first peaking inductor L D1 can couple the signal that is amplified by the first transistor and feedback to the signal input end through the Miller capacitance to the first distributed inductor downstream of the connection point where the gain unit is connected to the gate transmission line L G, thus avoiding the decrease in high-frequency gain caused by negative feedback; and the part of the signal coupled to the first distributed inductor L G can be further amplified by the subsequent gain unit, and finally the high-frequency gain is improved.

[0014] As an optimization, the gate of the second transistor M 2i is connected to the bias voltage R g2 through a series bias resistor V g2 .

[0015] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0016] The present invention adopts an amplifier unit circuit with a two-stage common-source current reuse structure, combined with a peaking inductor, to achieve the purpose of high gain and low power consumption (current reuse of the first transistor and the second transistor); at the same time, a unilateralization technique is adopted to expand the high-frequency gain bandwidth of the distributed amplifier. The present invention can effectively solve the problems of low gain and small gain bandwidth existing in the existing distributed amplifier circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0018] Figure 1 is a schematic diagram of a distributed amplifier circuit adopting a current reuse structure and a unilateralization technique according to the present invention;

[0019] Figure 2-1 is Figure 1 the circuit schematic diagram of the gain unit in

[0020] Figure 2-2 (with arrows indicating the signal flow);

[0021] Figure 3 is the circuit schematic diagram of an existing cascode gain unit with a peaking inductor (with arrows indicating the signal flow);

[0022] Figure 4 is the circuit schematic diagram of an existing common-source distributed amplifier circuit;

[0023] Figure 5Schematic diagram of an existing cascode distributed amplifier circuit with peaking inductors;

[0024] Figure 6 For a 4-stage ( n =4) cascode distributed amplifier circuit with peaking inductors;

[0025] Figure 7 For a 4-stage ( n =4) gain response curve of a cascode distributed amplifier with peaking inductors;

[0026] Figure 8 For a 4-stage ( n =4) schematic diagram of a current-reused structure distributed amplifier circuit;

[0027] Figure 9 For a 4-stage ( n =4) gain response curve of a current-reused structure distributed amplifier circuit;

[0028] Figure 10 Comparison chart of gain response curves for Case 1 and Case 2;

[0029] Figure 11 For a 4-stage ( n =4) schematic diagram of a distributed amplifier circuit using a current-reused structure and unilateralization technology;

[0030] Figure 12 For a 4-stage ( n =4) gain response curve of a distributed amplifier circuit using a current-reused structure and unilateralization technology;

[0031] Figure 13 Comparison chart of gain response curves for Case 1, Case 2, and Case 3. Detailed implementation manners

[0032] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below in conjunction with embodiments and the accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and do not limit the present invention.

[0033] Before describing the specific embodiments, it should be noted that the upstream and downstream directions in the present invention are represented according to the arrow directions in Figure 1 . The direction towards the arrow is the downstream direction, that is, the left in Figure 1 is the upstream direction, and the right is the downstream direction.

[0034] Next, the specific technology of the present invention will be introduced.

[0035] As shown in Figure 1As shown in the figure, a distributed amplifier circuit adopting a current multiplexing structure and unidirectional technology includes a gate transmission line with one end as a signal input end and the other end as a first grounding end, and a drain transmission line with one end as a signal output end and the other end as a second grounding end. A load with an impedance of Z o is connected in series to the gate transmission line located at the first grounding end and the drain transmission line located at the second grounding end respectively. Between the gate transmission line and the drain transmission line, there are n gain units adopting a current multiplexing structure combined with unidirectional technology. n is a positive integer greater than or equal to 2. The gate transmission line is the signal input transmission line. The gate transmission line is connected to the i th M 1i gain unit through a first transistor i = 1, 2... n . The gate of the first transistor M 1i is connected to the gate transmission line. On the gate transmission line, in front of and behind the connection point where each first transistor M 1i is connected to the gate transmission line, a first sub-distributed inductor with an inductance value of L G / 2 is connected in series respectively. Two first sub-distributed inductors located between two gain units form a first distributed inductor L G ; Between the signal input end of the gate transmission line and the first sub-distributed inductor adjacent to it (the signal input end of the gate transmission line), and between the load Z o set at the terminal of the gate transmission line and the first sub-distributed inductor adjacent to it (the load Z o at the terminal of the gate transmission line), a DC-blocking capacitor is connected in series respectively C ; The drain transmission line is connected to the i th M 2i gain unit through the drain of a second transistor and a second peaking inductor L D2 connected in series. i = 1, 2... n . On the drain transmission line, in front of and behind the connection point where each second peaking inductor L D2 is connected to the drain transmission line, a second sub-distributed inductor with an inductance value of L D / 2 is connected in series respectively. Two second sub-distributed inductors located between two gain units form a second distributed inductorL D ; A DC-blocking capacitor is serially connected between the signal output terminal of the drain transmission line and the second distributed inductor adjacent thereto (the signal output terminal of the drain transmission line), and between the load provided at the terminal of the drain transmission line and the second sub-distributed inductor adjacent thereto (the load at the terminal of the drain transmission line). C .

[0036] Specifically, each of the gain units includes a first transistor M 1i and a second transistor M 2i . The drain of the first transistor M 1i is serially connected with a first peaking inductor M 2i and a choke inductor L D1 1 in sequence between the source of the second transistor L 1. The gate of the first transistor M 1i is connected to the gate transmission line. Between the drain of the first transistor M 1i and the source of the second transistor M 2i , a first peaking inductor L D1 and a choke inductor L 1 are serially provided in sequence. In the gain unit that is not close to the terminal of the gate transmission line, the first peaking inductor L D1 is coupled to the first distributed inductor M 1i downstream of the connection point where the gate transmission line is connected to the gate of the first transistor L G of this gain unit. In the gain unit that is close to the terminal of the gate transmission line, the first peaking inductor L D1 is coupled to the first sub-distributed inductor M 1i downstream of the connection point where the gate transmission line is connected to the gate of the first transistor L G of this gain unit. The upstream and downstream of the connection point are described based on the signal transmission direction. The upstream is the signal input terminal, and the downstream is the signal output terminal. One end of the first peaking inductor L D1 far from the first transistor M 1i is connected to the first capacitor COne end of 1 is connected, and the first capacitor C The other end of 1 is connected to the gate of the second transistor M 2i The source of the first transistor M 1i is grounded. The drain of the second transistor M 2i is connected to the drain transmission line through a series-connected second peaking inductor L D2 The gate of the second transistor M 2i is connected to the bias voltage through a series-connected bias resistor R g2 The source of the second transistor V g2 is grounded through a series-connected second capacitor M 2i 2. C As shown in

[0037] is the unit circuit schematic diagram of a distributed amplifier circuit adopting the unidirectionalization technology proposed by the present invention. Figure 2-1 In Figure 2-1 the first transistor M 1i and the second transistor M 2i both operate in the common-source amplifier state. The AC signal behaves as follows: The signal is input from the gate of the first transistor M 1i and amplified to reach the drain of the first transistor M 1i At the drain of the first transistor M 1i due to the resonance of the first peaking inductor L D1 and the parasitic capacitance between the drain and source of the first transistor M 1i the high-frequency gain will be enhanced; The signal passing through the first peaking inductor L D1 is divided into two parts:

[0038] One part of the signal is coupled to the first distributed inductor adjacent to the downstream of the first transistor through the first peaking inductor L D1 where M 1i is the coupling coefficient between the first peaking inductor Figure 2-1 and the first distributed inductor (or the first sub-distributed inductor). Since the first transistor k is the first peaking inductor L D1 and the coupling coefficient between the first distributed inductor (or the first sub-distributed inductor), due to the first transistorM 1i There is a parasitic capacitance between the gate and the drain of M 1i the first transistor, and the signal transmitted to the drain of the first transistor M 1i will be negatively fed back to the gate of the first transistor through this parasitic capacitance, resulting in a roll-off of the high-frequency gain of the gain cell, thereby reducing the high-frequency gain bandwidth of the gain cell. In the present invention, the signal transmitted to the M 1i drain of the first transistor passes through the first peaking inductor L D1 and is coupled to the first distributed inductor (or the first sub-distributed inductor), which can prevent the M 1i drain signal of the first transistor from being negatively fed back to the gate of the first transistor M 1i and causing a reduction in the gain bandwidth, thereby realizing the unidirectional technology of the current signal. Therefore, the distributed amplifier adopting the unidirectional technology proposed by the present invention has a higher gain bandwidth than the traditional distributed amplifier.

[0039] Another part of the signal is coupled from the first capacitor C 1 to the gate of the second transistor M 2i and, after being further amplified by the second transistor M 2i it reaches the drain of the second transistor M 2i The second peaking inductor at the drain of the second transistor M 2i resonates with the parasitic capacitance from the drain to the source of the second transistor L D2 and the high-frequency gain will be enhanced. The signal enters the drain transmission line after passing through the second peaking inductor M 2i D2 L D2 D1 L D1 and a choke inductor is provided between the first peaking inductor M 2i and the second transistor L 1 D1 L D1 to prevent the signal passing through the first peaking inductor M 2i from entering the source of the second transistor C 2 serves to provide an AC ground, enabling the second transistor M 2i to operate in a common-source amplification state.

[0040] Figure 2-2 The circuit schematic diagram of a cascode gain cell with a peaking inductor and signal flow indication. For the cascode gain cell with a peaking inductor, after the signal comes out from the drain of the first transistor, it directly enters the source of the second transistor through the first peaking inductor. That is to say, the signal in the second transistor belongs to the amplification of a common-gate amplifier. However, for the gain cell proposed in the present invention, due to the existence of the choke inductor, after the signal comes out from the first transistor and passes through the first peaking inductor, the signal will not directly enter the source of the second transistor, but is capacitively coupled to the gate of the second transistor through the first capacitor. A second capacitor is provided at the source of the second transistor, which can provide a radio frequency ground for the radio frequency signal. Therefore, after the signal of the present invention enters from the gate of the second transistor, the signal belongs to the common-source amplification. Under the same conditions, the gain of the common-source amplifier is larger than that of the common-gate amplifier. Therefore, the gain cell proposed in the present invention can achieve a higher gain compared with the common-gate amplifier. It should be noted that the current multiplexing structure in the present invention is from the perspective of direct current, that is, the first transistor and the second transistor share the direct current.

[0041] For a distributed amplifier, starting from the signal input, the signal reaching the input of the gain cell becomes weaker as the distance from the input end increases. The main reason is that as the distance increases, the signal gradually enters each gain cell. Therefore, the signal allocated to the gain cell located behind the transmission line will become less and less. At the same time, the transmission line itself also has losses, which further reduces the input signal of the subsequent gain cells.

[0042] The specific principle is as follows:

[0043] Due to the parasitic capacitance, namely the Miller capacitance, between the gate and the drain of the first transistor M 1i After the signal is amplified by the first transistor M 1i and reaches the drain of the first transistor, it will be negatively fed back to the signal input end through the Miller capacitance. And the signal at the signal input end will also not be amplified by the first transistor, but directly fed forward to the signal output end (the drain of the first transistor M 1i ) through the Miller capacitance. Because the Miller capacitance is relatively small and has a greater impact on high-frequency signals, both negative feedback and feedforward will affect the high-frequency gain of the amplifier. The present invention effectively solves the influence brought by the Miller capacitance through the unilateralization technique (the first peaking inductor at the drain of the first transistor L D1 is coupled with the first distributed inductor L G (or the first sub-distributed inductor) downstream of the connection point where the gate-to-gate transmission line of the first transistor is connected). Specifically, it is manifested as: the introduced first peaking inductor LD1 The signal directly fed forward from the input end to the output end can be reduced, which can weaken the reduction of the amplifier gain caused by feedforward; meanwhile, the first peaking inductor L D1 can couple the signal that is amplified by the first transistor and negatively fed back to the signal input end through the Miller capacitance to the first distributed inductor downstream of the connection point between the gain unit and the gate transmission line L G (or the first sub-distributed inductor), thus avoiding the decrease of the high-frequency gain caused by negative feedback; and the part of the signal coupled to the first distributed inductor L G can be further amplified by the subsequent gain units, ultimately achieving the purpose of enhancing the high-frequency gain.

[0044] Figure 3 is the circuit schematic diagram of the existing common-source distributed amplifier, Figure 4 is the circuit schematic diagram of the existing common-source-cascode distributed amplifier, Figure 5 is the circuit schematic diagram of the common-source-cascode distributed amplifier with peaking inductors.

[0045] In order to prove the effectiveness of the present invention and to make the technical solutions and advantages of the present invention clearer. The following further illustrates the present invention in combination with three implementation cases based on the GaAs pHEMT process. The illustrative implementation manners of the present invention and their descriptions are only used to explain the present invention and do not limit the present invention. Distributed circuits implemented using the circuit structure units disclosed in the present invention based on other processes (such as CMOS and BiCMOS, etc.) also fall within the scope of the appended claims of this application.

[0046] Implementation Case One:

[0047] This Implementation Case One is a 4-stage common-source-cascode distributed amplifier with peaking inductors ( Figure 5 in n = 4), and its circuit structure is as shown in Figure 6 , Figure 7 and the gain response curve of this distributed amplifier is given, and the average gain of the amplifier (gain unit) is 10 dB.

[0048] Implementation Case Two:

[0049] The implementation purpose of Case Two is to highlight through performance comparison with Case One that the current reuse structure introduced in the present invention is different from the existing common-source-cascode gain unit, and it can significantly enhance the gain of the distributed amplifier.

[0050] This Implementation Case Two is a distributed amplifier circuit with a 4-stage current reuse structure gain unit with peaking inductors ( Figure 1China n = 4, but without introducing the unidirectional technology), the circuit structure is as Figure 8 shown. Figure 9 The gain response curve of the distributed amplifier is given, and the average gain of the amplifier is 20 dB. Figure 10 The gain response comparison curves of the distributed amplifiers in Case 1 and Case 2 are given. It can be seen that the gain of Case 2 is about 10 dB higher than that of Case 1. The following conclusions can be drawn from Case 1 and Case 2: 1) The gain unit of the current multiplexing structure with peaking inductance introduced in the present invention is different from the signal amplification process of the existing cascode distributed gain unit with peaking inductance. In the gain unit of the present invention, the signal is equivalently amplified by two common-source amplifiers; while in the existing cascode gain unit, the signal is amplified by a common-source amplifier and a common-gate amplifier in sequence; 2) Since each stage of the common-source amplifier of the common-source needs to be powered separately, therefore, two stages of the common-source amplifier require twice the current of the distributed amplifier current to be powered. The two common-source amplifiers in the gain unit of the current multiplexing structure with peaking inductance introduced in the present invention adopt the current multiplexing structure to achieve the multiplexing of the DC current, which is equivalent to only using one-fold current to supply two stages of the common-source amplifier, thus effectively reducing the DC power consumption of the circuit; 3) Adopting the gain unit of the current multiplexing structure with peaking inductance introduced in the present invention can significantly improve the gain of the distributed amplifier (from 10 dB to 20 dB).

[0051] Case 3:

[0052] This Case 3 is an improvement based on Case 2, that is, the unidirectional technology is introduced on the basis of Case 2, aiming to prove that the introduced unidirectional technology can significantly expand the high-frequency gain bandwidth of the distributed amplifier. Combining with Case 1 to prove the effectiveness of the structure and technology proposed in the present invention in improving the performance of the distributed amplifier.

[0053] Specifically, Case 3 is a distributed amplifier that adopts a 4-stage gain unit of the current multiplexing structure and unidirectional technology proposed in the present invention ( Figure 1 China n = 4), the circuit structure is as Figure 11 shown. Figure 12 The gain response curve of the distributed amplifier is given, and the gain of the amplifier is 19 dB, which is basically the same as that of Case 2. Figure 13 The gain response comparison curves of the distributed amplifiers in Case 1, Case 2 and Case 3 are given.

[0054] By Figure 13Comparisons of the gain response curves of Case 1, Case 2, and Case 3 can lead to the following conclusions: 1) By comparing the response curves of Case 1 and Case 2, the current reuse structure gain unit introduced in the present invention, at the cost of sacrificing a small amount of high-frequency gain bandwidth (decreasing by about 2.5 GHz compared to Case 1), significantly improves the gain of the distributed amplifier (increasing from 10 dB to about 20 dB) compared to the cascode gain unit distributed amplifier with a similar structure, which proves the effectiveness of the current reuse structure introduced in the present invention in improving the gain of the distributed amplifier; 2) By comparing the response curves of Case 2 and Case 3, the unilateralization technique introduced in the present invention, at the cost of sacrificing a small amount of gain (about 1 dB), significantly improves the high-frequency gain bandwidth of the distributed amplifier (increasing by about 5 GHz compared to Case 2), which proves the effectiveness of the unilateralization technique introduced in the present invention in improving the high-frequency gain bandwidth of the distributed amplifier; 3) By comparing the response curves of Case 1 and Case 3, the distributed amplifier proposed in the present invention achieves higher gain without deteriorating the high-frequency gain bandwidth compared to the existing cascode distributed amplifier with a similar structure; this proves the effectiveness of the present invention patent in improving the performance of the distributed amplifier.

[0055] Therefore, in summary, by adopting the current reuse structure in the present invention, the DC power consumption can be effectively reduced while the gain of the distributed amplifier is significantly improved; and by adopting the unilateralization technique, the high-frequency gain bandwidth of the distributed amplifier is expanded.

[0056] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above description is only the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A distributed amplifier circuit adopting a current multiplexing structure and unidirectionalization technology, characterized in that including a gate transmission line with a load having a terminal impedance of Z o , a drain transmission line with a load having a terminal impedance of Z o , and n gain units using a current multiplexing structure combined with a unilateralization technique, where n is an integer not less than 2. A first transistor M 1i is connected between the gate transmission line and the i-th gain unit, i = 1, 2... n. The gate of the first transistor M 1i is connected to the gate transmission line, and on the gate transmission line, before and after the connection point where the gate of each first transistor M 1i is connected to the gate transmission line, a first sub-distributed inductor of L G / 2 is serially connected respectively. Two first sub-distributed inductors located between two gain units form a first distributed inductor L G ; a DC-blocking capacitor C is serially connected respectively between the signal input end of the gate transmission line and the adjacent first sub-distributed inductor, and between the load provided at the terminal of the gate transmission line and the adjacent first sub-distributed inductor; The drain transmission line and the i-th gain unit are connected in series through the drain of the second transistor M 2i to a second peaking inductor L D2 , where i = 1, 2... n. On the drain transmission line, before and after the connection point of each second peaking inductor L D2 and the drain transmission line, a second sub-distributed inductor of L D / 2 is connected in series respectively. The two second sub-distributed inductors located between two gain units form a second distributed inductor L D ; A DC-blocking capacitor C is connected in series between the signal output end of the drain transmission line and the adjacent second sub-distributed inductor, and between the load provided at the terminal of the drain transmission line and the adjacent second sub-distributed inductor respectively; Each of the gain units includes a first transistor M 1i and a second transistor M 2i . A first peaking inductor L 1i is serially connected between the drain of the first transistor M 2i and the source of the second transistor M D1 in sequence, and a choke inductor L1; In the gain cell that is not near the terminal of the gate transmission line, the first peaking inductor L D1 is coupled with the first distributed inductor L 1i downstream of the connection point where the gate transmission line is connected to the gate of the first transistor M G of this gain cell. In the gain cell near the terminal of the gate transmission line, the first peaking inductor L D1 is coupled with the first sub-distributed inductor L 1i downstream of the connection point where the gate transmission line is connected to the gate of the first transistor M G of this gain cell; The second transistor M 2i has its gate connected to the connection point between the first peaking inductor L D1 and the choke inductor L1 through a series-connected first capacitor C1; The second transistor M 2i has its drain connected to the drain transmission line through a series-connected second peaking inductor L D2 ; The first transistor M 1i has its source grounded.

2. The distributed amplifier circuit adopting a current multiplexing structure and a unidirectionalization technique according to claim 1, wherein The source electrode of the second transistor M 2i is grounded through a second capacitor C2 connected in series.

3. The distributed amplifier circuit adopting a current multiplexing structure and unilateralization technology according to claim 1, characterized in that The second transistor M 2i has its gate connected to a bias voltage V g2 through a series bias resistor R g2 .

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