Fast common mode recovery circuit and method for burst mode limiting amplifier

Abstract

The application provides a low-cost design scheme suitable for common-mode recovery of burst-mode limiting amplifier. The method of variable time constant can shorten the common-mode recovery time to 14 ns, meeting the requirements of passive optical network. The design is simple and feasible, which not only retains the advantages of simple design of alternating current coupling of front and rear stages, but also avoids the long common-mode recovery time caused by alternating current coupling in the burst-mode limiting amplifier, which is difficult to meet the index requirements of the loop working speed better than 25.6 ns in the burst-mode limiting amplifier.

Description

Technical Field

[0001] The invention relates to a fast common mode recovery method and a circuit of a burst mode limiting amplifier. Background Art

[0002] With the rapid development of fiber-optic access technology, Passive Optical Network (PON) technology has become the mainstream of global access networks. Currently, upstream communication in PONs—that is, from the optical network unit (ONU) to the optical line terminal (OLT)—is quite difficult because multiple users share the same fiber. Only one user can transmit a data packet to the OLT at any given time. The Time Division Multiple Access (TDMA) protocol can be used to ensure this. This requires the ONU to be off when not transmitting a signal and quickly turn on when transmitting. This requires the ONU to support specialized burst-mode transmitters and receivers. Therefore, upstream access is crucial to system design, and burst-mode transceivers are both a key and challenging aspect of the entire system. In the OLT, the laser driver (LDD) operates in continuous mode, while the transimpedance amplifier (TIA) and limiting amplifier (LA) must support burst mode. In the general configuration of passive optical networks, some chips need to use burst mode, such as BM-TIA (burst mode transimpedance amplifier), BM-LA (burst mode limiting amplifier) ​​and BM-LDD (burst mode laser driver).

[0003] like Figure 1 Due to the different physical distances between different optical network units (ONUs), which leads to different link losses, the burst signals received by the optical line terminal (OLT) have significant differences in both intensity and common mode.

[0004] Figure 2This is a block diagram of an OLT receiver implementation in a conventional passive optical network. It primarily consists of modules such as an avalanche photodiode (APD) (not shown), a burst-mode transimpedance amplifier (BM-TIA) (not shown), and a burst-mode limiting amplifier (BM-LA). The APD converts the optical signal into a current signal; the BM-TIA converts the current signal into a voltage signal; and the BM-LA further amplifies the voltage signal to a limiting state. In traditional simple alternating current (AC) coupling, the common-mode recovery time and low-frequency energy loss of the signal are mutually constrained in a BM-LA receiver, resulting in a trade-off between efficiency and accuracy. Traditional direct current offset calibration (DCOC) feedback loops typically have loop bandwidths in the MHz or even kHz range, resulting in calibration times of tens to hundreds of microseconds. However, the long-term target for common-mode recovery time for PON protocols is less than 25.6 ns. Therefore, high-speed common-mode recovery and high-speed offset calibration in BM-LA design pose great challenges.

[0005] One solution is to use resistance-capacitance (RC) averaging to control the common-mode recovery time to 150 ns. Another approach uses direct current (DC) coupling and variable-bandwidth direct current offset calibration (DCOC) to further shorten the common-mode recovery time to 75 ns. Yet another approach uses DC coupling and a high-speed analog-to-digital converter (ADC) to shorten the common-mode recovery time for burst signals to 2.24 ns. However, the DCOC loop in this solution requires a clock source of up to 6.25 GHz, and both the digital circuitry and the digital-to-analog converter (DAC) in the DCOC loop must operate at 6.25 GHz. This design is extremely difficult, requires high process requirements, and is costly, making it unsuitable for low-cost passive optical network receiver designs.

[0006] Some relevant references are as follows:

[0007] [1] Li Qiang, Yin Aihan, Wang Zefan, et al. GPON security encryption optimization mechanism and implementation based on AES[J]. Optical Communication Technology, 2016, 40(07): 9-12.

[0008] [2] 10-Gigabit-capable passive optical network (XG-PON) systems[J].ITU-T Recommendation G.987 series.

[0009] [3] BACA R, ZUHDI M. Technological challenges to g-pon operation[C], 2008 Conference on Optical Fiber Communication / National Fiber Optic Engineers Conference (OFC / NFOEC 2008), 24-28 Feb. 2008,. San Diego, CA, USA. 02 2008.

[0010] [4] Hara, Kimura S, Nakamura H, et al. Ultra fast response ac-coupledburst-mode receiver with high sensitivity and wide dynamic range for 10g-eponsystem[J]. IEICE Transactions, vol. 94-B, pp. 1845–1852, 07 2011.

[0011] [5] Yin X, Qiu XZ, Gillis J, et al. Experiments on a 10 gb / s fast-settling high-sensitivity burst-mode

[0012] receiver with on-chip auto-reset for 10g-gpons[J]. Journal of OpticalCommunications and Networking, vol. 4, pp. B68–B76, 11 2012.

[0013] [6] Chen K C, Emami A. A 25-gb / s avalanche photodetector-based burst-mode optical receiver with 2.24-ns reconfiguration time in 28-nm cmos[J].IEEE Journal of Solid-State Circuits, vol. 54, pp. 1–12, 03 2019.

[0014] [7] Han S, Lee M S, Burst-mode penalty of ac-coupled opticalreceivers optimized for 8b / 10b line code[J], IEEE Photonics TechnologyLetters, vol. 16, pp. 1724 – 1726, 08 2004.

[0015] [8] Rotem E, Sadot D. Performance analysis of ac-coupled burst-modereceiver for fiber-optic burst switching networks[J], IEEE Transactions onCommunications, vol. 53, pp. 899 – 904, 06 2005.

[0016] [9] FAN X, SUN Y, FENG Y. A cmos dc offset cancellation (doc) circuitfor pga of low if wireless receivers[C]. in 2010 International Symposium onSignals, Systems and Electronics, 17-20 Sept. 2010, Nanjing, China. 2010, pp.1–4.

[0017]

[10] Coudyzer G, Ossieur P, Bauwelinck J, et al. A 25gbaud pam-4linear burst-mode receiver with analog gain- and offset control in 0.25msige:c bicmos, IEEE Journal of Solid-State Circuits, vol. 55, pp. 1–1, 042020.

[0018]

[11] Lee SH, Kim J, Le Q, et al. A single chip 2.5-gb / s burst-mode optical receiver with wide dynamic range. IEEE Photonics Technology Letters, vol. 23, pp. 85 – 87, 02 2011. Summary of the Invention

[0019] The present invention aims to provide a low-cost design for common-mode recovery in burst-mode limiting amplifiers. By using a variable time constant, the common-mode recovery time can be shortened to 14 ns, meeting the requirements of passive optical networks and suitable for burst-mode systems.

[0020] The specific technical solution for achieving the purpose of the present invention is:

[0021] A fast common-mode recovery circuit for a burst mode limiting amplifier includes three parts: a dynamic time constant control unit (RC_CONTROL), a limiting amplifier (LA), and a direct current offset calibration (DCOC) feedback loop.

[0022] The common-mode recovery time of AC coupling in burst-mode limiting amplifiers and the loss of low-frequency signal energy are mutually constrained, creating a trade-off between efficiency and accuracy. Traditional continuous-mode DCOC feedback loops typically have loop bandwidths in the MHz or even kHz range, making the loop operating speed unable to meet the required 25.6 ns.

[0023] In the present invention, the inventors uniquely designed a dynamic time constant control unit (RC_CONTROL) having signal input terminals In+ and In-, which are respectively connected to the signal input terminal of a limiting amplifier (LA) through two identical capacitors C. A first resistor R and a first controllable switch are connected in parallel between the signal input terminal In+ of the dynamic time constant control unit (RC_CONTROL) and the input common-mode voltage terminal through the capacitor C. A second resistor R and a second controllable switch are connected in parallel between the signal input terminal In- of the dynamic time constant control unit (RC_CONTROL) and the input common-mode voltage terminal through the capacitor C. The control terminals of the first controllable switch and the second controllable switch are both connected to an OR gate (OR) circuit, and the two signal input terminals of the OR gate (OR) circuit are respectively connected to a reset terminal (RST, Reset) and a DOC_ON terminal of a DC offset calibration (DCOC) feedback loop.

[0024] A fast common mode recovery method for a burst mode limiting amplifier (BM-LA) is based on the fast common mode recovery circuit of the burst mode limiting amplifier. Figure 3 As shown in the figure, the reset signal RST (active high) forces the first and second controllable switches to conduct, short-circuiting the first and second resistors. The equivalent resistance is approximately the on-resistance of the controllable switches. This value is typically very low, resulting in an extremely short time constant for the RC circuit, significantly shortening the common-mode recovery time of a burst signal input.

[0025] The extreme shortening of the time constant of the RC circuit is achieved by a high-level signal (i.e. RST=1) at the reset terminal (RST, Reset).

[0026] The present invention employs a dynamic time constant approach to resolve the conflict between efficiency and accuracy. This simple and feasible design retains the advantages of AC coupling, which facilitates the design of pre- and post-stage signal coupling, while also avoiding the long common-mode recovery time associated with conventional AC coupling in burst-mode limiting amplifier receivers, which makes it difficult to meet the loop operating speed requirement of better than 25.6ns in burst-mode limiting amplifier receivers.

[0027] The inventors have thus far elaborated in detail the working principle, technical solutions, and technical effects of the present invention. Any matters not described in detail in this specification are prior art known to those skilled in the art and should not be considered as insufficient disclosure of the invention by the present specification.

[0028] In addition, abbreviations not specifically described in this application are all common abbreviations in the fields of optical communications and electronic science. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 PON network features.

[0030] Figure 2 Prior art PON OLT receiver block diagram.

[0031] Figure 3 BM-LA RC_CONTROL circuit diagram in the present application.

[0032] Figure 4 Dynamic RC constant simulation waveform of the RST-free BM-LA burst input.

[0033] Figure 5 Dynamic RC constant simulation waveform of the 14ns RST pulse BM-LA burst input. DETAILED DESCRIPTION

[0034] In order to facilitate the understanding of the present application, the technical solutions of the present application will be specifically introduced below in combination with examples.

[0035] A fast common-mode recovery circuit of a burst mode limiting amplifier (BM-LA) includes a dynamic time constant control unit (RC_CONTROL), a limiting amplifier (LA) and a DCOC feedback loop.

[0036] In the present application, as shown in Figure 3 The dynamic time constant control unit (RC_CONTROL) designed by the inventor has signal input ends In+ and In-, which are connected to the signal input ends of the burst mode limiting amplifier (BM-LA) through two identical capacitors C, respectively. The signal input end In+ of the dynamic time constant control unit (RC_CONTROL) is connected in parallel with the first resistor R and the first controllable switch between the capacitor C and the input common-mode voltage end, and the signal input end In- of the dynamic time constant control unit (RC_CONTROL) is connected in parallel with the second resistor R and the second controllable switch between the capacitor C and the input common-mode voltage end. The control ends of the first controllable switch and the second controllable switch are connected to an OR circuit, and the two signal input ends of the OR circuit are connected to RST and the DOC_ON end of the DCOC feedback loop, respectively.

[0037] Preferably, the first resistor R and the second resistor R have the same value.

[0038] The relevant design parameters of the dynamic time constant control unit (RC_CONTROL) are shown in Table 1.

[0039] Table 1 RC_CONTROL related design parameters

[0040] RST R C τ f LF ]]> 0 20KΩ 40pF 800ns 200KHz normal 1 10Ω 40pF 0.4ns 398MHz Reset

[0041] A fast common-mode recovery method for a burst-mode limiting amplifier (BM-LA) is described. Based on the fast common-mode recovery circuit described above, the design parameters of the dynamic time constant control unit (RC_CONTROL) are shown in Table 1. During the initial burst input phase, the reset signal RST = 1. Due to the OR gate (OR) circuit's operating mechanism, regardless of the level of the DOC_ON terminal in the DC offset correction (DCOC) feedback loop, as long as the reset terminal (RST, Reset) is high, the OR gate (OR) circuit output remains high. This results in both the first and second controllable switches being closed, short-circuiting the first and second resistors R. Consequently, when the reset signal RST = 1, the RC time constant is τ = 0.4 ns, allowing the input common-mode voltage to recover to 99.99% in just 4 ns (10τ). Considering the 25Ω (50 / / 50) resistor introduced by the front-end port matching, when RST=1, R increases from 10Ω to 35Ω, the time constant τ increases to 3.5 times, and the common-mode recovery time increases to 14ns, which still meets the minimum 25.6ns indicator requirement of the PON system. After RST ends, RST=0, R switches to 20KΩ. At this time, the low-frequency cutoff frequency f caused by AC coupling in the signal chain LF =200KHz, low-frequency energy loss is small, meeting the requirements of the PON system.

[0042] The circuit of the present invention is simulated using simulation software, and the results are as follows: Figure 4 and Figure 5 Figure 2 shows the effect of the RST signal on the input waveform during a burst input in a dynamic RC constant circuit. RST is always 0, and the recovery time of the burst input signal is extremely slow. At the initial stage of the burst signal, a 14ns pulse is applied to RST. It is easy to see that using the dynamic time constant method can greatly accelerate the recovery of the input common-mode level.

[0043] As described above, in the present invention, due to the operating mechanism of the OR gate (OR) circuit, the level of the DOC_ON terminal of the DC offset calibration (DCOC) feedback loop does not affect the operating mechanism and performance of the dynamic time constant control unit (RC_CONTROL) regarding fast common-mode recovery. Therefore, in the present invention, unit circuits other than the dynamic time constant control unit (RC_CONTROL) are not specifically presented and analyzed.

[0044] Based on the compliance requirement regarding singularity, the inventor will further propose an invention patent application regarding a direct current offset calibration (DCOC) method and circuit thereof.

[0045] It is to be understood that the terms such as "upper", "lower", "front", "rear", "left", "right", and the like as used herein are used for convenience with reference to the accompanying drawings and are not intended to limit the protection scope of the present application. Throughout the drawings, the same elements are denoted by the same or similar reference numerals. When a conventional structure or configuration can cause confusion in understanding the present application, it will be omitted.

[0046] Further, the shape and size of each component in the drawings do not reflect the actual size and ratio, but only illustrate the content of the embodiments of the present application. In addition, in the claims, any reference numeral located between parentheses should not be construed as a limitation on the claims.

[0047] Unless explicitly stated otherwise, the numerical parameters in the specification and the attached claims are approximations. The numerical parameters can vary depending on the required characteristics obtained through the content of the present application. Specifically, all the numbers used in the specification and the claims to express the content, reaction conditions, and the like are understood to be modified by the term "about" in all cases.

[0048] Further, the word "comprise" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0049] The use of ordinal numbers such as "first", "second", "third" and the like in the specification and the claims is used to modify a corresponding element and does not imply that the element has any ordinal number, nor does it represent the order of a certain element with respect to another element or the order of a manufacturing method. The use of such ordinal numbers is only used to clearly distinguish an element having a certain name from another element having the same name.

[0050] In addition, unless specifically described or steps must occur in sequence, the order of the above steps is not limited to the above list and can be changed or rearranged according to the desired design. Also, the above embodiments can be mixed and used with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments can be freely combined to form more embodiments.

[0051] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this method of invention should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments of the preceding invention. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0052] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A fast common-mode recovery circuit for a burst mode-limiting amplifier (BM-LA), comprising: The dynamic time constant control unit (RC_CONTROL), limiting amplifier (LA) and DC offset calibration (DCOC) feedback loop are characterized by: The dynamic time constant control unit (RC_CONTROL) has signal input terminals In+ and In-, which are respectively connected to the signal input terminal of the BM-LA through two identical capacitors C. A first resistor R and a first controllable switch are connected in parallel between the signal input terminal In+ of the dynamic time constant control unit (RC_CONTROL) and the input common-mode voltage terminal through the capacitor C. A second resistor R and a second controllable switch are connected in parallel between the signal input terminal In- of the dynamic time constant control unit (RC_CONTROL) and the input common-mode voltage terminal through the capacitor C. Control terminals of the first controllable switch and the second controllable switch are both connected to an OR gate (OR) circuit, and two input terminals of the OR gate (OR) circuit are respectively connected to a reset terminal (RST, Reset) and a DOC_ON signal terminal of a DC offset calibration (DCOC) feedback loop. The extreme shortening of the time constant of the RC circuit composed of capacitor C and resistor R is achieved by a high-level signal (i.e., RST = 1) at the reset terminal (RST, Reset).

2. The fast common-mode recovery circuit for a burst mode limiting amplifier according to claim 1, wherein: The first resistor R and the second resistor R have the same value.

3. The fast common-mode recovery circuit for a burst mode limiting amplifier according to claim 2, wherein: The values ​​of the first resistor R and the second resistor R are both 20KΩ, and the values ​​of the two capacitors C are both 40pF.

4. The fast common-mode recovery circuit for a burst mode limiting amplifier according to claim 1, wherein: The burst mode limiting amplifier (BM-LA) is composed of four cascaded operational amplifiers.

5. A fast common-mode recovery method for a burst mode limiting amplifier (BM-LA), the method being implemented based on the fast common-mode recovery circuit for a burst mode limiting amplifier according to any one of claims 1 to 4, characterized in that: The reset signal RST (high level active) forces the first controllable switch and the second controllable switch to be turned on, so that the first resistor and the second resistor are short-circuited. The equivalent resistance is approximately the on-resistance of the controllable switch, which makes the time constant of the RC circuit extremely short, thereby greatly shortening the common-mode recovery time of the burst signal input, and is suitable for burst working systems.

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