Display panel and display device

Abstract

A display panel and a display device are provided. The display panel includes: a pixel unit including a pixel circuit and a light-emitting element, the pixel circuit including a first transistor, the pixel unit including a first pixel unit and a second pixel unit located in the same row and in adjacent columns; a first gate line connected to the gate of the first transistor of the first pixel unit; a second gate line connected to the gate of the first transistor of the second pixel unit; a first gate signal line extending along a first direction, connected to the first pixel unit, and configured to provide a first scanning signal to the first pixel unit; a second gate signal line extending along the first direction, connected to the second pixel unit, and configured to provide a second scanning signal to the second pixel unit; a first connecting line extending along a second direction, the first gate line connected to the first gate signal line through the first connecting line; and a second connecting line extending along the second direction, the second gate line connected to the second gate signal line through the second connecting line.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, active-matrix organic light-emitting diode (AMOLED) display technology has been increasingly used in display devices such as mobile phones, tablet computers, digital cameras, etc. due to its advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, and high response speed.

[0003] The under-screen camera technology is a new technology proposed to increase the screen-to-body ratio of display devices. Summary of the invention

[0004] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0005] At least one embodiment of the present disclosure provides a display panel, comprising: a substrate; a pixel unit, located on the substrate, comprising a pixel circuit and a light-emitting element, wherein the pixel circuit is configured to drive the light-emitting element, the pixel circuit comprises a driving transistor, and the driving transistor comprises a gate; a first gate signal line, connected to the gate of the driving transistor; a constant voltage line, configured to provide a first constant voltage to the pixel circuit; and a shielding electrode, connected to the constant voltage line, wherein the orthographic projection of the first gate signal line on the substrate falls within the orthographic projection of the shielding electrode on the substrate.

[0006] For example, the orthographic projection of the shielding electrode on the base substrate covers the orthographic projection of the first gate signal line on the base substrate, and the area of ​​the orthographic projection of the shielding electrode on the base substrate is larger than the area of ​​the orthographic projection of the first gate signal line on the base substrate.

[0007] For example, a distance between an orthographic projection of the first gate signal line on the base substrate and a boundary of an orthographic projection of the shielding electrode on the base substrate is greater than or equal to 1.75 μm.

[0008] For example, the orthographic projection of the gate of the driving transistor on the substrate falls within the orthographic projection of the shielding electrode on the substrate.

[0009] For example, the display panel further includes a second gate signal line, the second gate signal line is connected to the first gate signal line, and the orthographic projection of the second gate signal line on the base substrate falls within the orthographic projection of the shielding electrode on the base substrate.

[0010] For example, the first gate signal line and the second gate signal line are made of different materials.

[0011] For example, the material of the first gate signal line includes metal, and the material of the second gate signal line includes a conductive material formed by converting a semiconductor material into a conductor.

[0012] For example, the pixel circuit further includes a first reset transistor and a first initialization signal line, the first reset transistor is connected to the second gate signal line, the first electrode of the first reset transistor is connected to the first initialization signal line, and the second gate signal line is multiplexed as the second electrode of the first reset transistor.

[0013] For example, the constant voltage line includes the first initialization signal line.

[0014] For example, the display panel also includes a first power line, which is configured to provide a first power supply voltage to the pixel circuit. The pixel circuit also includes a storage capacitor, a first end of the storage capacitor is connected to the gate of the driving transistor, and a second end of the storage capacitor is connected to the first power line.

[0015] For example, the constant voltage line includes the first power line.

[0016] For example, the display panel further includes a third power line, the third power line is connected in parallel with the first power line, the shielding electrode and the third power line are an integrated structure, and the third power line and the first power line extend in the same direction.

[0017] For example, the display panel includes a first display area and a second display area, the first display area is located on at least one side of the second display area, the pixel unit includes a first pixel unit and a second pixel unit, the pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area, the pixel circuit of the second pixel unit is located in the first display area, the light-emitting element of the second pixel unit is located in the second display area, the pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit through a conductive line, the orthographic projection of the conductive line on the substrate partially overlaps with the orthographic projection of the pixel circuit of the first pixel unit on the substrate, and in a direction perpendicular to the substrate, the shielding electrode is located between the conductive line and the first gate signal line.

[0018] For example, the orthographic projection of the conductive line on the base substrate partially overlaps with the orthographic projection of the first gate signal line in the pixel circuit of the first pixel unit.

[0019] For example, the display panel also includes a gate line and a data line, the gate line is configured to provide a scanning signal to the pixel circuit, and the data line is configured to provide a data signal to the pixel circuit; the pixel circuit also includes a data writing transistor, the gate of the data writing transistor is connected to the gate line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the first electrode of the driving transistor.

[0020] For example, the display panel also includes a block, which is connected to the first power line, and the pixel circuit also includes a threshold compensation transistor, wherein the first electrode of the threshold compensation transistor is connected to the second electrode of the driving transistor, and the second electrode of the threshold compensation transistor is connected to the gate of the driving transistor; the gate of the threshold compensation transistor is connected to the gate line; the gate of the driving transistor is connected to the second electrode of the threshold compensation transistor through the first gate signal line, and the threshold compensation transistor includes a first channel and a second channel, and the first channel and the second channel are connected through a conductive connecting portion; the orthographic projection of the block on the substrate at least partially overlaps with the orthographic projection of the conductive connecting portion of the threshold compensation transistor on the substrate.

[0021] For example, an orthographic projection of the block on the base substrate partially overlaps with an orthographic projection of the second gate signal line on the base substrate.

[0022] For example, the display panel also includes a second reset control signal line, the pixel circuit also includes a second reset transistor, the gate of the second reset transistor is connected to the second reset control signal line, the first electrode of the second reset transistor is connected to the second initialization signal line, and the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element.

[0023] For example, the display panel also includes a light-emitting control signal line, and the pixel circuit also includes a first light-emitting control transistor and a second light-emitting control transistor, the gate of the first light-emitting control transistor is connected to the light-emitting control signal line, the first electrode of the first light-emitting control transistor is connected to the first power line, and the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor; the gate of the second light-emitting control transistor is connected to the light-emitting control signal line, the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected to the first electrode of the light-emitting element.

[0024] At least one embodiment of the present disclosure further provides a display device, comprising any one of the above-mentioned display panels.

[0025] For example, the display device further includes a sensor, and the sensor is located at one side of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0027] Figure 1 It is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0028] Figure 2 is a schematic diagram of a pixel unit of a display panel provided in one embodiment of the present disclosure.

[0029] Figure 3 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0030] Figure 4 A schematic diagram of a first display area and a second display area in a display panel provided in an embodiment of the present disclosure.

[0031] FIG. 5A to FIG. 5E A partial plan view of a display panel provided according to an embodiment of the present disclosure.

[0032] Fig. 6A is a schematic diagram of a pixel circuit provided by an embodiment of the present disclosure.

[0033] Figure 6B It is a layout diagram of a pixel circuit provided by an embodiment of the present disclosure.

[0034] Figure 6C for Figure 6B A cross-sectional view along line AB.

[0035] Fig.6D It is a layout diagram of a pixel circuit provided by an embodiment of the present disclosure.

[0036] Fig. 6E for Fig.6D A cross-sectional view along line CD.

[0037] Fig. 6F It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0038] Figure 6G It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0039] Figure 6H It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0040] Fig. 7AA layout diagram of a first pixel circuit or a second pixel circuit in a display panel provided in an embodiment of the present disclosure.

[0041] Figure 7B A layout diagram of a first pixel circuit or a second pixel circuit in a display panel provided in an embodiment of the present disclosure.

[0042] Fig. 8A and Figure 8B A schematic diagram of a display device provided in accordance with an embodiment of the present disclosure.

[0043] Fig. 9 for Fig. 6A The working timing diagram of the pixel circuit shown. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0046] With the development of display technology, the existing notch screen or water drop screen design is gradually unable to meet the user's demand for a high screen-to-body ratio of display panels, and a series of display panels with a light-transmitting display area have emerged. In this type of display panel, hardware such as light sensors (such as cameras) can be set in the light-transmitting display area. Since there is no need to punch holes, a true full screen becomes possible while ensuring the practicality of the display panel.

[0047] In the related art, a display panel with an under-screen camera generally includes a first display area for normal display and a second display area for setting the camera. The second display area generally includes: a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit is connected to a light-emitting element and is used to drive the light-emitting element to emit light, and the interconnected pixel circuits and light-emitting elements overlap in a direction perpendicular to the display panel.

[0048] Since a pixel circuit is also disposed in the second display area in the related art, the light transmittance of the second display area is poor, and accordingly, the display effect of the display panel is poor.

[0049] Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 1 As shown, the display panel may include: a substrate BS. The display panel includes a first display area R1 and a second display area R2, and the first display area R1 may be located on at least one side of the second display area R2. For example, in some embodiments, the first display area R1 surrounds the second display area R2. That is, the second display area R2 may be surrounded by the first display area R1. The second display area R2 may also be set at other positions, and the setting position of the second display area R2 may be determined as required. For example, the second display area R2 may be located at the top center of the substrate BS, or at the upper left corner or upper right corner of the substrate BS. For example, hardware such as a photosensitive sensor (such as a camera) is set in the second display area R2 of the display panel. For example, the second display area R2 is a light-transmitting display area, and the first display area R1 is a display area. For example, the first display area R1 is opaque and is only used for display.

[0050] Figure 2 FIG. 1 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure. The display panel includes a pixel unit 100, and the pixel unit 100 is located on a substrate. Figure 2 As shown, the pixel unit 100 includes a pixel circuit 100a and a light emitting element 100b, and the pixel circuit 100a is configured to drive the light emitting element 100b. For example, the pixel circuit 100a is configured to provide a driving current to drive the light emitting element 100b to emit light. For example, the light emitting element 100b is an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light under the drive of its corresponding pixel circuit 100b. The color of the light emitted by the light emitting element 100b can be determined as required.

[0051] In order to improve the light transmittance of the second display area R2, only the light emitting element can be arranged in the second display area R2, and the pixel circuit driving the light emitting element of the second display area R2 can be arranged in the first display area R1. That is, the light transmittance of the second display area R2 can be improved by separately arranging the light emitting element and the pixel circuit.

[0052] Figure 3 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 3 As shown, the display panel includes: a plurality of first pixel circuits 10, a plurality of second pixel circuits 20 and a plurality of first light-emitting elements 30 located in the first display area R1, and a plurality of second light-emitting elements 40 located in the second display area R2. For example, the plurality of second pixel circuits 20 may be distributed between the plurality of first pixel circuits 10 at intervals.

[0053] For example, Figure 3 As shown, at least one first pixel circuit 10 among the plurality of first pixel circuits 10 may be connected to at least one first light-emitting element 30 among the plurality of first light-emitting elements 30, and the orthographic projection of at least one first pixel circuit 10 on the substrate BS may at least partially overlap with the orthographic projection of at least one first light-emitting element 30 on the substrate BS. The at least one first pixel circuit 10 may be used to provide a driving signal to the connected first light-emitting element 30 to drive the first light-emitting element 30 to emit light.

[0054] For example, Figure 3 As shown, at least one second pixel circuit 20 among the plurality of second pixel circuits 20 can be connected to at least one second light-emitting element 40 among the plurality of second light-emitting elements 40 through a conductive line L1, and the at least one second pixel circuit 20 can be used to provide a driving signal to the connected second light-emitting element 40 to drive the second light-emitting element 40 to emit light. Figure 3 As shown, since the second light emitting element 40 and the second pixel circuit 20 are located in different areas, the orthographic projection of at least one second pixel circuit 20 on the substrate BS does not overlap with the orthographic projection of at least one second light emitting element 40 on the substrate BS.

[0055] For example, in the embodiment of the present disclosure, the first display area R1 can be set as a non-light-transmitting display area, and the second display area R2 can be set as a light-transmitting display area. For example, the first display area R1 is not light-transmitting, and the second display area R2 is light-transmitting. In this way, the display panel provided by the embodiment of the present disclosure does not need to be processed by digging holes on the display panel, and the required hardware structures such as the photosensitive sensor can be directly set at the position corresponding to the second display area R2 on one side of the display panel, laying a solid foundation for the realization of a true full screen. In addition, since the second display area R2 only includes light-emitting elements but not pixel circuits, it is beneficial to improve the transmittance of the second display area R2, so that the display panel has a better display effect.

[0056] like Figure 3As shown, the pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102, the pixel circuit 100a and the light-emitting element 100b of the first pixel unit 101 are both located in the first display area R1, the pixel circuit 100a of the second pixel unit 101 is located in the first display area R1, and the light-emitting element 100b of the second pixel unit 102 is located in the second display area R2. In the embodiment of the present disclosure, the pixel circuit 100a of the first pixel unit 101 is the first pixel circuit 10, the light-emitting element 100b of the first pixel unit 101 is the first light-emitting element 30, the pixel circuit 100a of the second pixel unit 101 is the second pixel circuit 20, and the light-emitting element 100b of the second pixel unit 102 is the second light-emitting element 40. For example, the first light-emitting element 30 can be referred to as an in-situ light-emitting element. For example, the first pixel circuit 10 can be referred to as an in-situ pixel circuit, and the second pixel circuit 20 can be referred to as a non-in-situ pixel circuit.

[0057] For example, Figure 3 As shown, the second light emitting element 40 and the second pixel circuit 20 connected to the second light emitting element 40 are located in the same row. That is, the light emitting signal of the second light emitting element 40 comes from the second pixel circuit in the same row. For example, the pixel circuits of the pixel units in the same row are connected to the same gate line.

[0058] like Figure 3 As shown, the pixel circuit (second pixel circuit 20) of the second pixel unit 102 is connected to the light-emitting element (second light-emitting element 40) of the second pixel unit 102 through the conductive line L1. For example, the conductive line L1 is made of a transparent conductive material. For example, the conductive line L1 is made of a conductive oxide material. For example, the conductive oxide material includes indium tin oxide (ITO), but is not limited thereto.

[0059] like Figure 3 As shown, one end of the conductive line L1 is connected to the second pixel circuit 20, and the other end of the conductive line L1 is connected to the second light emitting element 40. Figure 3 As shown, the conductive line L1 extends from the first display region R1 to the second display region R2.

[0060] like Figure 1 and Figure 3 As shown, in some embodiments, the display panel further includes an auxiliary area Ra, and the second pixel circuit 20 may be disposed in the auxiliary area Ra.

[0061] Figure 4 Schematic diagram of a first display area and a second display area in a display panel provided in an embodiment of the present disclosure. Figure 4 As shown, in the second display area R2, a light-transmitting area R0 is provided between adjacent second light-emitting elements 40. Figure 4As shown, a plurality of light-transmitting regions R0 are connected to each other to form a continuous light-transmitting region separated by a plurality of second light-emitting elements 40. The conductive line L1 is made of a transparent conductive material to increase the light transmittance of the light-transmitting region R0 as much as possible. Figure 4 As shown, the second display region R2 except for the area where the second light emitting element 40 is disposed may be a light-transmitting region.

[0062] FIG. 5A to FIG. 5E This is a partial plan view of a display panel provided by an embodiment of the present disclosure. FIG. 5A to FIG. 5E Give a description.

[0063] Figure 5A Schematic diagram of a first display area and a second display area of ​​a display panel provided in one embodiment of the present disclosure. Figure 5A As shown, the second display area R2 is a light-transmitting display area, and the first display area R1 is a display area.

[0064] Figure 5B A schematic diagram of a first light-emitting element in a first display area and a second light-emitting element in a second display area of ​​a display panel provided in an embodiment of the present disclosure. Figure 5B A first light emitting element 30 and a second light emitting element 40 are shown.

[0065] refer to Figure 5A , Figure 5B and Figure 3 In order to improve the display effect, the density of the second light emitting elements 40 may be equal to the density of the first light emitting elements 30. That is, the resolution of the second display area R2 is the same as the resolution of the first display area R1. Of course, in other embodiments, the density of the second light emitting elements 40 may be greater than or less than the density of the first light emitting elements 30. That is, the resolution of the second display area R2 may be greater than or less than the resolution of the first display area R1. For example, Figure 5B and Figure 4 As shown, the light emitting area of ​​the second light emitting element 40 is smaller than the light emitting area of ​​the first light emitting element 30 . Figure 4 The dotted lines show the light emitting area of ​​the second light emitting element 40 and the light emitting area of ​​the first light emitting element 30. For example, the light emitting area of ​​the light emitting element may correspond to the area of ​​the opening of the pixel definition layer.

[0066] Figure 5C A schematic diagram of a conductive line in a display panel provided by an embodiment of the present disclosure. Figure 5C A plurality of conductive lines L1 are shown.

[0067] Figure 5D A schematic diagram of a conductive line in a display panel provided by an embodiment of the present disclosure. Figure 5D The conductive line L1 is shown. Figure 5DAs shown, the conductive line L1 includes a first conductive line L11, a second conductive line L12, and a third conductive line L13. In a high PPI display panel, in order to avoid too dense conduction, multiple conductor pattern layers can be formed. An insulating layer is set between different conductor pattern layers. For example, the first conductive line L11 is located in the first conductor pattern layer, the second conductive line L12 is located in the second conductor pattern layer, and the third conductive line L13 is located in the third conductor pattern layer. Of course, in other embodiments, multiple conductive lines of other forms can also be set. For example, a conductive line L1 is formed by conductive parts located in different conductor pattern layers. For example, conductive parts located in different conductor pattern layers can be connected by vias that penetrate the insulating layer.

[0068] Figure 5E The first light emitting element 30, the second light emitting element 40, the first pixel circuit 10, the second pixel circuit 20, the connecting element CE0, and the conductive line L1 are shown. Each pixel circuit is connected to the light emitting element through the connecting element CE0. That is, each pixel unit has a connecting element CE0. That is, the first pixel circuit 10 is connected to the first light emitting element 30 through the connecting element CE0, and the second pixel circuit 20 is connected to the second light emitting element 40 through the connecting element CE0. For example, one end of the conductive line L1 is connected to the second pixel circuit 20 through the connecting element CE0, and the other end of the conductive line L1 is connected to the second light emitting element 40.

[0069] like Figure 5E As shown, a conductive line L1 passes through the area where the pixel circuit of the pixel unit is located to respectively connect the second pixel circuit 20 and the second light-emitting element 40 on both sides of the pixel unit. For example, the area where the pixel circuit of the pixel unit is located overlaps with multiple conductive lines L1 passing through the area, so that the pixel circuit and the conductive lines overlapping the pixel circuit are coupled to form parasitic capacitance, resulting in brightness differences and display defects such as stripes (Mura). The area where the second pixel circuit 20 is set in the first display area R1 can be called an auxiliary area Ra (such as Figure 1 and Figure 3 As shown in FIG. 1 , the auxiliary area Ra can also be called a transition area. Due to the coupling between the conductive line and the pixel circuit, the auxiliary area (transition area) is prone to dimming, and the dim pixel unit is the pixel unit (first pixel unit) in the first display area R1, not the second light-emitting element 40 in the second display area R2. For example, the dimming of the auxiliary area is more obvious in the case of high grayscale than in the case of low grayscale. Figure 5E Taking the example that a first pixel circuit 10 overlaps with at most two conductive lines L1, in other embodiments, a first pixel circuit 10 may also overlap with more conductive lines L1. Figure 5CAs shown, in some embodiments, one first pixel circuit 10 may overlap with 10-15 conductive lines L1. The number of conductive lines L1 overlapped with one first pixel circuit 10 may be determined according to needs.

[0070] In some embodiments, the size of the first pixel circuit 10 can be compressed in the first direction X to obtain an area for arranging the second pixel circuit 20. Figure 5E As shown, in the auxiliary area, a column of second pixel circuits 20 is provided for every set column of first pixel circuits 10. For example, the number of columns of first pixel circuits 10 between two adjacent columns of second pixel circuits 20 can be determined as required.

[0071] Fig. 6A It is a schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure. Figure 6B It is a layout diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure. Figure 6C for Figure 6B A cross-sectional view along line AB. Fig.6D It is a layout diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure. Fig. 6E for Fig.6D A cross-sectional view along line CD. Fig. 6F It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0072] Fig. 6A The pixel circuit shown may be a pixel circuit of a low temperature polysilicon (LTPS) AMOLED commonly used in the related art.

[0073] Fig. 6A FIG. 4 shows a pixel circuit of a pixel unit of a display panel, such as Fig. 6A As shown, the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes six switch transistors (T2-T7), a drive transistor T1 and a storage capacitor Cst. The six switch transistors are respectively a data write transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7. The light-emitting element 100b includes a first pole E1 and a second pole E2 and a light-emitting functional layer located between the first pole E1 and the second pole E2. For example, the first pole E1 is an anode and the second pole E2 is a cathode. Typically, the threshold compensation transistor T3 and the first reset transistor T6 use a dual-gate thin film transistor (TFT) to reduce leakage.

[0074] like Fig. 6AAs shown, the display panel includes a gate line GT, a data line DT, a first power line PL1, a second power line PL2, a light-emitting control signal line EML, an initialization signal line INT, a reset control signal line RST, etc. For example, the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2. The first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel unit 100, the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel unit 100, and the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT is configured to provide a scan signal SCAN to the pixel unit 100, the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 100, the light-emitting control signal line EML is configured to provide a light-emitting control signal EM to the pixel unit 100, the first reset control signal line RST1 is configured to provide a first reset control signal RESET1 to the pixel unit 100, and the second reset control signal line RST2 is configured to provide a scan signal SCAN to the pixel unit 100. The first initialization signal line INT1 is configured to provide a first initialization signal Vinit1 to the pixel unit 100. The second initialization signal line INT2 is configured to provide a second initialization signal Vinit2 to the pixel unit 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, and their magnitudes may be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto, for example, the first initialization signal Vinit1 and the second initialization signal Vinit2 may both be less than or equal to the second voltage signal VSS. For example, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT1 are connected, and are both configured to provide the initialization signal Vinit to the pixel unit 100, that is, the first initialization signal line INT1 and the second initialization signal line INT2 are both referred to as initialization signal lines INT, and the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, and are both Vinit.

[0075] like Fig. 6A As shown, the driving transistor T1 is electrically connected to the light emitting element 100b, and outputs a driving current to drive the light emitting element 100b to emit light under the control of the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals.

[0076] For example, the light emitting element 100b includes an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit 100a. For example, a pixel includes a plurality of pixel units. A pixel may include a plurality of pixel units that emit light of different colors. For example, a pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto. The number of pixel units included in a pixel and the light emission of each pixel unit can be determined as required.

[0077] For example, Fig. 6A As shown, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first electrode T21 of the data writing transistor T2 is connected to the data line DT, and the second electrode T22 of the data writing transistor T2 is connected to the first electrode T11 of the driving transistor T1.

[0078] For example, Fig. 6A As shown, the pixel circuit 100a further includes a threshold compensation transistor T3, a gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, a first electrode T31 of the threshold compensation transistor T3 is connected to the second electrode T12 of the driving transistor T1, and a second electrode T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0079] For example, Fig. 6A As shown, the display panel also includes a light-emitting control signal line EML, and the pixel circuit 100a also includes a first light-emitting control transistor T4 and a second light-emitting control transistor T5, a gate T40 of the first light-emitting control transistor T4 is connected to the light-emitting control signal line EML, a first electrode T41 of the first light-emitting control transistor T4 is connected to the first power line PL1, and a second electrode T42 of the first light-emitting control transistor T4 is connected to a first electrode T11 of the driving transistor T1; a gate T50 of the second light-emitting control transistor T5 is connected to the light-emitting control signal line EML, a first electrode T51 of the second light-emitting control transistor T5 is connected to a second electrode T12 of the driving transistor T1, and a second electrode T52 of the second light-emitting control transistor T5 is connected to a first electrode E1 of the light-emitting element 100b.

[0080] like Fig. 6AAs shown, the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1, and the second reset transistor T7 is connected to the first electrode E1 of the light emitting element 100b and is configured to reset the first electrode E1 of the light emitting element 100b. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The second initialization signal line INT2 is connected to the first electrode E1 of the light emitting element 100b through the second reset transistor T7. For example, the first initialization signal line INT1 and the second initialization signal line INT2 are connected to be input with the same initialization signal, but not limited to this. In some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 can also be insulated from each other and configured to input signals separately.

[0081] For example, Fig. 6A As shown, the first electrode T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, the second electrode T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, the first electrode T71 of the second reset transistor T7 is connected to the second initialization signal line INT2, and the second electrode T72 of the second reset transistor T7 is connected to the first electrode E1 of the light emitting element 100b. Fig. 6A As shown, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.

[0082] like Fig. 6A As shown, the first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a; the pixel circuit also includes a storage capacitor Cst, a first electrode Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and a second electrode Cb of the storage capacitor Cst is connected to the first power line PL1.

[0083] For example, Fig. 6A As shown, the display panel further includes a second power line PL2, and the second power line PL2 is connected to the second electrode 201 of the light emitting element 100b.

[0084] Fig. 6A A first node N1, a second node N2, a third node N3, and a fourth node N4 are shown. For example, in some embodiments, reference Figure 5C , Figure 5E and Fig. 6A A capacitor is formed between the first node N1 and the conductive line L1, a capacitor is formed between the conductive line L1 and the fourth node N4, and the conductive line L1 is coupled with the first node N1 and the fourth node N4 respectively, thereby causing brightness differences and forming display defects such as stripes (Mura), which affects the display quality.

[0085] like Figure 6B As shown, the pixel circuit includes a driving transistor T1, and the driving transistor includes a gate T10. Figure 6B and Figure 6C The second electrode Cb of the storage capacitor Cst has an opening OPN1, and one end of the connection electrode CE1 is connected to the gate T10 of the driving transistor T1 through the opening OPN1. The connection electrode CE1 may also be referred to as a first gate signal line SL1. Figure 6B As shown, the first gate signal line SL1 is connected to the gate T10 of the driving transistor T1.

[0086] like Figure 6B As shown, the first gate signal line SL1 is connected to the second gate signal line SL2. The gate T10 of the driving transistor T1, the first gate signal line SL1, and the second gate signal line SL2 constitute the gate signal portion PT1. The potential on the gate signal portion PT1 is the same. Of course, in other embodiments, the second gate signal line SL2 may not be provided. In this case, the gate T10 of the driving transistor T1 and the first gate signal line SL1 constitute the gate signal portion PT1. For example, the second gate signal line SL2 is the second electrode T62 of the first reset transistor T6.

[0087] refer to Figure 6B and Figure 6C In order to stabilize the potential on the gate signal portion PT1, the display panel provided by the embodiment of the present disclosure provides a shielding electrode SE and a constant voltage line L0, and the constant voltage line L0 is configured to provide a constant voltage to the pixel circuit. The shielding electrode SE is connected to the constant voltage line L0, so that the voltage on the shielding electrode SE is stable, which can play a shielding role and prevent the conductive line L1 from affecting the potential on the gate signal portion PT1. The positive projection of the first gate signal line SL1 on the base substrate BS falls within the positive projection of the shielding electrode SE on the base substrate BS.

[0088] refer to FIG. 6B to FIG. 6D In order to make the shielding electrode play a better shielding role and increase the shielding amount, the orthographic projection of the first gate signal line SL1 on the base substrate BS completely falls within the orthographic projection of the shielding electrode SE on the base substrate BS.

[0089] For example, in order to reduce display defects (mura) and improve display effects, the distance between the orthographic projection of the first gate signal line SL1 on the substrate BS and the boundary of the orthographic projection of the shielding electrode SE on the substrate BS is greater than or equal to 1.75 μm. Because the area occupied by the pixel unit is limited, the distance of the shielding electrode SE beyond the first gate signal line SL1 can be limited. For example, in some embodiments, in order to obtain a better shielding effect, the distance between the orthographic projection of the first gate signal line SL1 on the substrate BS and the boundary of the orthographic projection of the shielding electrode SE on the substrate BS is greater than or equal to 2.33 μm.

[0090] like Figure 6B As shown, the display panel further includes a block BK, the block BK is connected to the first power line PL1, the threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, the first channel CN1 and the second channel CN2 are connected through a conductive connection portion CP; the orthographic projection of the block BK on the base substrate BS at least partially overlaps with the orthographic projection of the conductive connection portion CP of the threshold compensation transistor T3 on the base substrate BS. Figure 6B As shown, the blocking block BK of the adjacent column of pixel units is used to shield the conductive connection portion CP of the threshold compensation transistor T3 of the pixel unit in the same column.

[0091] For example, Figure 6B , 6G As shown in Figures 6H and 6H, in the case where the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1, and the orthographic projection of the second gate signal line SL2 on the substrate substrate BS falls within the orthographic projection of the block BK on the substrate substrate BS. Further, for example, the boundary of the orthographic projection of the block BK on the substrate substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate substrate BS. For example, the distance that the boundary of the orthographic projection of the block BK on the substrate substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate substrate BS is greater than or equal to 1.75μm. For example, the distance that the boundary of the orthographic projection of the block BK on the substrate substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate substrate BS is greater than or equal to 2.33μm. Of course, in other embodiments, the shielding electrode SE may be used to replace the function of the block BK, or the orthographic projection of the second gate signal line SL2 on the base substrate BS falls within both the orthographic projection of the block BK on the base substrate BS and the orthographic projection of the shielding electrode SE on the base substrate BS (e.g. Fig. 7A shown).

[0092] For example, the first gate signal line SL1 and the second gate signal line SL2 are made of different materials. For example, the first gate signal line SL1 is made of metal, and the second gate signal line SL2 is made of a conductive material formed by converting a semiconductor material into a conductor.

[0093] For example, Figure 6B and Fig.6D As shown, in order to save wiring, the first power line PL1 is used as the constant voltage line L0. In other embodiments, in order to save wiring, the first initialization signal line INL1 can also be used as the constant voltage line or the second initialization signal line INL2 can be used as the constant voltage line. The example of the constant voltage line L0 is not limited to the first power line PL1, the first initialization signal line INL1 and the second initialization signal line INL2. As long as it is a signal line that provides a constant voltage in the pixel circuit, it can be used as the constant voltage line L0. The embodiment of the present disclosure is explained by taking the first power line PL1 as the constant voltage line L0 as an example. When a signal line that provides a constant voltage other than the first power line PL1 is used as the constant voltage line L0, the shape of the shielding electrode SE can be adjusted so that it is connected to the signal line that provides the constant voltage.

[0094] like Fig. 6F As shown, the conductive line L1 includes a first portion L1a, a second portion L1b and a third portion L1c. The first portion L1a and the third portion L1c both extend along the second direction Y, and the second portion L1b extends along the first direction X. For example, the first portion L1a and the third portion L1c are located in the same conductor pattern layer, and the second portion L1b is located in another conductor pattern layer. Fig. 6F The medium grey filled areas represent vias used to connect different parts of the conductive lines.

[0095] Fig. 6F The via Ha and the via Hb are shown. The first part L1a and the second part L1b are connected by the via Ha penetrating the insulating layer, and the second part L1b and the third part L1c are connected by the via Hb penetrating the insulating layer. For example, Fig. 6F Three conductive lines L1 are shown, and the conductive lines L10 and L100 have similar structures.

[0096] Of course, in other embodiments, the entire conductive line may be located in the same conductor pattern layer. That is, the first portion L1a, the second portion L1b, and the third portion L1c are located in the same conductor pattern layer. For example, in other embodiments, three adjacent conductive lines L1 in the second direction Y are located in the first conductor pattern layer, the second conductor pattern layer, and the third conductor pattern layer, respectively. The arrangement of the conductive lines may be determined as required.

[0097] like Fig. 6F As shown, the orthographic projection of the conductive line L1 on the base substrate BS partially overlaps with the orthographic projection of the pixel circuit (first pixel circuit 10) of the first pixel unit 101 on the base substrate BS. Fig. 6FAs shown, the shielding electrode SE is located between the conductive line L1 and the first gate signal line SL1. In the embodiment of the present disclosure, after forming the pixel circuit, the shielding electrode SE is formed, and then the conductive line L1 is formed, and then the light emitting element is formed. Thus, the shielding electrode SE is located between the conductive line L1 and the first gate signal line SL1, and the shielding electrode SE is located between the conductive line L1 and the gate T10 of the driving transistor (refer to Figure 6G and Figure 6H ).

[0098] For clarity of illustration, Fig. 6F Only a part of the structure of the pixel circuit is shown in FIG. A conductive line L1 is provided in the auxiliary area, and no conductive line L1 is provided in the area of ​​the first display area other than the auxiliary area, so that the orthographic projection of the pixel circuit (first pixel circuit) in the area of ​​the first display area other than the auxiliary area on the base substrate BS does not overlap with the orthographic projection of the conductive line L1 on the base substrate BS.

[0099] like Fig. 6F As shown, the orthographic projection of the conductive line L1 on the base substrate BS partially overlaps with the orthographic projection of the first gate signal line SL1 in the pixel circuit of the first pixel unit 101 .

[0100] Fig. 6F Via HL and via HE are shown. Fig. 6F As shown, one end of the conductive line L10 is connected to the second pixel circuit 20 through the via hole HL, and the other end of the conductive line L10 is connected to the first electrode E1 of the second light emitting element 40 through the via hole HE.

[0101] refer to Figure 6C and Fig. 6EA buffer layer BL is disposed on the substrate BS, an isolation layer BR is disposed on the buffer layer BL, an active layer LY0 is disposed on the isolation layer BR, a first insulating layer ISL1 is disposed on the active layer LY0, a first conductive layer LY1 is disposed on the first insulating layer ISL1, a second insulating layer ISL2 is disposed on the first conductive layer LY1, a second conductive layer LY2 is disposed on the second insulating layer ISL2, a third insulating layer ISL3 is disposed on the second conductive layer LY2, a third conductive layer LY3 is disposed on the third insulating layer ISL3, and the third conductive layer LY3 includes a connecting electrode CE01, and the connecting electrode CE01 passes through the first insulating layer ISL1, the second insulating layer ISL2 and The via hole H3 of the third insulating layer ISL3 is connected to the second electrode T52 of the second light emitting control transistor T5, a fourth insulating layer ISL4 and a fifth insulating layer ISL5 are arranged on the third conductive layer LY3, a fourth conductive layer LY4 is arranged on the fourth insulating layer ISL4 and the fifth insulating layer ISL5, the fourth conductive layer LY4 includes a connecting electrode CE02, the connecting electrode CE02 is connected to the connecting electrode CE01 through a via hole H22 penetrating the fourth insulating layer ISL4 and the fifth insulating layer ISL5, a sixth insulating layer ISL6 is arranged on the fourth conductive layer LY4, and the light emitting element 100b (the second light emitting element 30) is connected to the light emitting element 100b (the second light emitting element 30) through a via hole H31 penetrating the sixth insulating layer ISL6. Fig.6D and Fig. 6E The light emitting element 100b includes a first electrode E1, a second electrode E2, and a light emitting functional layer FL located between the first electrode E1 and the second electrode E2. For example, the connecting element CE0 includes a connecting electrode CE01 and a connecting electrode CE02.

[0102] like Figure 6B As shown, one end of the connection electrode CE1 is connected to the gate T10 of the driving transistor T1 through the via H1, and the other end of the connection electrode CE1 is connected to the second electrode T62 of the first reset transistor T6 through the via H2. One end of the connection electrode CE2 is connected to the first initialization signal line INL1 through the via H4, and the other end of the connection electrode CE2 is connected to the first electrode T61 of the first reset transistor T6 through the via H5. One end of the connection electrode CE3 is connected to the second initialization signal line INL2 through the via H6, and the other end of the connection electrode CE3 is connected to the first electrode T71 of the second reset transistor T7 through the via H7. The first power line PL1 is connected to the first electrode T41 of the first light-emitting control transistor T4 through the via H8. The first power line PL1 is connected to the second electrode Cb of the storage capacitor Cst through the via H9. The first power line PL1 is connected to the block BK through the via Hk. The data line DT is connected to the first electrode T21 of the data writing transistor T2 through the via H0.

[0103] For example, in the manufacturing process of the display panel, a self-alignment process is adopted to conduct the semiconductor pattern layer using the first conductive layer LY1 as a mask. The semiconductor pattern layer can be formed by patterning a semiconductor thin film. For example, the semiconductor pattern layer is heavily doped by ion implantation, so that the portion of the semiconductor pattern layer not covered by the first conductive layer LY1 is conductive, forming the source region (first electrode T11) and drain region (second electrode T12) of the driving transistor T1, the source region (first electrode T21) and drain region (second electrode T22) of the data writing transistor T2, the source region (first electrode T31) and drain region (second electrode T32) of the threshold compensation transistor T3, the source region (first electrode T41) and drain region (second electrode T42) of the first light emission control transistor T4, the source region (first electrode T51) and drain region (second electrode T52) of the second light emission control transistor T5, the source region (first electrode T61) and drain region (second electrode T62) of the first reset transistor T6, and the source region (first electrode T71) and drain region (second electrode T72) of the second reset transistor T7. The portion of the semiconductor pattern layer covered by the first conductive layer LY1 retains semiconductor characteristics, forming a channel region of the driving transistor T1, a channel region of the data writing transistor T2, a channel region of the threshold compensation transistor T3, a channel region of the first light emission control transistor T4, a channel region of the second light emission control transistor T5, a channel region of the first reset transistor T6, and a channel region of the second reset transistor T7. For example, Figure 6B As shown, the second electrode T72 of the second reset transistor T7 and the second electrode T52 of the second light-emitting control transistor T5 are formed in one piece; the first electrode T51 of the second light-emitting control transistor T5, the second electrode T12 of the driving transistor T1 and the first electrode T31 of the threshold compensation transistor T3 are formed in one piece; the first electrode T11 of the driving transistor T1, the second electrode T22 of the data writing transistor T2 and the second electrode T42 of the first light-emitting control transistor T4 are formed in one piece; the second electrode T32 of the threshold compensation transistor T3 and the second electrode T62 of the first reset transistor T6 are formed in one piece. In some embodiments, Figure 6B As shown, the first electrode T71 of the second reset transistor T7 and the first electrode T61 of the first reset transistor T6 can be formed integrally.

[0104] For example, the channel region of the transistor used in the embodiment of the present disclosure may be single crystal silicon, polycrystalline silicon (e.g., low temperature polycrystalline silicon) or metal oxide semiconductor material (e.g., IGZO, AZO, etc.). In one embodiment, the transistors are all P-type low temperature polycrystalline silicon (LTPS) thin film transistors. In another embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin film transistors, that is, the channel material of the transistor is a metal oxide semiconductor material (e.g., IGZO, AZO, etc.), and the metal oxide semiconductor thin film transistor has a lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.

[0105] For example, the transistors used in the embodiments of the present disclosure may include a variety of structures, such as top-gate, bottom-gate or dual-gate structures. In one embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are dual-gate thin film transistors, which can help reduce the gate leakage current of the driving transistor T1.

[0106] For example, Fig. 6E As shown, the display panel further includes a pixel definition layer PDL and a spacer PS, wherein the pixel definition layer PDL has an opening OPN, and the opening OPN is configured to define the light emitting area (light emitting area, effective light emitting area) of the pixel unit. The spacer PS is configured to support the fine metal mask when forming the light emitting functional layer FL.

[0107] For example, the opening OPN is a light emitting area of ​​the pixel unit. The light emitting function layer FL is located on the first electrode E1 of the light emitting element 100b, and the second electrode E2 of the light emitting element 100b is located on the light emitting function layer FL. Fig. 6E As shown, a packaging layer CPS is provided on the light emitting element 100b. The packaging layer CPS includes a first packaging layer CPS1, a second packaging layer CPS2, and a third packaging layer CPS3. For example, the first packaging layer CPS1 and the third packaging layer CPS3 are inorganic material layers, and the second packaging layer CPS2 is an organic material layer. For example, the first electrode E1 is an anode of the light emitting element 100b, and the second electrode E2 is a cathode of the light emitting element 100b, but is not limited thereto.

[0108] Figure 6G It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 6G A plurality of conductive lines L1 are shown. For example, the conductive lines L1 extend along a first direction X, and the plurality of conductive lines L1 are arranged along a second direction Y, but this is not limited thereto. Figure 6G Four conductive lines L1 are shown, however, the conductive lines L1 may be as many as desired. Figure 6G The pixel unit shown is a first pixel unit 101, Figure 6GThe pixel circuit shown is a first pixel circuit 10. The display panel provided by the embodiment of the present disclosure further includes a first pixel unit 101 that does not overlap with the conductive line L1. For example, the first pixel unit 101 that does not overlap with the conductive line L1 is located in the first display area except the auxiliary area. Figure 6G Each conductive line L1 shown is used to connect the second pixel circuit 20 and the second light emitting element 40 located at the left and right sides of the first pixel unit 101 respectively.

[0109] Figure 6H It is a partial schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 6H A plurality of conductive lines L1 are shown. For example, the conductive lines L1 extend along a first direction X, and the plurality of conductive lines L1 are arranged along a second direction Y, but this is not limited thereto. Figure 6G Four conductive lines L1 are shown, however, the conductive lines L1 may be as many as desired. Figure 6G The pixel unit shown is the second pixel circuit 20 of the second pixel unit 102. Figure 6H As shown, one of the plurality of conductive lines L1 is connected to the second pixel unit 102, and the remaining conductive lines L1 are not connected to the second pixel unit 102. For example, the conductive line L10 (one of the plurality of conductive lines L1) is connected to the connecting element CE0 of the second pixel unit 102 through the via hole HL penetrating the insulating layer. For further example, the conductive line L10 is connected to the connecting electrode CE02 of the connecting element CE0 of the second pixel unit 102 through the via hole HL penetrating the insulating layer. The conductive line L10 is used to be connected to the first electrode E1 of the second light-emitting element 40 located in the second display area.

[0110] Fig. 7A A layout diagram of a first pixel circuit or a second pixel circuit in a display panel provided in an embodiment of the present disclosure. Fig. 7A As shown, the orthographic projection of the gate T10 of the driving transistor T1 on the substrate BS falls within the orthographic projection of the shielding electrode SE on the substrate BS.

[0111] For example, Fig. 7AAs shown, in the case where the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1, and the orthographic projection of the second gate signal line SL2 on the substrate BS also falls within the orthographic projection of the shielding electrode SE on the substrate BS. For example, the boundary of the orthographic projection of the shielding electrode SE on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS. For example, the distance that the boundary of the orthographic projection of the shielding electrode SE on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 1.75μm. For example, the distance that the boundary of the orthographic projection of the shielding electrode SE on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 2.33μm.

[0112] For example, Fig. 7A As shown, the orthographic projections of the gate T10 of the driving transistor T1 , the first gate signal line SL1 , and the second gate signal line SL2 on the base substrate BS all fall within the orthographic projection of the shielding electrode SE on the base substrate BS.

[0113] For example, Fig. 7A As shown, the orthographic projection of the shielding electrode SE on the base substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the base substrate BS, and the orthographic projection of the block BK on the base substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the base substrate BS. Fig. 7A In the display panel shown, the shielding electrode SE and the block BK form a double-layer shielding for the second gate signal line SL2.

[0114] For example, Fig. 7A As shown, the orthographic projection of the shielding electrode SE on the base substrate BS partially overlaps with the orthographic projection of the block BK on the base substrate BS.

[0115] Of course, in other embodiments, the block BK may not be provided, or the orthographic projection of the block BK on the base substrate BS does not overlap with the orthographic projection of the second gate signal line SL2 on the base substrate BS.

[0116] Figure 7B FIG. 1 is a layout diagram of a first pixel circuit or a second pixel circuit in a display panel provided by an embodiment of the present disclosure. Figure 7B As shown, the fourth conductive layer LY4 further includes a third power line PL3, which is integrally formed with the shielding electrode SE. The third power line PL3 is connected to the first power line PL1 through a via H21 to form a parallel structure to reduce resistance. The third power line PL3 extends along the second direction Y. Figure 7B As shown, the dimension of the third power line PL3 in the second direction Y is greater than the dimension of the shielding electrode SE in the second direction Y.

[0117] For example, Figure 6B , Fig.6D , Figure 7B As shown, the orthographic projection of the block BK on the base substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the base substrate BS, and the orthographic projection of the shielding electrode SE on the base substrate BS partially overlaps with the orthographic projection of the first gate signal line SL1 on the base substrate BS, so that the block BK and the shielding electrode SE together play a role in shielding the gate signal portion PT1. Of course, in some other embodiments, the block BK may not be provided, or the orthographic projection of the block BK on the base substrate BS does not overlap with the orthographic projection of the second gate signal line SL2 on the base substrate BS.

[0118] For example, Figure 6B , Fig.6D , Figure 7B As shown, the left block BK extends to the pixel unit on the left side of the pixel unit shown in the figure to block the conductive connection portion CP of its threshold compensation transistor T3, and the right block BK extends from the block BK connected to the pixel unit on the right side of the pixel unit shown in the figure.

[0119] like Figure 6B , Fig.6D , Fig. 7A ,as well as Figure 7B As shown, the channels of each transistor and the first and second electrodes on both sides of the channels are located in the active layer LY0; the first reset control signal line RST1, the gate line GT, the gate T10 of the driving transistor (the first electrode Ca of the storage capacitor Cst), the light emitting control signal line EML and the second reset control signal line RST2 are located in the first conductive layer LY1; the first initialization signal line INL1, the second electrode Cb of the storage capacitor Cst, and the second initialization signal line INL2 are located in the second conductive layer LY2; the data line DT, the first power line PL1, the connecting electrode CE1, the connecting electrode CE2, the connecting electrode CE3, and the connecting electrode CE01 are located in the third conductive layer LY3; the shielding electrode SE is located in the fourth conductive layer LY4. Figure 7B As shown, the shielding electrode SE and the third power line PL3 are located in the fourth conductive layer LY4.

[0120] like Figure 6B , Fig.6D , Fig. 7A ,as well as Figure 7B As shown, the first initialization signal line INL1, the first reset control signal line RST1, the gate line GT, the light emitting control signal line EML, the second initialization signal line INL2 and the second reset control signal line RST2 all extend along the first direction X. Figure 6B , Fig.6D , Fig. 7A,as well as Figure 7B As shown, the data line DT and the first power line PL1 both extend along the second direction Y.

[0121] In the embodiments of the present disclosure, the orthographic projection of component A on substrate BS falls within the orthographic projection of component B on substrate BS means that the orthographic projection of component A on substrate BS completely falls within the orthographic projection of component B on substrate BS, that is, the orthographic projection of component A on substrate BS covers the orthographic projection of component B on substrate BS, and the area of ​​the orthographic projection of component A on substrate BS is less than or equal to the area of ​​the orthographic projection of component B on substrate BS.

[0122] For example, in some embodiments of the present disclosure, each pixel circuit 100a is provided with any shielding electrode SE as described above. That is, no matter the first pixel circuit 10 of the first pixel unit 101 or the second pixel circuit 20 of the second pixel unit 102, it is provided with any shielding electrode SE as described above. Fig. 6F It is shown that the first pixel circuit 10 of the first pixel unit 101 includes a shielding electrode SE, and the second pixel circuit 20 of the second pixel unit 102 includes a shielding electrode SE. Of course, the shielding electrode SE may also be in other forms, for example, Fig. 6F The shield electrode shown can also be replaced by Fig. 7A The shield electrode shown or Figure 7B Shield electrode shown.

[0123] For example, the transistors in the pixel circuit of the embodiment of the present disclosure are all thin film transistors. For example, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, and the fourth conductive layer LY4 are all made of metal materials. For example, the first conductive layer LY1 and the second conductive layer LY2 are formed of metal materials such as nickel and aluminum, but not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are formed of materials such as titanium and aluminum, but not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are respectively formed of three sub-layers of Ti / AL / Ti, but not limited thereto. For example, the substrate substrate can be a glass substrate or a polyimide substrate, but not limited thereto, and can be selected as needed. For example, the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer IS4, the fifth insulating layer ISL5, and the sixth insulating layer ISL6 are all made of insulating materials. The materials of the first pole E1 and the second pole E2 of the light-emitting element can be selected as needed. In some embodiments, the first pole E1 can be made of at least one of a transparent conductive metal oxide and silver, but not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode E1 may adopt a structure in which three sub-layers of ITO-Ag-ITO are stacked. In some embodiments, the second electrode E2 may be a metal with a low work function, and may be at least one of magnesium and silver, but is not limited thereto.

[0124] For example, referring to the layout diagram and the cross-sectional diagram of the embodiments of the present disclosure, the display panel provided by at least one embodiment of the present disclosure may be manufactured by the following method.

[0125] (1) A buffer layer BL and a spacer layer BR are formed on a base substrate BS.

[0126] (2) A semiconductor thin film is formed on the isolation layer BR.

[0127] (3) Patterning the semiconductor film to form a semiconductor pattern layer.

[0128] (4) A first insulating film is formed on the semiconductor pattern layer.

[0129] (5) A first conductive film is formed on the first insulating film, and the first conductive film is patterned to form a first conductive layer LY1.

[0130] (6) The semiconductor pattern layer is doped using the first conductive layer LY1 as a mask to form an active layer LY0.

[0131] (7) A second insulating film is formed on the first conductive layer LY1.

[0132] (8) A second conductive film is formed on the second insulating layer ISL2, and the second conductive film is patterned to form a second conductive layer LY2.

[0133] (9) A third insulating film is formed on the second conductive layer LY2.

[0134] (10) At least one of the first insulating film, the second insulating film, and the third insulating film is patterned to form a first insulating layer ISL1, a second insulating layer ISL2, and a third insulating layer ISL3 while forming via holes.

[0135] (11) A third conductive film is formed and patterned to form a third conductive layer LY3. Each component in the third conductive layer LY3 is connected to the components located therebelow through via holes.

[0136] (12) A fourth insulating film and a fifth insulating film are formed, and the fourth insulating film and the fifth insulating film are patterned to form a fourth insulating layer ISL4 and a fifth insulating layer ISL5 while forming via holes.

[0137] (13) A fourth conductive film is formed and patterned to form a fourth conductive layer LY4.

[0138] (14) At least one insulating layer is formed and at least one transparent conductive layer is formed, wherein the transparent conductive layer includes the conductive line L1.

[0139] (15) The first electrode E1 of the light-emitting element is formed.

[0140] (16) A pixel definition layer PDL and a spacer layer PS are formed.

[0141] (17) A light-emitting functional layer FL is formed.

[0142] (18) The second electrode E2 of the light-emitting element is formed.

[0143] (19) Forming a packaging layer CPS.

[0144] At least one embodiment of the present disclosure provides a display device, comprising any one of the above-mentioned display panels.

[0145] Fig. 8A and Figure 8B Schematic diagram of a display device provided by an embodiment of the present disclosure. Fig. 8A and Figure 8B As shown, the sensor SS is located on one side of the display panel DS and in the second display area R2. Ambient light can pass through the second display area R2 and be sensed by the sensor SS. Figure 8B As shown, the side of the display panel where the sensor SS is not provided is the display side, which can display images.

[0146] For example, the display device is a full-screen display device with an under-screen camera. For example, the display device includes OLED or a product including OLED. For example, the display device includes any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc., containing the above display panel.

[0147] Fig. 9 for Fig. 6A The working timing diagram of the pixel circuit is shown in FIG. Fig. 9 As shown, in one frame display period, the driving method of the pixel unit includes a first reset stage t1, data writing and threshold compensation, a second reset stage t2, and a light emitting stage t3. When the reset control signal RESET is at a low level, the gate of the driving transistor T1 is reset, and when the scan signal SCAN is at a low level, the first electrode E1 (for example, anode) of the light emitting element 100b is reset. For example, Fig. 6A As shown, when the scan signal SCAN is at a low level, the data voltage VDATA is written, and the threshold voltage Vth of the driving transistor T1 is obtained at the same time, and the data voltage VDADA containing the data information on the data line is stored in the capacitor Cst; when the light-emitting control signal line EML is at a low level, the light-emitting element 100b emits light, and the voltage of the first node N1 (gate point) is maintained (the light-emitting stability of the light-emitting element 100b) by the storage capacitor Cst. In the driving process of the pixel circuit 10, in the light-emitting stage, the storage capacitor is used to maintain the voltage signal so that the potential of its signal holding end can be kept constant, and a voltage is formed between the gate and the source of the driving transistor, thereby controlling the driving transistor to form a driving current, and then driving the light-emitting element 100b to emit light.

[0148] like Fig. 9 As shown, in the reset stage t1 , the light emitting control signal EM is set to a turn-off voltage, the reset control signal RESET is set to a turn-on voltage, and the scan signal SCAN is set to a turn-off voltage.

[0149] like Fig. 9 As shown, in the data writing and threshold compensation stage and the second reset stage t2, the light emitting control signal EM is set to a turn-off voltage, the reset control signal RESET is set to a turn-off voltage, and the scan signal SCAN is set to a turn-on voltage.

[0150] like Fig. 9 As shown, in the light emitting stage t3, the light emitting control signal EM is set to an on voltage, the reset control signal RESET is set to an off voltage, and the scan signal SCAN is set to an off voltage.

[0151] like Fig. 9As shown, the first voltage signal ELVDD and the second voltage signal ELVSS are both constant voltage signals. For example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.

[0152] For example, the turn-on voltage in the embodiments of the present disclosure refers to a voltage that can turn on the first and second electrodes of the corresponding transistor, and the turn-off voltage refers to a voltage that can turn off the first and second electrodes of the corresponding transistor. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V) and the turn-off voltage is a high voltage (e.g., 5V); when the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V) and the turn-off voltage is a low voltage (e.g., 0V). Fig. 9 The driving waveforms shown are all described by taking a P-type transistor as an example. For example, the turn-on voltage is a low voltage (eg, 0V), and the turn-off voltage is a high voltage (eg, 5V), but it is not limited thereto.

[0153] Please also read Fig. 6A and Fig. 9 , in the first reset stage t1, the light control signal EM is a turn-off voltage, the reset control signal RESET is a turn-on voltage, and the scan signal SCAN is a turn-off voltage. At this time, the first reset transistor T6 is in a conducting state, while the second reset transistor T7, the data writing transistor T2, the threshold compensation transistor T3, the first light control transistor T4, and the second light control transistor T5 are in a turn-off state. The first reset transistor T6 transmits the first initialization signal (initialization voltage Vinit) Vinit1 to the gate of the driving transistor T1 and is stored by the storage capacitor Cst, resetting the driving transistor T1 and eliminating the data stored in the last (previous frame) light emission.

[0154] In the data writing and threshold compensation and second reset stage t2, the light control signal EM is a turn-off voltage, the reset control signal RESET is a turn-off voltage, and the scan signal SCAN is an on voltage. At this time, the data writing transistor T2 and the threshold compensation transistor T3 are in an on state, the second reset transistor T7 is in an on state, and the second reset transistor T7 transmits the second initialization signal (initialization voltage Vinit) Vinit2 to the first pole E1 of the light emitting element 100b to reset the light emitting element 100b. The first light emitting control transistor T4, the second light emitting control transistor T5, and the first reset transistor T6 are in an off state. At this time, the data writing transistor T2 transmits the data voltage VDATA to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and writes the data voltage VDATA to the first pole of the driving transistor T1 according to the scan signal SCAN. The threshold compensation transistor T3 is turned on to connect the driving transistor T1 into a diode structure, thereby charging the gate of the driving transistor T1. After charging is completed, the gate voltage of the driving transistor T1 is VDATA+Vth, where VDATA is the data voltage and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and performs threshold voltage compensation on the gate voltage of the driving transistor T1 according to the scan signal SCAN. At this stage, the voltage difference across the storage capacitor Cst is ELVDD-VDATA-Vth.

[0155] In the light-emitting stage t3, the light-emitting control signal EM is the on voltage, the reset control signal RESET is the off voltage, and the scan signal SCAN is the off voltage. The first light-emitting control transistor T4 and the second light-emitting control transistor T5 are in the on state, while the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6 and the second reset transistor T7 are in the off state. The first voltage signal ELVDD is transmitted to the first electrode of the driving transistor T1 through the first light-emitting control transistor T4, and the gate voltage of the driving transistor T1 is maintained at VDATA+Vth. The light-emitting current I flows into the light-emitting element 100b through the first light-emitting control transistor T4, the driving transistor T1 and the second light-emitting control transistor T5, and the light-emitting element 100b emits light. That is, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 receive the light-emitting control signal EM, and control the light-emitting element 100b to emit light according to the light-emitting control signal EM. The light-emitting current I satisfies the following saturation current formula:

[0156] K(Vgs-Vth) 2 =K(VDATA+Vth-ELVDD-Vth) 2 =K(VDATA-ELVDD) 2

[0157] in, μ n is the channel mobility of the driving transistor, Cox is the channel capacitance per unit area of ​​the driving transistor T1, W and L are the channel width and channel length of the driving transistor T1 respectively, and Vgs is the voltage difference between the gate and the source (ie, the first electrode of the driving transistor T1 in this embodiment) of the driving transistor T1.

[0158] It can be seen from the above formula that the current flowing through the light emitting element 100b has nothing to do with the threshold voltage of the driving transistor T1. Therefore, the pixel circuit can very well compensate for the threshold voltage of the driving transistor T1.

[0159] For example, the proportion of the duration of the light-emitting stage t3 in one frame display time period can be adjusted. In this way, the light brightness can be controlled by adjusting the proportion of the duration of the light-emitting stage t3 in one frame display time period. For example, the proportion of the duration of the light-emitting stage t3 in one frame display time period can be adjusted by controlling the scanning drive circuit in the display panel or an additional drive circuit.

[0160] For example, the present disclosure is not limited to Fig. 6A The specific pixel circuit shown may adopt other pixel circuits that can realize compensation for the driving transistor. Based on the description and teaching of the implementation method disclosed in this disclosure, other configuration methods that can be easily thought of by ordinary technicians in this field without creative work are all within the protection scope of this disclosure.

[0161] The above description is made using a 7T1C pixel circuit as an example, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin-film transistors and the number of capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, and the embodiments of the present disclosure do not limit this. Of course, the display panel may also include a pixel circuit with less than 7 transistors.

[0162] In the embodiments of the present disclosure, the components located in the same layer may be formed by the same film layer through the same patterning process. For example, the components located in the same layer may be located on the surface of the same component away from the substrate.

[0163] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of the layer or region is exaggerated. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be an intermediate element.

[0164] In the embodiments of the present disclosure, the patterning or patterning process may include only the photolithography process, or include the photolithography process and the etching step, or may include other processes such as printing and inkjetting for forming a predetermined pattern. The photolithography process refers to a process including film formation, exposure, and development, and a pattern is formed using a photoresist, a mask, an exposure machine, etc. The corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

[0165] In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0166] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, comprising: substrate substrate; A pixel unit, located on the substrate, comprises a pixel circuit and a light emitting element, wherein the pixel circuit is configured to drive the light emitting element, the pixel circuit comprises a driving transistor, and the driving transistor comprises a gate; A first gate signal line connected to the gate of the driving transistor; a constant voltage line, configured to provide a first constant voltage to the pixel circuit; a shielding electrode connected to the constant voltage line, wherein the orthographic projection of the first gate signal line on the base substrate falls within the orthographic projection of the shielding electrode on the base substrate, A distance between an orthographic projection of the first gate signal line on the base substrate and a boundary of an orthographic projection of the shielding electrode on the base substrate is greater than or equal to 1.75 μm.

2. The display panel according to claim 1, wherein: The orthographic projection of the shielding electrode on the base substrate covers the orthographic projection of the first gate signal line on the base substrate, and the orthographic projection area of ​​the shielding electrode on the base substrate is larger than the orthographic projection area of ​​the first gate signal line on the base substrate.

3. The display panel according to claim 1, wherein: The orthographic projection of the gate of the driving transistor on the base substrate falls within the orthographic projection of the shielding electrode on the base substrate.

4. The display panel according to any one of claims 1 to 3, further comprising a second gate signal line, wherein: The second gate signal line is connected to the first gate signal line, and an orthographic projection of the second gate signal line on the base substrate falls within an orthographic projection of the shielding electrode on the base substrate.

5. The display panel according to claim 4, wherein: The first gate signal line and the second gate signal line are made of different materials.

6. The display panel according to claim 4, wherein: The material of the first gate signal line includes metal, and the material of the second gate signal line includes a conductive material formed by converting a semiconductor material into a conductor.

7. The display panel according to any one of claims 1 to 3, wherein: The pixel circuit also includes a first reset transistor and a first initialization signal line, the first reset transistor is connected to the second gate signal line, the first electrode of the first reset transistor is connected to the first initialization signal line, and the second gate signal line is multiplexed as the second electrode of the first reset transistor.

8. The display panel according to claim 7, wherein: The constant voltage line includes the first initialization signal line.

9. The display panel according to claim 7, wherein: The display panel further includes a first power line, the first power line is configured to provide a first power voltage to the pixel circuit, and the pixel circuit further includes a storage capacitor. A first end of the storage capacitor is connected to the gate of the driving transistor, and a second end of the storage capacitor is connected to the first power line.

10. The display panel according to claim 9, wherein: The constant voltage line includes the first power line.

11. The display panel according to claim 9 or 10, further comprising a third power supply line, wherein: The third power line is connected in parallel with the first power line, the shielding electrode and the third power line are an integrated structure, and the third power line and the first power line have the same extension direction.

12. The display panel according to any one of claims 1 to 3, wherein: The display panel includes a first display area and a second display area, the first display area is located at least on one side of the second display area, The pixel unit includes a first pixel unit and a second pixel unit. The pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area, The pixel circuit of the second pixel unit is located in the first display area, and the light emitting element of the second pixel unit is located in the second display area. The pixel circuit of the second pixel unit is connected to the light emitting element of the second pixel unit through a conductive line, The orthographic projection of the conductive line on the substrate overlaps with the orthographic projection of the pixel circuit of the first pixel unit on the substrate. In a direction perpendicular to the base substrate, the shielding electrode is located between the conductive line and the first gate signal line.

13. The display panel according to claim 12, wherein: An orthographic projection of the conductive line on the base substrate partially overlaps with an orthographic projection of the first gate signal line in the pixel circuit of the first pixel unit.

14. The display panel according to claim 9, further comprising gate lines and data lines, wherein: The gate line is configured to provide a scan signal to the pixel circuit, and the data line is configured to provide a data signal to the pixel circuit; The pixel circuit further includes a data writing transistor, a gate of the data writing transistor is connected to the gate line, a first electrode of the data writing transistor is connected to the data line, and a second electrode of the data writing transistor is connected to the first electrode of the driving transistor.

15. The display panel according to claim 14, further comprising a stopper, wherein the stopper is connected to the first power line, The pixel circuit further comprises a threshold compensation transistor, wherein a first electrode of the threshold compensation transistor is connected to a second electrode of the driving transistor, and a second electrode of the threshold compensation transistor is connected to a gate electrode of the driving transistor; and the gate electrode of the threshold compensation transistor is connected to the gate line; The gate of the driving transistor is connected to the second electrode of the threshold compensation transistor through the first gate signal line. The threshold compensation transistor includes a first channel and a second channel, wherein the first channel and the second channel are connected via a conductive connection portion; An orthographic projection of the block on the substrate at least partially overlaps with an orthographic projection of the conductive connection portion of the threshold compensation transistor on the substrate.

16. The display panel according to claim 15, wherein: An orthographic projection of the block on the base substrate partially overlaps with an orthographic projection of the second gate signal line on the base substrate.

17. The display panel according to any one of claims 1 to 3, further comprising a second reset control signal line, wherein: The pixel circuit further includes a second reset transistor, a gate of the second reset transistor is connected to the second reset control signal line, a first electrode of the second reset transistor is connected to the second initialization signal line, and a second electrode of the second reset transistor is connected to the first electrode of the light emitting element.

18. The display panel according to claim 15, further comprising a light emitting control signal line, wherein: The pixel circuit further includes a first light emission control transistor and a second light emission control transistor. The gate of the first light emission control transistor is connected to the light emission control signal line, the first electrode of the first light emission control transistor is connected to the first power supply line, and the second electrode of the first light emission control transistor is connected to the first electrode of the driving transistor; The gate of the second light emission control transistor is connected to the light emission control signal line, the first electrode of the second light emission control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light emission control transistor is connected to the first electrode of the light emitting element.

19. A display device comprising the display panel according to any one of claims 1-18.

20. The display device according to claim 19, further comprising a sensor, wherein: The sensor is located at one side of the display panel.

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