A testing device, a failure analysis method, and a testing system

Abstract

This disclosure provides a testing device, a failure analysis method, and a testing system. The testing device includes a chip stage and a support base for supporting the chip stage. The support base houses a comparison module and an adjustable resistor module. The chip stage carries the chip under test (DUT). The comparison module, connected to the adjustable resistor module, compares the ground voltage of the layer under test in the DUT with the ground voltage of the chip stage. Based on the comparison result and the ground resistance of the layer under test by the adjustable resistor module, the comparison module adjusts the resistance to reduce the surface charge effect of the layer under test. This disclosure reduces signal interference between the ground point of the layer under test and the ground point of the chip stage, improves the imaging effect of EBAC (Electronic Electron Diagnostics Analysis), and enables rapid and accurate location of the failure point during failure analysis of the DUT.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit failure analysis technology, and in particular to a test device, failure analysis method and test system. Background Technology

[0002] As the critical dimensions of chips continue to shrink, the interconnection and integration of metals inside the chip becomes increasingly higher. Whether between metals in the same layer or between different metal layers, the isolation material becomes thinner and thinner, which often leads to various failure phenomena inside the chip, such as short circuits, open circuits, micro-leakage, or high resistance.

[0003] When analyzing these failure phenomena of metal layers, for short circuits or open circuits, obvious anomalies can be observed through optical or electron microscopy; for microleakage or high resistance, such failures usually manifest as very small tangles between metal lines, making it difficult to locate the failure location; the electron beam absorbed current (EBAC) function of nanoprobes is an effective technique for locating microleakage and high resistance. Summary of the Invention

[0004] This disclosure provides a testing device, a failure analysis method, and a testing system:

[0005] In a first aspect, embodiments of this disclosure provide a testing device, the testing device including a chip stage and a support base for supporting the chip stage, wherein a comparison module and an adjustable resistor module are disposed within the support base; wherein:

[0006] The chip carrier is used to support the chip under test;

[0007] The comparison module, connected to the adjustable resistor module, is used to compare the ground voltage of the test layer in the chip under test with the ground voltage of the chip stage. Based on the comparison result and the adjustable resistor module, the ground resistance of the test layer is adjusted to reduce the surface charge effect of the test layer.

[0008] In some embodiments, the support base is further provided with a first metal probe and a second metal probe; wherein:

[0009] One end of the first metal probe is connected to the first input terminal of the comparison module, and the other end of the first metal probe is connected to the grounding point on the layer to be tested, for obtaining the grounding voltage of the layer to be tested.

[0010] One end of the second metal probe is connected to the second input terminal of the comparison module, and the other end of the second metal probe is connected to the grounding point on the chip stage to obtain the grounding voltage of the chip stage.

[0011] In some embodiments, the first metal probe and the second metal probe each independently include a nanoprobe.

[0012] In some embodiments, the support base further comprises a first signal testing unit and a second signal testing unit; wherein:

[0013] The first signal testing unit is used to measure the ground voltage of the layer under test through the first metal probe, and to provide the measured ground voltage of the layer under test to the first input terminal of the comparison module;

[0014] The second signal testing unit is used to measure the ground voltage of the chip stage through the second metal probe, and to provide the measured ground voltage of the chip stage to the second input terminal of the comparison module;

[0015] The first signal testing unit is connected between one end of the first metal probe and the first input terminal of the comparison module, and the second signal testing unit is connected between one end of the second metal probe and the second input terminal of the comparison module.

[0016] In some embodiments, the adjustable resistor module is used to adjust the resistance value corresponding to the voltage difference between the ground voltage of the layer to be tested and the ground voltage of the chip stage after determining the voltage difference.

[0017] In some embodiments, there is a corresponding relationship between the voltage difference and the grounding resistance; wherein:

[0018] If the voltage difference increases, the grounding resistance decreases;

[0019] If the voltage difference decreases, the grounding resistance increases.

[0020] In some embodiments, the chip under test includes at least one metal layer and at least one dielectric layer, wherein the at least one metal layer includes the layer to be tested; wherein:

[0021] The comparison module is further configured to perform a differential comparison based on the ground voltage of the layer under test and the ground voltage of the chip stage, so as to reduce the interference signal generated by the metal layer and dielectric layer contained between the layer under test and the chip stage in the chip under test.

[0022] In some embodiments, the comparison module includes a first operational amplifier, a second operational amplifier, a first transistor, a second transistor, a first resistor, a second resistor, and a third transistor; the adjustable resistor module includes an adjustable resistor; wherein:

[0023] The negative input terminal of the first operational amplifier is connected to the ground point on the layer under test, the positive input terminal of the second operational amplifier is connected to the ground point on the chip stage, and the positive input terminal of the first operational amplifier is connected to the negative input terminal of the second operational amplifier.

[0024] The output terminal of the first operational amplifier is connected to the input terminal of the first transistor, and the output terminal of the second operational amplifier is connected to the input terminal of the second transistor.

[0025] The output terminal of the first transistor is connected to the output terminal of the second transistor, and is also connected to the first terminal of the first resistor;

[0026] The first end of the second resistor is connected to the input terminal of the third transistor, and the second end of the first resistor, the second end of the second resistor, and the output terminal of the third transistor are all connected to the output terminal of the comparator module.

[0027] The output terminal of the comparison module is connected to the input terminal of the adjustable resistor, the input terminal of the adjustable resistor is also connected to the adjustment terminal of the adjustable resistor, and the output terminal of the adjustable resistor is grounded.

[0028] In some embodiments, the first transistor, the second transistor, and the third transistor are all diodes, and the third transistor is a Zener diode.

[0029] In some embodiments, the support base is further provided with a third metal probe and a fourth metal probe; wherein:

[0030] In the layer to be tested, the third metal probe is connected to the first test point of the layer to be tested, and the fourth metal probe is connected to the second test point of the layer to be tested, for measuring whether there is a failure point between the first test point and the second test point.

[0031] In a second aspect, embodiments of this disclosure provide a failure analysis method applied to a test device as described in any of the first aspects, the method comprising:

[0032] Provide the chip under test;

[0033] The chip under test is placed on the upper surface of the chip stage;

[0034] Provide driving current to the layer under test in the chip under test;

[0035] Obtain the analysis image of the layer under test under the driving current;

[0036] Based on the analyzed image, determine whether there are any failure points in the layer to be tested.

[0037] In some embodiments, before providing a drive current to the layer under test in the chip under test, the method further includes:

[0038] The ground voltage of the layer under test is obtained by the first metal probe, and the ground voltage of the chip stage is obtained by the second metal probe.

[0039] The grounding resistance value is determined based on the grounding voltage of the layer to be tested and the grounding voltage of the chip stage.

[0040] The resistance value of the adjustable resistor module is adjusted so that the adjusted resistance value is equal to the grounding resistance value;

[0041] Wherein, one end of the first metal probe is connected to the first input terminal of the comparison module, and the other end of the first metal probe is connected to the ground point on the layer to be tested; one end of the second metal probe is connected to the second input terminal of the comparison module, and the other end of the second metal probe is connected to the ground point on the chip stage.

[0042] In some embodiments, obtaining the ground voltage of the layer under test through a first metal probe includes:

[0043] With one end of the first metal probe connected to the ground point on the layer to be tested and the other end of the first metal probe connected to the first signal testing unit, the ground voltage of the layer to be tested is measured by the first signal testing unit, and the measured ground voltage of the layer to be tested is provided to the first input terminal of the comparison module.

[0044] The step of obtaining the ground voltage of the chip stage through the second metal probe includes:

[0045] With one end of the second metal probe connected to a ground point on the chip stage and the other end of the second metal probe connected to a second signal testing unit, the ground voltage of the chip stage is measured by the second signal testing unit, and the measured ground voltage of the chip stage is provided to the second input terminal of the comparison module.

[0046] In some embodiments, determining the grounding resistance value based on the grounding voltage of the layer under test and the grounding voltage of the chip stage includes:

[0047] Perform differential calculation on the ground voltage of the layer under test and the ground voltage of the chip stage to determine the voltage difference;

[0048] Based on the preset correspondence between voltage difference and grounding resistance, the grounding resistance corresponding to the voltage difference is determined.

[0049] In some embodiments, based on the preset correspondence between the voltage difference and the grounding resistance, the method further includes:

[0050] If the voltage difference increases, then the grounding resistance value is determined to decrease;

[0051] If the voltage difference decreases, then the grounding resistance value is determined to have increased.

[0052] In some embodiments, providing a drive current to the test layer of the chip under test includes:

[0053] The driving current is provided to the layer under test through the third and fourth metal probes;

[0054] Wherein, one end of the third metal probe is connected to the first test point of the layer to be tested, and the other end of the third metal probe is connected to a current source; one end of the fourth metal probe is connected to the second test point of the layer to be tested, and the other end of the fourth metal probe is grounded.

[0055] In some embodiments, providing the chip under test includes:

[0056] Obtain the chip under test;

[0057] The chip under test is preprocessed to expose the layer to be tested.

[0058] In some embodiments, the failure point includes a high-resistance failure point and / or a microleakage failure point.

[0059] Thirdly, embodiments of this disclosure provide a testing system, including a chip under test and a testing device as described in any of the first aspects; wherein the testing device is used to perform failure analysis on the chip under test.

[0060] This disclosure provides a testing device, a failure analysis method, and a testing system. The testing device includes a chip stage and a support base for supporting the chip stage. The support base houses a comparison module and an adjustable resistor module. The chip stage carries the chip under test (TBD). The comparison module, connected to the adjustable resistor module, compares the ground voltage of the layer under test in the TBD with the ground voltage of the chip stage. Based on the comparison result and the ground resistance of the TBD layer, the adjustable resistor module adjusts the resistance to reduce the surface charge effect of the TBD layer. By incorporating the comparison module and adjustable resistor module within the testing device, signal interference between the TBD layer and the chip stage is reduced. Furthermore, the adjustable resistor module dynamically adjusts the ground resistance of the TBD layer, further reducing the surface charge effect and effectively preventing the risk of probe tip discharge damaging the probe or the TBD chip. It also improves the imaging effect of EBAC (Effective Electron Diagnostic Angiography), facilitating rapid and accurate location of failure points in the TBD layer and increasing the efficiency of failure analysis. Attached Figure Description

[0061] Figure 1A Schematic diagram of a failure phenomenon;

[0062] Figure 1B Schematic diagram two of a failure phenomenon;

[0063] Figure 2A This is a schematic diagram of the structure of a testing machine.

[0064] Figure 2B This is a schematic diagram of the structure of a chip under test.

[0065] Figure 3 This is a schematic diagram of an EBAC image;

[0066] Figure 4 This is a schematic diagram of the composition structure of a testing device provided in an embodiment of the present disclosure;

[0067] Figure 5 A schematic diagram of the specific structure of a testing device provided in an embodiment of this disclosure is shown below;

[0068] Figure 6 This is a detailed structural diagram of a test layer provided in an embodiment of the present disclosure;

[0069] Figure 7 A schematic diagram of the specific structure of a testing device provided in this embodiment of the present disclosure is shown below;

[0070] Figure 8 This disclosure provides a flowchart illustrating a failure analysis method.

[0071] Figure 9This is a schematic diagram of the composition structure of a test system provided in an embodiment of this disclosure. Detailed Implementation

[0072] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0074] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0075] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0076] Chip failures are inevitable during research, development, production, and use. Failure analysis is a necessary means to determine chip failure mechanisms, providing essential information for effective fault diagnosis and guiding design engineers to continuously improve or repair chip designs. For example, failure analysis can identify potential failures during product manufacturing and analyze their causes and mechanisms. This provides a basis and direction for designers of integrated circuits to find design defects, process parameter mismatches, or improper design and operation. It is of great significance for seeking improvement measures, avoiding failures, improving product quality and reliability, and reducing cost losses.

[0077] As the critical dimensions of chips continue to shrink, the interconnection and integration of metals within the chip becomes increasingly higher. Whether between metals in the same layer or between different metal layers, the isolation material becomes thinner and thinner. Various failure phenomena often occur inside the chip, such as short circuits, micro-leakage, high resistance, or open circuits.

[0078] Figure 1A A schematic diagram of a failure phenomenon is shown. For example... Figure 1AAs shown, the nth metal layer and the (n+1)th metal layer are connected by a contact plug. In the contact plug used to connect the nth metal layer and the (n+1)th metal layer, a failure point as shown in the figure appears. Figure 1B Schematic diagram two of a failure phenomenon, such as Figure 1B As shown, a high-resistance failure point appears in the chip illustrated.

[0079] When analyzing the failure phenomena of metal layers, for short circuits or open circuits, obvious abnormalities can be observed through optical or electron microscopy; for microleakage or high resistance, these failures usually manifest as very small tangled connections between metal lines, making it difficult to locate the failure location; the EBAC function of nanoprobes is an effective location technique.

[0080] Figure 2A A schematic diagram of a testing machine is shown. Figure 2A As shown, the dashed circle indicates the chip under test (DUT) placed on the surface of the test stage (Holder, also known as the stage). When performing failure analysis on the DUT, the DUT is placed on the upper surface of the test stage. Probe 1 and Probe 2 are connected to two detection points of the current test layer of the DUT, respectively. Both Probe 1 and Probe 2 are nano probes. Figure 2B for Figure 2A The schematic diagram of the chip under test circled by the dashed circle is shown below. Figure 2B As shown, probe 1 is connected to one detection point, and probe 2 is connected to another detection point. Between the two detection points lies a section of the circuit under test (TBD) within the chip. This circuit encompasses any tiny failure points exhibiting malfunctions. It's understood that the closer the two detection points are to this failure point, the easier it is to detect. Probe 1 can be connected to a current source that provides 10 nanoamps (nA) (or other current values) to the TBD. Probe 2 can be grounded. Under DC bias, an electron-induced change occurs. Due to the presence of tiny failure points, the conductivity varies at different locations within the TBD circuit. In the obtained EBAC image, these tiny failure points will exhibit obvious anomalies, thus enabling the location of the failure point.

[0081] For example, Figure 3 A schematic diagram of an EBAC image is shown. For example... Figure 3 As shown, in the EBAC image, anomalies (EBAC hotspots) that are significantly different from other locations in the image can be located. These anomalies are failure points.

[0082] It should be noted that EBAC can locate high-resistance problems in the range of kiloohms (KΩ) to megaohms (MΩ) (low ΔI), and also low-resistance leakage problems in the range of 100Ω to KΩ (high ΔI). Here, ΔI refers to the current change between probe 1 and probe 2 in the EBAC test mode of the test equipment, which can be understood as ΔI = current value at probe 1 - current value at probe 2.

[0083] When using EBAC to perform failure analysis on the chip under test, micro-leakage or high impedance phenomena are easily masked by stray noise, requiring a lot of time to adjust the machine to minimize the stray noise, and the success rate is also easily affected by various factors.

[0084] Based on this, this disclosure provides a testing device, including a chip stage and a support base for supporting the chip stage, wherein a comparison module and an adjustable resistor module are disposed within the support base; wherein: the chip stage is used to support the chip under test; the comparison module is connected to the adjustable resistor module and is used to compare the ground voltage of the layer under test in the chip under test with the ground voltage of the chip stage, and adjust the ground resistance of the layer under test according to the comparison result and the adjustable resistor module to reduce the surface charge effect of the layer under test. Thus, by setting the comparison module and the adjustable resistor module inside the testing device, not only can signal interference between the layer under test and the chip stage be reduced, but the surface charge effect of the layer under test can also be reduced by dynamically adjusting the ground resistance of the layer under test through the adjustable resistor module, effectively avoiding the risk of probe tip discharge damaging the probe or the chip under test, and also improving the imaging effect of EBAC, which is beneficial for quickly and accurately locating failure points in the layer under test and improving the efficiency of failure analysis.

[0085] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0086] In one embodiment of this disclosure, see [link to embodiment]. Figure 4 This illustrates a schematic diagram of the composition of a testing device 10 provided in an embodiment of this disclosure. For example... Figure 4 As shown, the test device 10 may include a chip stage 101 and a support base 102 for supporting the chip stage 101, and the support base 102 is provided with a comparison module 103 and an adjustable resistor module 104; wherein,

[0087] Chip stage 101 is used to support the chip under test 20;

[0088] The comparison module 103, connected to the adjustable resistor module 104, is used to compare the ground voltage of the test layer in the chip under test 20 with the ground voltage of the chip platform 101. Based on the comparison result and the adjustable resistor module 104, the ground resistance of the test layer is adjusted to reduce the surface charge effect of the test layer.

[0089] It should be noted that the test equipment 10 provided in this embodiment can be a test machine used to perform failure analysis on the chip under test 20 in order to determine the small failure points such as high resistance and microleakage in the chip under test 20.

[0090] It should also be noted that when performing failure analysis on the chip under test 20, the chip under test 20 is placed on the upper surface of the chip stage 20. The two input terminals of the comparison module 103 receive the ground voltage of the layer under test in the chip under test 20 and the ground voltage of the chip stage 101 (specifically, the ground voltage of the upper surface of the chip stage 101). Then, a differential comparison is performed between the ground voltage of the layer under test and the ground voltage of the chip stage 101, thereby effectively shielding the interference signal between the ground point of the layer under test in the chip under test and the ground point of the chip stage, achieving surface noise reduction of the chip under test, improving the signal-to-noise ratio of the failure point signal, and reducing the influence of interference signals. Consequently, when performing failure analysis on the chip under test, the imaging effect of EBAC can be improved, and the failure point can be located accurately and quickly, improving efficiency.

[0091] It should also be noted that after comparing the grounding voltage of the layer to be tested with the grounding voltage of the chip stage 101, the resistance value of the adjustable resistor module 104 can be adjusted according to the comparison result, which can also realize the adjustment of the grounding resistance of the layer to be tested in the chip under test 20.

[0092] Here, the value of the grounding resistor directly affects the efficiency of the electron-guided ground terminal of the test layer in the chip under test 20, i.e., it directly affects the charging effect. Based on the comparison between the grounding voltage of the test layer and the grounding voltage of the chip stage 101, the resistance value of the adjustable resistor module 104 is adjusted to reduce the charging effect on the surface of the test layer. In this way, when using EBAC to perform failure analysis on the chip under test, not only can the grounding resistance value of the test layer be dynamically adjusted to reduce the charging effect and obtain a high-quality EBAC image, but also, because the charging effect on the surface of the test layer is reduced, the trial and error risk of the probe probing the surface of the test layer can be reduced, effectively avoiding the damage to the probe or the chip under test caused by tip discharge.

[0093] Further, see Figure 5 This illustrates a schematic diagram of the specific structure of a testing device 10 provided in an embodiment of this disclosure. In some embodiments, such as Figure 5 As shown, the support base 102 is also provided with a first metal probe 105 and a second metal probe 106; wherein:

[0094] One end of the first metal probe 105 is connected to the first input terminal of the comparison module 103, and the other end of the first metal probe 105 is connected to the grounding point GND1 on the layer to be tested, in order to obtain the grounding voltage of the layer to be tested.

[0095] One end of the second metal probe 106 is connected to the second input terminal of the comparison module 103, and the other end of the second metal probe 106 is connected to the grounding point GND2 on the chip stage 101 to obtain the grounding voltage of the chip stage 101.

[0096] It should be noted that the comparison module 103 may include two input terminals: a first input terminal and a second input terminal. The first metal probe 105 connects the first input terminal to the ground point GND1 of the layer under test of the chip 20, thereby enabling the acquisition of the ground voltage U on the surface of the layer under test. RH The second metal probe 106 connects the second input terminal to the grounding point GND2 on the upper surface of the chip stage 101, thereby enabling the acquisition of the grounding voltage U on the surface of the chip stage 101. RL .

[0097] It should also be noted that, such as Figure 5 As shown, in the support base 102, two interfaces are provided on the left side of the comparison module 103. Among them, one is marked with U. RH The interface is for connecting the first input terminal of the comparison module 103 to the first metal probe 105. That is, the first metal probe 105 can be mounted on a connecting line, which is inserted into the interface to connect the first metal probe to the first input terminal of the comparison module 103; marked with U... RL The interface is used to connect the second input terminal of the comparison module 103 to the second metal probe 106. In other words, the second metal probe 106 can be set on a connecting line and the connecting line can be inserted into the interface to connect the second metal probe and the second input terminal of the comparison module 103.

[0098] Furthermore, such as Figure 5 As shown, in some embodiments, the support base 102 is further provided with a third metal probe 107 and a fourth metal probe 108; wherein:

[0099] In the layer to be tested, the third metal probe 107 is connected to the first test point of the layer to be tested, and the fourth metal probe 108 is connected to the second test point of the layer to be tested, for measuring whether there is a failure point between the first test point and the second test point.

[0100] It should be noted that the aforementioned first metal probe 105 and second metal probe 106 are respectively connected to the grounding point GND1 of the layer under test and the grounding point GND2 of the chip stage 101, and are used to measure the grounding voltage at the corresponding locations. The test equipment 10 also includes a third metal probe 107 and a fourth metal probe 108, which are respectively connected to the first test point and the second test point of the layer under test. The circuit under test in the layer under test is located between the first test point and the second test point. A driving current is provided to this section of the circuit under test through the third metal probe 107 and the fourth metal probe 108, and an EBAC image of the layer under test under this driving current is acquired using an imaging device such as a microscope. This allows for the determination of whether there are any failure points in the layer under test of the chip under test from the acquired EBAC image.

[0101] Normally, if there are no failure points, the EBAC image is uniform overall. However, if there are failure points, there will be obvious abnormal points in the EBAC image that are different from other locations. The location of the abnormal point in the EBAC image is the failure point in the chip under test.

[0102] In the embodiments of this disclosure, the first metal probe and the second metal probe each independently include a nanoprobe; for example, both can be nanoprobes, and the third metal probe and the fourth metal probe can also both be nanoprobes. In this way, nanoprobes can be used to perform nanoscale failure analysis on the chip under test, such as measuring electrical characteristic parameters (e.g., ground voltage measurement) and locating nanoscale failure points (e.g., high resistance or microleakage).

[0103] For example, see Figure 6 This illustrates a detailed structural diagram of a test layer provided in an embodiment of this disclosure. For example... Figure 6 As shown, the first test point and the second test point are the two endpoints of the metal wire segment, and the metal wire between the first test point and the second test point is the circuit under test. Figure 6 The image also shows the grounding point GND1 of the chip under test.

[0104] Figure 6 This diagram illustrates two types of failure points: high resistance and microleakage. These failure points may be caused by circuit design or manufacturing defects. At the high resistance failure point, the resistance of the metal wires is significantly increased, exceeding that at other locations. At the microleakage failure point, two metal wires that should be insulated from each other are in contact, causing leakage. High resistance and microleakage are very small defects in the circuit, unlike larger defects such as short circuits or open circuits; locating high resistance and microleakage is more difficult and complex.

[0105] It should also be noted that one end of the third metal probe 107 is connected to the first test point of the layer under test, and the other end can be connected to a current source. One end of the fourth metal probe 108 is connected to the second test point of the layer under test, and the other end can be grounded, thereby providing drive current to the chip under test through the current source. In this way, EBAC is used to locate small defects such as high resistance / microleakage.

[0106] In other words, in this embodiment of the present disclosure, the test equipment contains at least two pairs of metal probes. One pair consists of a first metal probe and a second metal probe. The first metal probe is used to connect the ground point of the test layer of the chip under test to the first input terminal of the comparison module. The second metal probe is used to connect the ground point of the chip stage to the second input terminal of the comparison module and provide the ground voltage of the two ground points to the comparison module. The comparison module compares the two ground voltages and adjusts the resistance value of the adjustable resistor module according to the comparison result to reduce the charging effect on the surface of the chip under test. Thus, when locating the failure point through EBAC, a high-quality EBAC image can be obtained, and the failure point can be located quickly and accurately. The other pair consists of a third metal probe 107 and a fourth metal probe 108, which are used to introduce driving current to realize the detection of failure points in the test layer of the chip under test using EBAC.

[0107] It should also be noted that the first metal probe 105, the second metal probe 106, the third metal probe 107, and the fourth metal probe 108 can all be nanoprobes. Figure 5 In order to distinguish them, different fillers are used.

[0108] It should also be noted that, such as Figure 5 As shown, the chip under test 20 may include multiple metal layers ( Figure 5 The diagram shows two metal layers (first metal layer 203 and second metal layer 205). Failure points can exist in one or more metal layers. When performing failure analysis on the chip under test 20, it is necessary to preprocess the chip under test 20 to prepare the layers to be tested (in...) Figure 5 In the middle, the layer to be tested, namely the second metal layer 205, is exposed, which facilitates analysis and detection.

[0109] Furthermore, in some embodiments, the support base is also provided with a first signal testing unit and a second signal testing unit; wherein:

[0110] The first signal testing unit is used to measure the ground voltage of the layer under test through the first metal probe, and to provide the measured ground voltage of the layer under test to the first input terminal of the comparison module.

[0111] The second signal testing unit is used to measure the ground voltage of the chip stage through the second metal probe, and to provide the measured ground voltage of the chip stage to the second input terminal of the comparison module.

[0112] The first signal testing unit is connected between one end of the first metal probe and the first input terminal of the comparison module, and the second signal testing unit is connected between one end of the second metal probe and the second input terminal of the comparison module.

[0113] It should be noted that the ground voltage can be tested using a Signal Measurement Unit (SMU). In this embodiment, two signal measurement units (a first signal measurement unit and a second signal measurement unit) are provided in the support base, respectively for measuring the ground voltage of the layer under test and the ground voltage of the chip stage, and providing the two test voltages to the first and second input terminals of the comparison module, respectively. Furthermore, the test equipment can also be configured with or connected to a display screen. After measuring the two ground voltages, the first and second signal measurement units can display the specific voltage values ​​on the display screen.

[0114] As mentioned above, microleakage or high impedance phenomena are easily masked by stray signals. Analysis shows that this is related to the grounding resistance of the test equipment on the one hand, and to the stray signals (also known as interference signals) from the layer under test and the underlying metal layer, dielectric layer (insulating layer), etc.

[0115] Theoretically, the potential of the grounding point of the layer under test and the grounding point on the upper surface of the chip substrate are always the same. However, interference signals exist due to interference from metal layers, dielectric layers, etc. Differential noise reduction using the comparison module 103 can effectively shield interference signals and achieve surface noise reduction of the chip under test. Therefore, in some embodiments, such as Figure 5 As shown, the chip under test 20 includes at least one metal layer and at least one dielectric layer, wherein the at least one metal layer includes the layer to be tested; wherein:

[0116] The comparison module 103 is also used to perform differential comparison based on the ground voltage of the test layer and the ground voltage of the chip stage 101, so as to reduce the interference signal generated by the metal layer and dielectric layer contained between the test layer and the chip stage 101 in the chip under test 20.

[0117] It should be noted that, in Figure 5 In this process, the chip under test 20 may include a silicon substrate 201, a first dielectric layer 202, a first metal layer 203, a second dielectric layer 204, and a second metal layer 205. Among them, the second metal layer 205 is the layer to be tested.

[0118] In this embodiment of the present disclosure, the comparison module 103 performs a differential comparison between the ground voltage of the test layer and the ground voltage of the chip stage 101, effectively shielding the interference signals generated by the several metal layers, dielectric layers, etc. that exist between the test layer and the upper surface of the chip stage 101. When performing failure analysis on the chip under test 20, the interference signals can be effectively reduced and the signal-to-noise ratio of the failure point signal can be improved, thereby obtaining better EBAC imaging effect and quickly finding the failure point.

[0119] Furthermore, in embodiments of this disclosure, the comparison module can be implemented using a differential comparator (such as a window comparator), and the adjustable resistor module can be implemented using an adjustable resistor (such as a variable resistor), see [link to relevant documentation]. Figure 7 This illustrates a schematic diagram of the specific structure of a testing device 10 provided in an embodiment of this disclosure. In some embodiments, such as Figure 7 As shown, the comparison module 103 includes a first operational amplifier A1, a second operational amplifier A2, a first transistor D1, a second transistor D2, a first resistor R1, a second resistor R2, and a third transistor D3; the adjustable resistor module 104 includes an adjustable resistor R; wherein:

[0120] The negative input terminal of the first operational amplifier A1 is connected to the ground point GND1 on the layer under test, the positive input terminal of the second operational amplifier A2 is connected to the ground point GND2 on the chip stage 101, and the positive input terminal of the first operational amplifier A1 is connected to the negative input terminal of the second operational amplifier A2.

[0121] The output of the first operational amplifier A1 is connected to the input of the first transistor D1, and the output of the second operational amplifier A2 is connected to the input of the second transistor D2.

[0122] The output terminal of the first transistor D1 is connected to the output terminal of the second transistor D2, and is also connected to the first terminal of the first resistor R1.

[0123] The first end of the second resistor R2 is connected to the input terminal of the third transistor D3, and the second end of the first resistor R1, the second end of the second resistor R2, and the output terminal of the third transistor D3 are all connected to the output terminal of the comparator module 103.

[0124] The output terminal of the comparator module 103 is connected to the input terminal of the adjustable resistor R. The input terminal of the adjustable resistor R is also connected to the adjustment terminal of the adjustable resistor R. The output terminal of the adjustable resistor R is grounded.

[0125] It should be noted that, as Figure 7As shown, to facilitate illustrating the circuit composition and connection relationship of the comparison module 103 and the adjustable resistor module 104, the specific structure of the comparison module 103 is shown in the upper right corner dashed box, and the specific structure of the adjustable resistor module 104 is shown in the lower right corner dashed box. The ground point GND1 of the test layer of the chip under test 20 is connected to the negative input terminal of the first operational amplifier A1 (i.e., the first input terminal of the comparison module 103), and the ground voltage U of the test layer is connected to the first operational amplifier A1. RH The voltage U is obtained by amplification. o1 The grounding point GND2 on the surface of the chip stage 101 is connected to the positive input terminal of the second operational amplifier A2 (i.e., the second input terminal of the comparator module 103), and the grounding voltage U of the second operational amplifier A2 to the chip stage 101 is... RL The voltage U is obtained by amplification. o2 Then, after passing through the first transistor D1, the second transistor D2, the first resistor R1, the second resistor R2, and the third transistor D3, the output voltage U of the comparator module is finally obtained at the output terminal of the comparator module 103. o The input voltage U o This serves as the input voltage for the adjustable resistor module 104.

[0126] It should also be noted that, such as Figure 7 As shown, the adjustable resistor module 104 can be implemented using an adjustable resistor R. Specifically, the adjustable resistor R can be a variable resistor whose resistance value can be adjusted. The input voltage U at the input terminal of the adjustable resistor R... in For the output voltage U of the comparator module 103 o The resistance value of the adjustable resistor R can be changed by sliding its adjustment terminal. Figure 7 In the middle, sliding the adjustment terminal upwards increases the resistance of the adjustable resistor R, and sliding the adjustment terminal downwards decreases the resistance of the adjustable resistor R. The voltage at the output terminal of the adjustable resistor R is U. out The output terminal of the adjustable resistor R is grounded.

[0127] It should also be noted that, such as Figure 7 (or Figure 6 As shown in the figure, in the support base 102, the right side of the comparison module is marked with U. o The interface, the adjustable resistor module 104, has markings labeled U on its left and right sides respectively. in and U out The interface is described. Specifically, the right-side interface of the comparator module 103 can be connected to the left-side interface of the adjustable resistor module 104 via a connecting cable, thereby enabling the voltage U output from the output terminal of the comparator module 103 to be... o The input terminal provided to the adjustable resistor module 104 serves as the input voltage U of the adjustable resistor module 104. inThe interface on the right end of the adjustable resistor module 104 can be grounded via a connecting wire, thereby grounding the output terminal of the adjustable resistor module 104. It should also be noted that the first transistor D1, the second transistor D2, and the third transistor D3 are all diodes, and the third transistor D3 is a Zener diode. Thus, the third transistor D3 also serves as a voltage regulator, ensuring a stable output voltage for the comparator module 103.

[0128] Furthermore, for the adjustable resistor module, in some embodiments, the adjustable resistor module is used to adjust the resistance value corresponding to the voltage difference to the ground resistance value corresponding to the voltage difference after determining the voltage difference between the ground voltage of the layer to be tested and the ground voltage of the chip stage.

[0129] It should be noted that, as Figure 7 As shown, a resistance adjustment knob 109 can also be provided in the support base. By rotating the resistance adjustment knob 109, the resistance value of the adjustable resistor module 104 can be adjusted, thereby adjusting the grounding resistance value of the layer under test. In this way, by dynamically changing the grounding resistance value of the layer under test, the charging effect on the surface of the layer under test can be reduced.

[0130] In this embodiment, the resistance adjustment of the adjustable resistor module is based on the ground voltage of the layer under test and the ground voltage of the chip stage. The difference between the ground voltage of the layer under test and the ground voltage of the chip stage is defined as the voltage difference. There is a corresponding relationship between this voltage difference and the ground resistance. Analysis shows that if the voltage difference increases, the ground resistance decreases; if the voltage difference decreases, the ground resistance increases.

[0131] It should also be noted that the specific correspondence between voltage difference and grounding resistance can be determined by performing failure analysis on several sample chips and adjusting the resistance value of the adjustable resistor module 104 during the analysis process, so that the resistance value corresponding to the best imaging effect is determined as the grounding resistance corresponding to the current voltage difference.

[0132] For example, Table 1 is an exemplary correspondence between voltage difference and grounding resistance.

[0133] Table 1

[0134] <![CDATA[Voltage difference (V) = U RH -U RL > <![CDATA[R W (Oh)]]> -5 150 -4 120 -3 100 -2 80 0 60 +2 50 +3 40 +4 25 +5 10

[0135] It should be noted that Table 1 shows the voltage difference (U) RH -U RL (Unit: Volts / V) and grounding resistance (R) WExample of the correspondence (unit: ohms / Ω), where the voltage difference is the difference between the ground voltage of the layer under test and the ground voltage of the chip stage, and the ground resistance is the resistance value of the adjustable resistor module corresponding to the voltage difference when the imaging effect is best. It can also be understood as the resistance value of the ground resistance of the layer under test of the chip.

[0136] Based on the correspondence shown in Table 1, when performing failure analysis on the chip under test, the resistance value of the adjustable resistor module can be adjusted to the corresponding grounding resistance value according to the voltage difference, thereby realizing dynamic adjustment of the grounding resistance value, improving the charging effect on the surface of the chip under test, and obtaining the best EBAC imaging effect.

[0137] In short, this disclosure presents a novel testing apparatus (i.e., testing equipment 10) designed to address the difficulty in locating micro-leakage or high-resistivity defects. It reduces the influence of stray signals and improves the efficiency and success rate of failure point location. The overall concept of this disclosure is to integrate a window comparator and a variable resistor onto an existing testing apparatus to achieve surface noise reduction and dynamic adjustment of the grounding resistance of the sample (i.e., the chip under test).

[0138] For window comparators, the differential comparison method is used to effectively shield the interference signals generated by several metal layers and dielectric layers between the ground point of the layer under test and the upper surface of the chip carrier.

[0139] For rheostats, dynamically adjusting the grounding resistance of the grounding point of the layer under test can improve the surface charging effect of the sample, thereby obtaining the best imaging effect. At the same time, since the grounding resistance can be adjusted according to the voltage difference, there is no need to adjust the probe multiple times, which can also reduce the trial and error risk when the probe is probed (tip discharge).

[0140] This disclosure provides a testing device, including a chip stage and a support base for supporting the chip stage. The support base houses a comparison module and an adjustable resistor module. The chip stage carries the chip under test (DUT). The comparison module, connected to the adjustable resistor module, compares the ground voltage of the layer under test in the DUT with the ground voltage of the chip stage. Based on the comparison result and the ground resistance of the layer under test, the adjustable resistor module adjusts the resistance to reduce the surface charge effect of the layer under test. By incorporating the comparison module and adjustable resistor module within the testing device, signal interference between the layer under test and the chip stage is reduced. Furthermore, the dynamic adjustment of the ground resistance of the layer under test by the adjustable resistor module further reduces the surface charge effect, effectively preventing the risk of probe tip discharge damaging the probe or the DUT. This also shortens the time required for debugging the testing device, improves the imaging effect of EBAC (Electronic Electron Diagnostics Analysis), facilitates rapid and accurate location of failure points in the layer under test, and improves the efficiency of failure analysis.

[0141] In another embodiment of this disclosure, see Figure 8 This illustrates a flowchart of a failure analysis method provided in an embodiment of this disclosure. Figure 8 As shown, the method may include:

[0142] S301 provides the chip under test.

[0143] S302. Place the chip to be tested on the upper surface of the chip stage.

[0144] It should be noted that the testing method provided in this disclosure is applied to the testing device 10 in the foregoing embodiments, and the failure analysis of the chip under test is realized based on the testing device.

[0145] It should also be noted that when performing failure analysis on the chip under test, the layer to be tested on the chip under test must first be exposed. Therefore, in some embodiments, the chip under test may include:

[0146] Obtain the chip under test;

[0147] The chip under test is preprocessed to expose the layer to be tested.

[0148] It should be noted that the process begins with acquiring the chip under test (DUT) for failure analysis. The DUT is then pre-processed to expose the layers to be tested. Pre-processing methods can include grinding or etching to remove the upper packaging structure or all packaging structures of the DUT. Then, devices such as photodetectors can be used for preliminary defect localization. After locating the approximate defect location, metal layers, dielectric layers, etc., are further removed from the DUT, thus exposing the layers to be tested. The pre-processed DUT is then placed on the upper surface of a chip stage for failure analysis.

[0149] S303 provides drive current to the layer under test in the chip under test.

[0150] S304. Obtain the analysis image of the layer under test under the driving current.

[0151] It should be noted that the embodiments of this disclosure utilize EBAC to locate the failure point of the chip under test. In order to eliminate the interference of interference signals on the EBAC imaging effect and the influence of grounding resistance on the EBAC imaging effect, a comparison module and an adjustable resistor module are integrated in the test equipment to realize differential noise reduction and dynamic adjustment of the grounding resistance of the layer under test, thereby obtaining an EBAC image with good imaging effect for use as an analysis image.

[0152] Therefore, in some embodiments, the method may further include the following before providing a drive current to the layer under test in the chip under test:

[0153] The ground voltage of the layer to be tested is obtained through the first metal probe, and the ground voltage of the chip stage is obtained through the second metal probe.

[0154] Determine the grounding resistance value based on the grounding voltage of the layer to be tested and the grounding voltage of the chip stage;

[0155] The resistance value of the adjustable resistor module is adjusted so that the adjusted resistance value is equal to the grounding resistance value;

[0156] One end of the first metal probe is connected to the first input terminal of the comparison module, and the other end of the first metal probe is connected to the ground point on the layer to be tested; one end of the second metal probe is connected to the second input terminal of the comparison module, and the other end of the second metal probe is connected to the ground point on the chip stage.

[0157] It should be noted that the first metal probe is connected between the first input terminal of the comparator module and the ground point on the layer under test, thereby obtaining the ground voltage of the layer under test through the first metal probe; the second metal probe is connected between the second input terminal of the comparator module and the ground point on the chip stage, thereby obtaining the ground voltage of the chip stage through the second metal probe.

[0158] More specifically, embodiments of this disclosure can determine the specific values ​​of the ground voltage of the layer under test and the ground voltage of the chip stage using a signal testing unit. Therefore, in some embodiments, obtaining the ground voltage of the layer under test using a first metal probe may include:

[0159] When one end of the first metal probe is connected to the ground point on the layer to be tested and the other end of the first metal probe is connected to the first signal test unit, the ground voltage of the layer to be tested is measured by the first signal test unit, and the measured ground voltage of the layer to be tested is provided to the first input terminal of the comparison module.

[0160] Obtaining the ground voltage of the chip stage using a second metal probe can include:

[0161] With one end of the second metal probe connected to the grounding point on the chip stage and the other end of the second metal probe connected to the second signal test unit, the grounding voltage of the chip stage is measured by the second signal test unit, and the measured grounding voltage of the chip stage is provided to the second input terminal of the comparison module.

[0162] It should be noted that the first signal test unit can be connected between the first metal probe and the first input terminal of the comparison module, and is used to measure the ground voltage of the test layer of the chip under test through the first metal probe; the second signal test unit can be connected between the second metal probe and the second input terminal of the comparison module, and is used to measure the ground voltage of the test layer of the chip stage through the second metal probe.

[0163] After measuring the ground voltage of the test layer of the chip under test and the ground voltage of the test layer of the chip platform, the first signal test unit and the second signal test unit can display the specific voltage values ​​on a display screen.

[0164] Based on the measured ground voltage of the layer under test and the ground voltage of the chip stage, the ground resistance value is determined, and the resistance value of the adjustable resistor module is adjusted to match the ground resistance value. In this way, by adjusting the resistance value of the adjustable resistor module, the ground resistance of the layer under test of the chip can be dynamically adjusted, resulting in better images during EBAC testing.

[0165] In some embodiments, determining the grounding resistance value based on the grounding voltage of the layer to be tested and the grounding voltage of the chip stage may include:

[0166] Perform differential calculations between the ground voltage of the layer to be tested and the ground voltage of the chip platform to determine the voltage difference;

[0167] Based on the preset correspondence between voltage difference and grounding resistance, the grounding resistance corresponding to the voltage difference is determined.

[0168] It should be noted that the voltage difference is obtained by subtracting the ground voltage of the chip stage from the ground voltage of the layer to be tested, and the ground resistance value corresponding to the voltage difference is determined from the preset correspondence between the voltage difference and the ground resistance value.

[0169] In some embodiments, based on a preset correspondence between voltage difference and grounding resistance, the method may further include:

[0170] If the voltage difference increases, then the grounding resistance must decrease.

[0171] If the voltage difference decreases, it indicates that the grounding resistance has increased.

[0172] It should be noted that there can be a positive correlation between the voltage difference and the grounding resistance. The specific correspondence can be shown in Table 1 above. Each voltage difference corresponds to a grounding resistance value, and the resistance value of the adjustable resistor module can be adjusted accordingly.

[0173] The correspondence can be obtained experimentally, using the voltage difference and grounding resistance recorded when the imaging effect is optimal. Specifically, in determining the preset relationship, this embodiment can provide multiple sample chips, determine the voltage difference and corresponding grounding resistance of each sample chip, and finally determine the preset correspondence between the voltage difference and grounding resistance, resulting in the correspondence shown in Table 1.

[0174] Taking any sample chip as an example, the test equipment provided in this embodiment of the present disclosure is used to perform failure analysis on the sample chip according to the normal failure analysis process. Here, it is assumed that the components of the test equipment are already connected. The sample chip is placed on the chip stage. The ground point of the layer to be tested on the sample chip is connected to one end of the first metal probe, and the second metal probe is connected to the ground point of the chip stage. The first test point in the layer to be tested is connected to the third metal probe, and the second test point in the layer to be tested is connected to the fourth metal probe. The third and fourth metal probes provide driving current to the layer to be tested, and the resistance value of the adjustable resistor module is changed. The adjustment method can be to rotate the resistance adjustment knob on the test equipment. At this time, EBAC images under different resistance values ​​can be observed. When the imaging effect is optimal, that is, when the failure point can be clearly observed from the EBAC image, the corresponding resistance value is determined as the ground resistance value. The difference between the ground voltage of the layer to be tested on the sample chip and the ground voltage of the chip stage is the voltage difference value, thus obtaining a set of corresponding voltage difference values ​​and ground resistance values.

[0175] Each sample chip is tested and analyzed in the same manner, resulting in multiple sets of corresponding voltage difference and grounding resistance values. It's possible that multiple sample chips correspond to the same voltage difference, but their corresponding grounding resistance values ​​differ within an error range, or both the voltage difference and grounding resistance values ​​differ within an error range. In such cases, the average values ​​of multiple voltage differences and / or multiple grounding resistance values ​​are calculated separately, and the resulting average value is used to determine a pair of voltage difference and grounding resistance values. Additionally, due to operational errors or other reasons, some data may deviate significantly from the error range; these data are discarded. This establishes a preset correspondence between voltage difference and grounding resistance values. Therefore, after measuring the voltage difference, the corresponding grounding resistance value can be determined based on this correspondence, allowing adjustment of the resistance value of the adjustable resistor module to improve imaging results.

[0176] Furthermore, the comparison module can specifically perform differential noise reduction on the ground voltage of the layer under test and the ground voltage of the chip stage. Several metal layers and dielectric layers exist between the layer under test and the upper surface of the chip stage. These metal and dielectric layers generate interference signals, affecting the imaging effect of EBAC. This embodiment utilizes the comparison module to perform differential comparison between the ground voltage of the layer under test and the ground voltage of the chip stage to achieve noise reduction. This reduces the interference signals generated by the metal and dielectric layers between the layer under test and the chip stage, improves the imaging effect of EBAC, and facilitates failure analysis of the chip under test, enabling rapid location of failure points.

[0177] In some embodiments, providing a drive current to the layer under test of the chip under test may include:

[0178] The driving current is provided to the layer under test through the third and fourth metal probes;

[0179] One end of the third metal probe is connected to the first test point of the layer to be tested, and the other end of the third metal probe is connected to the current source; one end of the fourth metal probe is connected to the second test point of the layer to be tested, and the other end of the fourth metal probe is grounded.

[0180] It should be noted that the area between the first and second test points constitutes the circuit under test within the layer of the chip under test. The closer the first and second test points are to the failure point, the easier it is to locate the failure point. One end of the third metal probe is connected to the first test point, and the other end can be connected to a current source. One end of the fourth metal probe is connected to the second test point, and the other end can be connected to ground. This allows a driving current to be provided through the current source and introduced into the chip under test via the third and fourth metal probes.

[0181] With the driving current applied, an EBAC image (i.e., an analysis image) of the layer under test is acquired. The EBAC image of the layer under test can be acquired by means of any suitable microscope or other methods.

[0182] S305. Based on the image analysis, determine whether there are any failure points in the layer to be tested.

[0183] It should be noted that after acquiring the analysis image, the presence of failure points in the layer under test is determined from the analysis image. If the layer under test has no failure points, the analysis image is relatively uniform overall. If failure points exist, the image of the failure point will be significantly different from other parts of the image, thus allowing for the location of the failure point. The analysis image can be referenced... Figure 3As shown. The failure point may include a high-resistance failure point and / or a micro-leakage failure point, thereby enabling the rapid and accurate location of failure points that are difficult to locate, such as high-resistance or micro-leakage failure points, based on the method provided in this disclosure.

[0184] It should also be noted that if there is no failure point in the layer under test, it means that the failure point may exist in other metal layers. In this case, the layer under test that has already been tested can be removed to expose a new metal layer as the layer under test, and the failure analysis can be carried out again using this method to determine the failure point.

[0185] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0186] This disclosure integrates a window comparator and a variable resistor onto a nanoprobe testing platform, particularly for the precise positioning of high-resistivity, micro-leakage circuits under EBAC functionality. Utilizing the differential noise reduction function of the window comparator, noise generated by the metal and insulating layers between the ground terminal of the tested layer and the upper surface of the chip platform can be effectively removed, significantly improving the signal-to-noise ratio of high-resistivity, micro-leakage signals under EBAC. The adjustable resistance function of the variable resistor allows for dynamic adjustment of the grounding resistance from the tested layer to the ground terminal, resulting in a better EBAC profile. Furthermore, dynamically adjusting the grounding resistance reduces the risk of trial and error when the probe reaches the sample surface, preventing tip discharge from damaging the probe or sample.

[0187] This disclosure provides a failure analysis method applied to the test equipment described in the foregoing embodiments. The method includes: providing a chip under test (TBD); placing the TBD on the upper surface of a chip stage; providing a drive current to the TBD layer; acquiring an analysis image of the TBD layer under the drive current; and determining whether a failure point exists in the TBD layer based on the analysis image. This method not only reduces signal interference between the TBD layer and the chip stage, but also reduces surface charging effects by dynamically adjusting the grounding resistance of the TBD layer, effectively avoiding the risk of probe tip discharge damaging the probe or the TBD chip. Furthermore, it improves the imaging effect of EBAC, facilitating rapid and accurate location of failure points in the TBD layer and improving the efficiency of failure analysis.

[0188] In another embodiment of this disclosure, see Figure 9 This illustrates a schematic diagram of the composition of a test system 40 provided in an embodiment of this disclosure. For example... Figure 9 As shown, the test system 40 includes a chip under test 20 and a test device 10 as described in any of the foregoing embodiments; wherein the test device 10 is used to perform failure analysis on the chip under test 20.

[0189] In this embodiment of the disclosure, since the test system 40 includes the test equipment 10 described in the foregoing embodiments, it can now shorten the debugging time, quickly locate high resistance and micro-leakage defects, and improve efficiency when performing failure analysis on the chip under test 20.

[0190] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0191] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0192] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0193] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0194] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0195] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0196] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A testing device, characterized in that, The testing equipment includes a chip stage and a support base for supporting the chip stage, and the support base houses a comparison module and an adjustable resistor module; wherein: The chip carrier is used to support the chip under test; The comparison module, connected to the adjustable resistor module, is used to compare the ground voltage of the test layer in the chip under test with the ground voltage of the chip stage. Based on the comparison result and the adjustable resistor module, the ground resistance of the test layer is adjusted to reduce the surface charge effect of the test layer.

2. The testing equipment according to claim 1, characterized in that, The support base is also provided with a first metal probe and a second metal probe; wherein: One end of the first metal probe is connected to the first input terminal of the comparison module, and the other end of the first metal probe is connected to the grounding point on the layer to be tested, for obtaining the grounding voltage of the layer to be tested. One end of the second metal probe is connected to the second input terminal of the comparison module, and the other end of the second metal probe is connected to the grounding point on the chip stage to obtain the grounding voltage of the chip stage.

3. The testing equipment according to claim 2, characterized in that, The first metal probe and the second metal probe each independently include nanoprobes.

4. The testing equipment according to claim 2, characterized in that, The support base is also provided with a first signal testing unit and a second signal testing unit; wherein: The first signal testing unit is used to measure the ground voltage of the layer under test through the first metal probe, and to provide the measured ground voltage of the layer under test to the first input terminal of the comparison module; The second signal testing unit is used to measure the ground voltage of the chip stage through the second metal probe, and to provide the measured ground voltage of the chip stage to the second input terminal of the comparison module; The first signal testing unit is connected between one end of the first metal probe and the first input terminal of the comparison module, and the second signal testing unit is connected between one end of the second metal probe and the second input terminal of the comparison module.

5. The testing equipment according to claim 4, characterized in that, The adjustable resistor module is used to adjust the resistance value corresponding to the voltage difference between the ground voltage of the layer to be tested and the ground voltage of the chip stage after determining the voltage difference.

6. The testing equipment according to claim 5, characterized in that, The voltage difference and the grounding resistance have a corresponding relationship; wherein: If the voltage difference increases, the grounding resistance decreases; If the voltage difference decreases, the grounding resistance increases.

7. The testing equipment according to claim 1, characterized in that, The chip under test includes at least one metal layer and at least one dielectric layer, wherein the at least one metal layer includes the layer to be tested; wherein: The comparison module is further configured to perform a differential comparison based on the ground voltage of the layer under test and the ground voltage of the chip stage, so as to reduce the interference signal generated by the metal layer and dielectric layer contained between the layer under test and the chip stage in the chip under test.

8. The testing equipment according to any one of claims 1 to 7, characterized in that, The comparison module includes a first operational amplifier, a second operational amplifier, a first transistor, a second transistor, a first resistor, a second resistor, and a third transistor; the adjustable resistor module includes an adjustable resistor; wherein: The negative input terminal of the first operational amplifier is connected to the ground point on the layer under test, the positive input terminal of the second operational amplifier is connected to the ground point on the chip stage, and the positive input terminal of the first operational amplifier is connected to the negative input terminal of the second operational amplifier. The output terminal of the first operational amplifier is connected to the input terminal of the first transistor, and the output terminal of the second operational amplifier is connected to the input terminal of the second transistor. The output terminal of the first transistor is connected to the output terminal of the second transistor, and is also connected to the first terminal of the first resistor; The first end of the second resistor is connected to the input terminal of the third transistor, and the second end of the first resistor, the second end of the second resistor, and the output terminal of the third transistor are all connected to the output terminal of the comparator module. The output terminal of the comparison module is connected to the input terminal of the adjustable resistor, the input terminal of the adjustable resistor is also connected to the adjustment terminal of the adjustable resistor, and the output terminal of the adjustable resistor is grounded.

9. The testing equipment according to claim 8, characterized in that, The first transistor, the second transistor, and the third transistor are all diodes, and the third transistor is a Zener diode.

10. The testing equipment according to claim 1, characterized in that, The support base is also provided with a third metal probe and a fourth metal probe; wherein: In the layer to be tested, the third metal probe is connected to the first test point of the layer to be tested, and the fourth metal probe is connected to the second test point of the layer to be tested, for measuring whether there is a failure point between the first test point and the second test point.

11. A failure analysis method, characterized in that, Applied to the test apparatus as described in any one of claims 1 to 10, the method comprises: Provide the chip under test; The chip under test is placed on the upper surface of the chip stage; Provide driving current to the layer under test in the chip under test; Obtain the analysis image of the layer under test under the driving current; Based on the analyzed image, determine whether there are any failure points in the layer to be tested.

12. The method according to claim 11, characterized in that, Before providing drive current to the layer under test in the chip under test, the method further includes: The ground voltage of the layer under test is obtained by the first metal probe, and the ground voltage of the chip stage is obtained by the second metal probe. The grounding resistance value is determined based on the grounding voltage of the layer to be tested and the grounding voltage of the chip stage. The resistance value of the adjustable resistor module is adjusted so that the adjusted resistance value is equal to the grounding resistance value; Wherein, one end of the first metal probe is connected to the first input terminal of the comparison module, and the other end of the first metal probe is connected to the ground point on the layer to be tested; one end of the second metal probe is connected to the second input terminal of the comparison module, and the other end of the second metal probe is connected to the ground point on the chip stage.

13. The method according to claim 12, characterized in that, The step of obtaining the ground voltage of the layer under test through the first metal probe includes: With one end of the first metal probe connected to the ground point on the layer to be tested and the other end of the first metal probe connected to the first signal testing unit, the ground voltage of the layer to be tested is measured by the first signal testing unit, and the measured ground voltage of the layer to be tested is provided to the first input terminal of the comparison module. The step of obtaining the ground voltage of the chip stage through the second metal probe includes: With one end of the second metal probe connected to a ground point on the chip stage and the other end of the second metal probe connected to a second signal testing unit, the ground voltage of the chip stage is measured by the second signal testing unit, and the measured ground voltage of the chip stage is provided to the second input terminal of the comparison module.

14. The method according to claim 12, characterized in that, The step of determining the grounding resistance value based on the grounding voltage of the layer under test and the grounding voltage of the chip platform includes: Perform differential calculation on the ground voltage of the layer under test and the ground voltage of the chip stage to determine the voltage difference; Based on the preset correspondence between voltage difference and grounding resistance, the grounding resistance corresponding to the voltage difference is determined.

15. The method according to claim 14, characterized in that, Based on the preset correspondence between the voltage difference and the grounding resistance, the method further includes: If the voltage difference increases, then the grounding resistance value is determined to decrease; If the voltage difference decreases, then the grounding resistance value is determined to have increased.

16. The method according to claim 11, characterized in that, Providing drive current to the test layer of the chip under test includes: The driving current is provided to the layer under test through the third and fourth metal probes; Wherein, one end of the third metal probe is connected to the first test point of the layer to be tested, and the other end of the third metal probe is connected to a current source; one end of the fourth metal probe is connected to the second test point of the layer to be tested, and the other end of the fourth metal probe is grounded.

17. The method according to claim 11, characterized in that, The provided chip under test includes: Obtain the chip under test; The chip under test is preprocessed to expose the layer to be tested.

18. The method according to claim 11, characterized in that, The failure points include high-resistance failure points and / or micro-leakage failure points.

19. A testing system, characterized in that, It includes the chip under test and the test equipment as described in any one of claims 1 to 10; wherein the test equipment is used to perform failure analysis on the chip under test.

Images