Data read / write control methods, control devices, computer storage media, and electronic equipment

Abstract

This application discloses a data read / write control method, control device, computer storage medium, and electronic device, relating to the field of data processing. The caching device of this application simultaneously receives both a read instruction and a write instruction, and the read address of the read instruction and the write address of the write instruction are the same. In this case, the input data of the write instruction is directly transmitted to the initiator of the read instruction without passing through the caching device. Since the input data to be written is not cached in the caching device, data caching operations are unnecessary, thereby improving data transmission efficiency and reducing data transmission latency.

Description

Technical Field

[0001] This application relates to the field of data processing, and in particular to a data read / write control method, control device, computer storage medium, and electronic device. Background Technology

[0002] With the development of integrated circuit technology, the requirements for chip area, power consumption, and performance are becoming increasingly stringent. To improve the data exchange speed between two devices, a buffer device is placed between them, and the performance of the buffer device has a significant impact on the chip. In related technologies, read and write operations of the buffer device are generally performed independently; that is, input data is written to the buffer device based on a read operation. How to improve the data read and write efficiency of the buffer device is a problem that urgently needs to be solved. Summary of the Invention

[0003] This application provides a data read / write control method, control device, computer storage medium, and electronic device, which can improve data read / write efficiency when performing read and write operations on the same address simultaneously. The technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a data read / write control method, including:

[0005] If both a read instruction and a write instruction are received simultaneously, the write address of the write instruction and the read address of the read instruction are obtained; wherein, a buffer device is provided between the initiator of the write instruction and the initiator of the read instruction;

[0006] Compare whether the read address and the write address are the same;

[0007] If so, the input data indicated by the write instruction is directly transmitted to the initiator of the read instruction, so that the data to be written is not cached in the cache device.

[0008] Secondly, embodiments of this application provide a control device, including: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed by the method of this application.

[0009] Thirdly, this application provides a control device, including: a first AND gate, a second AND gate, a comparator, and a multiplexer;

[0010] In this configuration, the first input of the first AND gate is connected to the read enable terminal of the cache device, the second input of the first AND gate is connected to the write enable terminal of the cache device, and the output of the first AND gate is connected to the first input of the second AND gate; the first input of the comparator is connected to the write address terminal of the cache device, the second input of the comparator is connected to the read address terminal of the cache device, the output of the comparator is connected to the second input of the second AND gate, the output of the second AND gate is connected to the enable terminal of the multiplexer, the first input of the multiplexer is connected to the data input terminal of the cache device, the second input of the multiplexer is connected to the data output terminal of the cache device, and the output of the multiplexer is connected to the initiator of the read instruction.

[0011] Fourthly, embodiments of this application provide a computer storage medium storing a plurality of instructions adapted for loading by a processor and executing the above-described method steps.

[0012] Fifthly, embodiments of this application provide an electronic device that may include a control device and a cache device, wherein the cache device may be a synchronous FIFO memory.

[0013] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:

[0014] When both read and write commands are received simultaneously, and the read address and write address of the read command are the same, the input data of the write command is directly transmitted to the initiator of the read command without passing through the buffer device. Since the input data to be written is not buffered in the buffer device, data caching is not required, thereby improving data transmission efficiency and reducing data transmission latency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the system architecture provided in the embodiments of this application;

[0017] Figure 2 This is a flowchart illustrating the data read / write control method provided in an embodiment of this application;

[0018] Figure 3 This is a schematic diagram showing the connection between the control device and the buffer device provided in the embodiments of this application;

[0019] Figure 4 This is a schematic diagram of the structure of a control device provided in an embodiment of this application;

[0020] Figure 5 This is another structural schematic diagram of a control device provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0022] Figure 1 An exemplary system architecture that can be applied to the data read / write control method of this application is shown.

[0023] like Figure 1 As shown, the system architecture may include: a first device, a cache device, a control device, and a second device. The first device is connected to the cache device, the cache device is connected to the second device, and the control device is connected to the cache device, the first device, and the second device. The first device is the initiator of write instructions (referred to as the writer), and the second device is the initiator of read instructions (referred to as the reader). The first device writes data to the cache device, and the second device reads data from the cache device. The cache device provides storage space for data and can be a synchronous FIFO (first input first output) memory. The control device is used to perform read operations in response to read instructions or write operations in response to write instructions.

[0024] The following will be combined with the appendix Figure 2 This application provides a detailed description of the data read / write control method provided in its embodiments. The execution entity of these embodiments is... Figure 1 The control device shown.

[0025] Please see Figure 2 This is a flowchart illustrating a data read / write control method provided in an embodiment of this application. Figure 2 As shown, the method described in this application embodiment may include the following steps:

[0026] S201. If both read and write instructions are received simultaneously, obtain the write address of the write instruction and the read address of the read instruction.

[0027] A buffer device is provided between the initiator of the write instruction and the initiator of the read instruction. The control device of this application is connected to the initiator of the read instruction (hereinafter referred to as the reader), the initiator of the write instruction (hereinafter referred to as the writer), and the buffer device. The write instruction is used to perform a write operation in the buffer device, and the read instruction is used to perform a read operation in the buffer device. If the control device receives a read instruction from the reader and a write instruction from the writer simultaneously (meaning simultaneously in the same clock cycle), it obtains the write address of the write instruction and the read address of the read instruction. The write address represents the address where input data is written in the buffer device, and the read address represents the address where output data is read in the buffer device.

[0028] In one or more possible embodiments, the cache device is provided with a read enable terminal, a write enable terminal, a read address terminal, a write address terminal, a data input terminal, and a data output terminal. The read enable terminal is used to input a read instruction, the write enable terminal is used to input a read instruction, the read address terminal is used to input a read address, the write address terminal is used to input a write address, the data input terminal is used to write data to the cache device, and the data output terminal is used to read data from the cache device. The writer performs a write operation using the write enable terminal, the write address terminal, and the data input terminal, while the reader performs a read operation using the read enable terminal, the read address terminal, and the data output terminal. The control device detects the level signals on the write enable terminal and the read enable terminal. When a high level signal is detected on both the read enable terminal and the write enable terminal within the same clock cycle, it determines that a read instruction and a write instruction have been received simultaneously. Then, it obtains the read address at the read address terminal and the write address at the write address terminal.

[0029] S202. Compare whether the read address and write address are the same.

[0030] The read address and write address are generally composed of a specific number of bits. The read address and write address are compared to see if all bits are the same. If they are the same, it means that the read address and write address are the same, and then the same address in the cache device needs to be read and written. If they are not the same, it means that the read address and write address are different.

[0031] S203. If so, the input data indicated by the write instruction will be directly transmitted to the initiator of the read instruction.

[0032] The input data indicated by the write instruction represents the data to be written to the cache device. The input data indicated by the write instruction is directly used as the output data of the read instruction, without going through the cache device, and is directly transmitted to the initiator of the read instruction (i.e., the reader), saving the caching step, improving the data transmission speed, and reducing the data transmission latency.

[0033] Furthermore, the step of directly transmitting the input data indicated by the write instruction to the initiator of the read instruction includes:

[0034] A data bypass is formed by connecting the data input and data output terminals of the cache device, and the input data indicated by the write instruction is transmitted to the initiator of the read instruction through the data bypass.

[0035] For example: see Figure 2 The diagram shows the structure of the control device and the buffer device. The buffer device has a data input terminal wdata, a write enable terminal wr_en, a write address terminal wr_ptr, a data output terminal rdata, a read enable terminal rd_en, and a read address terminal rd_ptr. The control device is connected to these six ports. When the control device simultaneously detects that the level signals on both the write enable terminal wr_en and the read enable terminal rd_en are high, it obtains the first address through the write address terminal wr_ptr, removes the most significant bit of the first address to obtain the read address, and obtains the second address through the read address terminal rd_ptr, removes the most significant bit of the second address to obtain the write address. It compares the read address and the write address. If they are the same, the control device connects the data input terminal wdata and the data output terminal rdata to obtain a data bypass, and outputs the input data to be written to the initiator of the read command through this data bypass.

[0036] Furthermore, in addition to simultaneously receiving read and write instructions, and ensuring that the read address of the read instruction and the write address of the write instruction are the same, this application also requires that the buffer device be empty. That is, after satisfying the above three conditions, the input data of the write instruction is directly transmitted to the initiator of the read instruction without passing through the buffer device.

[0037] The method for determining that the cache device is empty in this embodiment of the application includes:

[0038] Obtain the read address through the read address terminal of the cache device;

[0039] Obtain the write address through the write address terminal of the cache device;

[0040] Compare whether the highest bit and the remaining bits of the read address and the write address are the same; the read address and the write address are composed of the highest bit and the remaining bits. For example, the read address is composed of 8 bits, with the highest bit being the 1st bit and the remaining bits being the 2nd to 8th bits.

[0041] If yes, the cache device is determined to be empty; if the highest bit of the read address and the write address are different but the remaining bits are the same, the cache device is determined to be full; if the highest bit of the read address and the write address are different and the remaining bits are also different, the cache device is neither empty nor full.

[0042] In this embodiment of the application, the method for determining that the cache device is empty further includes:

[0043] A counter is used to count the number of used storage units in the cache device. The cache device consists of multiple storage units of equal size, which are the basic storage units, and each storage unit is used to store data. When data is written, one or more storage units in the cache device are used; when data is read, one or more storage units in the cache device are released. When the counter counts the number of storage units in the idle state and it equals the maximum number, the cache device is determined to be in an empty state.

[0044] Furthermore, the method of this application also includes:

[0045] If a write instruction and a read instruction are not received simultaneously, or the read address of the read instruction and the write address of the write instruction are different, or the buffer device is full, the input data from the initiator of the write instruction is obtained, and then the input data is written into the buffer device according to the write address. The output data is read from the buffer device according to the read address, and the output data is transmitted to the initiator of the read instruction.

[0046] The control device in this application is used in conjunction with a buffer device to control the transmission of input data. When a read instruction and a write instruction are received simultaneously, and the read address of the read instruction and the write address of the write instruction are the same, the input data of the write instruction is directly transmitted to the initiator of the read instruction without passing through the buffer device. Since the input data to be written is not buffered in the buffer device, data caching is not required, thereby improving data transmission efficiency.

[0047] See Figure 4 This is a schematic diagram of the control device of this application. The control device of this application is implemented by pure hardware and includes: a first AND gate, a second AND gate, a comparator and a multiplexer.

[0048] The connections of the aforementioned components are as follows: The buffer device has a data input terminal wdata, a write enable terminal wr_en, a write address terminal wr_ptr, a data output terminal rdata, a read enable terminal rd_en, and a read address terminal rd_ptr. The first input of the first AND gate is connected to the read enable terminal rd_en, the second input of the first AND gate is connected to the write enable terminal wr_en, and the output of the first AND gate is connected to the first input of the second AND gate. The first input of the comparator is connected to the write address terminal wr_ptr, the second input of the comparator is connected to the read address terminal rd_ptr, the output of the comparator is connected to the second input of the second AND gate, and the output of the second AND gate is connected to the enable terminal of the multiplexer. The first input of the multiplexer is connected to the data input terminal wdata, and the second input of the multiplexer is connected to the output terminal rdata.

[0049] Furthermore, the control device of this application also includes a NOT gate, the input of which is connected to the empty / full terminal of the buffer device, and the output of which is connected to the third input of the second AND gate.

[0050] The control device of this application operates as follows: When the writer performs a write operation, a high-level signal is sent through the write enable terminal wr_en; when the reader performs a read operation, a high-level signal is sent through the read enable terminal wr_en. When the first AND gate detects high-level signals simultaneously at its first and second input terminals, the output terminal of the first AND gate outputs a high-level signal. The comparator obtains the write address through its first input terminal and the read address through its second input terminal, compares whether the write address and read address are the same, and if they are the same, the comparator outputs a high-level signal; otherwise, it outputs a high-level signal. When the buffer is empty, the empty / full terminal outputs a low-level signal, and the NOT gate converts the low-level signal to a high-level signal, outputting it to the third input terminal of the second AND gate; conversely, when the buffer is full, the NOT gate outputs a low-level signal. When the first, second, and third input terminals of the second AND gate simultaneously receive high-level signals, the output terminal of the second AND gate outputs a high-level signal. When the multiplexer detects a high-level signal at the enable terminal, the input data on the data input terminal wdata is directly transmitted to the reader (i.e., the initiator of the read command) through the output terminal of the multiplexer; when the multiplexer detects a low-level signal at the enable terminal, the input data on the data input terminal wdata is written into the buffer for buffering, and then output to the reader through the data output terminal rdata.

[0051] This application also provides a computer storage medium that can store multiple instructions, which are adapted to be loaded and executed by a processor as described above. Figure 2 The method steps of the illustrated embodiment can be found in the following documentation for detailed execution. Figure 2 The specific details of the illustrated embodiments will not be elaborated here.

[0052] This application also provides a computer program product that stores at least one instruction, which is loaded and executed by the processor to implement the data read / write control method described in the above embodiments.

[0053] Please see Figure 5 The diagram below provides a structural schematic of a control device according to an embodiment of this application. Figure 5 As shown, the control device 500 includes at least one processor 501, at least one communication interface 504, a memory 503, and at least one communication bus 502.

[0054] The communication bus 502 is used to enable communication between these components.

[0055] The communication interface 504 is used to communicate with external devices, and the communication method can be wired or wireless communication.

[0056] The processor 501 may include one or more processing cores. The processor 501 connects to various parts within the control device 500 using various interfaces and lines. It executes various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 503, and by calling data stored in the memory 503. Optionally, the processor 501 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 501 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content to be displayed on the screen; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip without being integrated into the processor 501.

[0057] The memory 503 may include random access memory (RAM) or read-only memory. Optionally, the memory 503 may include a non-transitory computer-readable storage medium. The memory 503 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 503 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 503 may also be at least one storage device located remotely from the aforementioned processor 501. Figure 5 As shown, the memory 503, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and application programs.

[0058] exist Figure 5 In the control device 500 shown, the processor 501 can be used to call the application program stored in the memory 503 and specifically execute, such as Figure 2 The method shown can be referred to for details. Figure 2 As shown, it will not be elaborated further here.

[0059] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory, or random access memory, etc.

[0060] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A data read / write control method, characterized in that, include: Detect the level signals of the read enable and write enable pins of the cache device; If both the read enable terminal and the write enable terminal are high, then it is determined that both read and write commands are received simultaneously. A buffer device is provided between the initiator of the write instruction and the initiator of the read instruction; Obtain the read address from the read address end of the cache device, and obtain the write address from the write address end of the cache device; Compare whether the read address and the write address are the same; If so, when the cache device is determined to be empty, the input data indicated by the write instruction is directly transmitted to the initiator of the read instruction, so that the input data is not cached in the cache device; Determining that the cache device is empty includes: the cache device includes multiple storage units, and if the number of storage units in the cache device that are in an idle state is equal to the maximum number, then the cache device is determined to be empty.

2. The method according to claim 1, characterized in that, The step of directly transmitting the input data indicated by the write command to the initiator of the read command includes: The data input and data output terminals of the cache device are connected to form a data bypass; The input data indicated by the write instruction is transmitted to the initiator of the read instruction via the data bypass.

3. A control device, characterized in that, include: A processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed the method steps as claimed in any one of claims 1 to 2.

4. A control device, characterized in that, include: The system comprises a first AND gate, a second AND gate, a NOT gate, a comparator, and a multiplexer; wherein, the first input of the first AND gate is connected to the read enable terminal of the cache device, the second input of the first AND gate is connected to the write enable terminal of the cache device, and the output of the first AND gate is connected to the first input of the second AND gate; the first input of the comparator is connected to the write address terminal of the cache device, the second input of the comparator is connected to the read address terminal of the cache device, the output of the comparator is connected to the second input of the second AND gate, the output of the second AND gate is connected to the enable terminal of the multiplexer, the first input of the multiplexer is connected to the data input terminal of the cache device, the second input of the multiplexer is connected to the data output terminal of the cache device, and the output of the multiplexer is connected to the initiator of the read instruction; the input of the NOT gate is connected to the empty / full terminal of the cache device, and the output of the NOT gate is connected to the third input of the second AND gate.

5. A computer storage medium, characterized in that, The computer storage medium stores a plurality of instructions, which are adapted to be loaded by a processor and executed as the method steps of any one of claims 1 to 2.

6. An electronic device, characterized in that, include: The buffer device and the control device as described in any one of claims 3 to 4.

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