Electronic product analysis method and device, computer device and storage medium
By performing simulation analysis and constructing fault propagation models for electronic products, collaborative modeling of reliability and testability is achieved, solving the problem of model mismatch in existing technologies and improving the efficiency and accuracy of design analysis.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA ELECTRONICS RELIABILITY AND ENVIRONMENTAL TESTING INSTITUTE ((THE FIFTH INSTITUTE OF ELECTRONICS MINISTRY OF INDUSTRY AND INFORMATION TECHNOLOGY) (CHINA SAIBAO LABORATORY)
- Filing Date
- 2022-07-15
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies, product reliability and testability modeling are conducted separately, resulting in different model formats and mismatched parameters, which affects the efficiency of design analysis and the accuracy of results.
By performing simulation analysis on electronic products, a fault propagation model is constructed, fault impact analysis and fault tree analysis are conducted, a correlation matrix is established, and collaborative modeling of reliability and testability is achieved.
It improves the reliability and testability of electronic products, enhances the efficiency and accuracy of design analysis results, and avoids inconsistencies caused by differences in the capabilities and depth of designers.
Smart Images
Figure CN115238488B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of testing technology, and in particular to an electronic product analysis method, apparatus, computer equipment, and storage medium. Background Technology
[0002] With the innovation and rapid development of equipment technology and information technology, products are also developing rapidly towards integration, informatization and intelligence, which puts forward increasingly higher requirements for product reliability and testability.
[0003] In existing technologies, reliability modeling and testability modeling of products are separate. Due to the different starting points of reliability and testability development and the different levels of importance they have received, designers' ability to conduct product reliability and testability modeling, the depth of analysis, and the level of detail in their work vary greatly. This leads to problems such as different forms of reliability models and testability models, mismatch of the same parameters in different models, and inconsistent states, which seriously affect the efficiency and accuracy of product reliability and testability design analysis results. Summary of the Invention
[0004] Therefore, it is necessary to provide an electronic product analysis method, apparatus, computer equipment, and storage medium that can efficiently perform collaborative modeling of product reliability and testability, thereby improving the efficiency and accuracy of product reliability and testability design analysis results, in response to the aforementioned technical problems.
[0005] Firstly, this application provides a method for analyzing electronic products. The method includes:
[0006] The electronic product is simulated and analyzed to obtain its fault information and the fault levels at each stage.
[0007] A fault propagation model is constructed based on the fault information and each of the aforementioned levels;
[0008] Based on the fault propagation model, fault impact analysis and fault tree analysis are performed on the electronic product to obtain the reliability analysis results of the electronic product.
[0009] Based on the fault transmission model, a correlation matrix is constructed, and the testability analysis results of the electronic product are obtained based on the correlation matrix.
[0010] In one embodiment, the simulation analysis of the electronic product to obtain fault information and various levels of the electronic product includes:
[0011] Determine the load profile of the electronic product based on the task profile of the electronic product;
[0012] Determine the functions of each level of the electronic product and each node in each level, and construct a digital prototype model of the electronic product;
[0013] Based on the digital prototype model, a stress simulation model of the electronic product is established, and the load profile is applied to the stress simulation model to obtain the stress profile and key failure points of the electronic product under the load profile.
[0014] Based on the key failure locations and actual failure data, the potential failure mechanism analysis results for each node of the electronic product are determined, wherein the potential failure mechanism analysis results include potential failure modes, potential failure mechanisms, and failure physical models;
[0015] Based on the analysis results of the potential fault mechanisms and the functional structure of the electronic product, the fault detection methods corresponding to different potential fault mechanisms are determined, and the fault propagation path is analyzed.
[0016] Based on the fault physics model corresponding to the different potential fault mechanisms of each node of the electronic product, the pre-fault time of the potential fault mechanism of each node under the stress profile is determined.
[0017] Based on the model parameters of the fault physical model of each node of the electronic product, the fault physical model parameter matrix is determined, and based on the fault physical model parameter matrix, the fault physical model, the stress sequence in the stress profile and the duration of different stress values, the large sample pre-fault time of each node is determined.
[0018] Based on the large sample time before failure of each node, determine the failure probability of each node.
[0019] The fault information includes the potential fault mode, potential fault mechanism, fault physical model, fault detection method, fault propagation path and fault probability.
[0020] In one embodiment, constructing the fault propagation model based on the fault information and each of the levels includes:
[0021] Construct a hierarchical diagram of the electronic product according to each of the aforementioned levels, and establish the functional relationship between each node and the corresponding node.
[0022] Establish the correlation between each node and its corresponding potential failure modes, potential failure mechanisms, failure physical models, failure detection methods, failure propagation paths, and failure probabilities;
[0023] Based on the potential failure modes, potential failure mechanisms, failure physical models, failure detection methods, failure propagation paths, failure probabilities, and actual failure information of each node, the failure propagation relationships between each node are determined to complete the construction of the failure propagation model.
[0024] In one embodiment, the step of performing fault impact analysis and fault tree analysis on the electronic product based on the fault propagation model to obtain the reliability analysis results of the electronic product includes:
[0025] Based on the fault information and function of each node in the fault transmission model, the electronic product is subjected to fault impact analysis to obtain tabular fault impact analysis results.
[0026] Based on the failure impact analysis results, analyze the causes and impacts of the critical failures at each node;
[0027] The top event is determined based on the failure probability and severity of each node in the failure impact analysis results. Based on the graphical failure and transmission relationship of the failure transmission model and the logical relationship of the failure transmission model, a fault tree is generated in reverse order modeling.
[0028] The fault tree is subjected to quantitative and qualitative analysis to obtain the reliability analysis results, wherein the reliability analysis results include the minimum cut set of the top event, the probability of occurrence of the top event, the probability importance, the structural importance, and the critical importance.
[0029] In one embodiment, constructing the correlation matrix based on the fault transmission model includes:
[0030] Find the fault modes of each node in the lowest level of each level, and form a fault mode set by the fault modes of the nodes in the lowest level.
[0031] Find all test points in the fault propagation model and combine the tests of all test points into a test set.
[0032] Select the i-th test from the test set in order as the target test, where i is an integer greater than or equal to 1 and less than or equal to the total number of tests in the test set;
[0033] From all the test points, query the target test point to which the target test belongs, and find the output port through the connection between the target test point and the output port;
[0034] Query all the fault modes contained in the output port, draw a fault tree with each fault mode as the top event, and form a fault tree set with each fault tree;
[0035] Select the j-th fault mode from the fault mode set in sequence as the target fault mode, and input the target fault mode into all fault trees in the fault tree set to obtain the value of the element in the j-th row and i-th column of the correlation matrix, where j is an integer greater than or equal to 1 and less than or equal to the total number of all fault modes.
[0036] In one embodiment, the step of sequentially selecting the j-th fault mode from the fault mode set as the target fault mode, and inputting the target fault mode into all fault trees in the fault tree set to obtain the value of the element in the j-th row and i-th column of the correlation matrix includes:
[0037] If the fault impact analysis algorithm determines that the target fault mode is true and the top event occurs, then the value of the element in the j-th row and i-th column of the correlation matrix is determined to be equal to a first preset value, wherein the first preset value is used to characterize the correlation between the target fault mode and the target test.
[0038] In one embodiment, the method further includes:
[0039] If the fault impact analysis algorithm determines that the target fault mode is true and the top event has not occurred, then the value of the element in the j-th row and i-th column of the correlation matrix is determined to be equal to the second preset value, wherein the second preset value is used to characterize that there is no correlation between the target fault mode and the target test.
[0040] Secondly, this application also provides an electronic product analysis device, the device comprising:
[0041] The simulation module is used to perform simulation analysis on the electronic product to obtain the fault information and various levels of the electronic product;
[0042] The model building module is used to build a fault transmission model based on the fault information and each of the levels;
[0043] The first acquisition module is used to perform fault impact analysis and fault tree analysis on the electronic product based on the fault propagation model, so as to obtain the reliability analysis results of the electronic product.
[0044] The second acquisition module is used to construct a correlation matrix based on the fault transmission model, and obtain the testability analysis results of the electronic product based on the correlation matrix.
[0045] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:
[0046] The electronic product is simulated and analyzed to obtain its fault information and the fault levels at each stage.
[0047] A fault propagation model is constructed based on the fault information and each of the aforementioned levels;
[0048] Based on the fault propagation model, fault impact analysis and fault tree analysis are performed on the electronic product to obtain the reliability analysis results of the electronic product.
[0049] Based on the fault transmission model, a correlation matrix is constructed, and the testability analysis results of the electronic product are obtained based on the correlation matrix.
[0050] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:
[0051] The electronic product is simulated and analyzed to obtain its fault information and the fault levels at each stage.
[0052] A fault propagation model is constructed based on the fault information and each of the aforementioned levels;
[0053] Based on the fault propagation model, fault impact analysis and fault tree analysis are performed on the electronic product to obtain the reliability analysis results of the electronic product.
[0054] Based on the fault transmission model, a correlation matrix is constructed, and the testability analysis results of the electronic product are obtained based on the correlation matrix.
[0055] The aforementioned electronic product analysis methods, devices, computer equipment, and storage media perform simulation analysis on electronic products to obtain fault information and its various levels. Then, based on this fault information and levels, a fault propagation model is constructed. Following this model, fault impact analysis and fault tree analysis are performed to obtain reliability analysis results. Furthermore, a correlation matrix is constructed based on the fault propagation model, and the testability analysis results are obtained from the correlation matrix. By using the fault information and the fault propagation model constructed at each level, the reliability and correlation analysis of electronic products can be coordinated. In other words, the fault propagation model is a model jointly constructed based on reliability and testability. This coordinated modeling of reliability and testability of electronic products improves the efficiency and accuracy of design and analysis results for both reliability and testability. Attached Figure Description
[0056] Figure 1 This is one of the flowcharts illustrating the electronic product analysis method provided in the embodiments of this application;
[0057] Figure 2 This is a flowchart illustrating another electronic product analysis method provided in an embodiment of this application;
[0058] Figure 3 This is a flowchart illustrating another electronic product analysis method provided in an embodiment of this application;
[0059] Figure 4 This is a flowchart illustrating another electronic product analysis method provided in an embodiment of this application;
[0060] Figure 5 This is a flowchart illustrating another electronic product analysis method provided in an embodiment of this application;
[0061] Figure 6 This is a structural block diagram of the electronic product analysis device provided in the embodiments of this application;
[0062] Figure 7 This is a diagram of the internal structure of a computer device in one embodiment of this application. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0064] The electronic product analysis method, apparatus, computer equipment, and readable storage medium provided in this application aim to achieve collaborative modeling and analysis of the reliability and testability of electronic products. The technical solutions of this application and how they solve the aforementioned technical problems will be described in detail below through embodiments and in conjunction with the accompanying drawings. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0065] It should be noted that the electronic product analysis method provided in this application can be executed by an electronic product analysis device. This device can be implemented as part or all of a computer device through software, hardware, or a combination of both. The computer device can be a server (or terminal) used for electronic product analysis. In the following method embodiments, the execution entity is a computer device, which is used as an example for explanation. It is understood that the electronic product analysis method provided in the following method embodiments can also be applied to systems including terminals and servers, and implemented through the interaction between the terminal and the server.
[0066] In one embodiment, such as Figure 1 As shown, Figure 1This is one of the flowcharts illustrating the electronic product analysis method provided in this application, including the following steps:
[0067] S101. Perform simulation analysis on electronic products to obtain fault information and various levels of the electronic products.
[0068] Specifically, the electronic products in this embodiment can be large electronic products such as aircraft and ships, or small and medium-sized electronic products such as home appliances or industrial machines. Simulation analysis can overcome the drawbacks of traditional reliability or testability analysis methods that rely too heavily on empirical data. Even when empirical data is difficult to obtain, it can still ensure the accuracy of reliability or testability analysis, providing effective support for the design of reliability or testability models.
[0069] S102. Construct a fault propagation model based on fault information and each level.
[0070] The fault information includes some or all of the following: potential fault modes, potential fault mechanisms, fault physical models, fault detection methods, fault propagation paths, and fault probabilities.
[0071] S103. Based on the fault propagation model, perform fault impact analysis and fault tree analysis on electronic products to obtain the reliability analysis results of electronic products.
[0072] Specifically, both fault impact analysis and fault tree analysis are reliability analyses of electronic products.
[0073] S104. Based on the fault propagation model, construct a correlation matrix and obtain the testability analysis results of electronic products according to the correlation matrix.
[0074] Specifically, reliability characterizes whether a fault exists at a certain test point of an electronic product, while testability characterizes whether a fault can be detected at that test point.
[0075] In this embodiment, the correlation matrix specifically refers to the correlation between the faults at the test points and the tests conducted at the test points.
[0076] The electronic product analysis method provided in this embodiment obtains a fault propagation model by collaboratively modeling the reliability and testability of electronic products. This model enables simultaneous reliability and testability analysis of the electronic product. It avoids the differences in designers' capabilities in product reliability and testability modeling, the depth of analysis, and the level of detail in their work, thus integrating the reliability and testability of electronic products into an organic whole. This significantly improves the efficiency and accuracy of design analysis results for both reliability and testability of electronic products.
[0077] like Figure 2 As shown, Figure 2This is a flowchart illustrating another electronic product analysis method provided in this application embodiment. This embodiment relates to how to perform simulation analysis on electronic products to obtain fault information and an optional approach for each level of the electronic product. Based on the above embodiment, S101 includes the following steps:
[0078] S201. Determine the load profile of the electronic product based on the task profile of the electronic product.
[0079] In this embodiment, the process of determining the load profile of an electronic product based on its task profile involves dividing and describing the electronic product according to its task requirements and status throughout its life cycle, thus obtaining a set of task profiles. Each task profile of the electronic product is then analyzed to determine its corresponding load profile. Specifically, the load types within the load profile are generally divided into environmental loads and operational loads.
[0080] S202. Determine the functions of each level of the electronic product and each node in each level, and construct a digital prototype model of the electronic product.
[0081] The process of determining the levels of an electronic product involves analyzing its functional characteristics, structural parameters, material parameters, and processing parameters. Based on the analysis results, the levels of the electronic product are then determined. It should be noted that in this embodiment, the electronic product is divided into three levels from highest to lowest: system level, module level, and component level. However, this is not limited to three levels; the specific levels can be determined according to the actual situation.
[0082] Specifically, a node refers to different components within the same level. For example, in a computer hierarchy, there are three levels: the first level is the system level, which includes the computer itself. The second level is the module level, which may include the host and the monitor; the host and monitor are two nodes in the module level. The third level can be the component level; for example, the host in the second level includes component A, component B, and component C. After classifying electronic products, each level includes at least one node, and the functions performed by each node can be identified.
[0083] In this embodiment, the digital prototype model includes a two-dimensional digital prototype model and a three-dimensional digital prototype model.
[0084] S203. Establish a stress simulation model of the electronic product based on the digital prototype model, and apply the load profile to the stress simulation model to solve for the stress profile and key failure parts of the electronic product under the load profile.
[0085] Specifically, a stress simulation model is generated by assigning materials, constraints, parameters, forces, and environmental conditions to the digital prototype model. Environmental and operational loads are then applied to the stress simulation model, and the stress profile and key failure points of the equipment under the load profile are obtained. The stress simulation model can include a finite element model or an electrophysical model. The stress profile includes the thermal stress state and vibration stress state of the equipment under the load conditions.
[0086] S204. Based on the key failure locations and actual failure data, determine the potential failure mechanism analysis results for each node of the electronic product. The potential failure mechanism analysis results include potential failure modes, potential failure mechanisms, and failure physical models.
[0087] Specifically, actual fault data includes actual failure analysis results and field or laboratory fault data. In this embodiment, after determining the potential fault mechanism analysis results for each node of the electronic product, the potential fault mechanisms are prioritized, and model parameters such as geometric structural parameters, material property parameters, process parameters, electrical parameters, stress parameters, and model correction factors in commonly used fault physical models are sorted out.
[0088] S205. Based on the analysis results of potential fault mechanisms and the functional structure of electronic products, determine the fault detection methods corresponding to different potential fault mechanisms, and analyze the fault transmission path.
[0089] Specifically, the fault propagation path is used to provide a basis for the construction of the fault propagation model.
[0090] S206. Based on the physical models of different potential failure mechanisms of each node in an electronic product, determine the pre-failure time of the potential failure mechanism of each node under the stress profile.
[0091] Specifically, firstly, based on the failure physics model corresponding to the different potential failure mechanisms of each node in the electronic product, the stress damage of each node under the stress profile is calculated. For overstress failure mechanisms, if the stress level borne by the node of the electronic product exceeds its upper limit, the node is considered to have failed, and the time before failure is 0. If the stress level borne by the electronic product does not exceed its upper limit, subsequent analysis can continue. That is, for wear-type failure mechanisms, the time before failure or the number of cycles before failure can be obtained for each potential failure mechanism of the electronic product node at each stress level based on the failure physics model. The number of cycles before failure can be converted into the time before failure.
[0092] S207. Based on the model parameters of the physical model of each node of the electronic product, determine the physical model parameter matrix of the fault, and based on the physical model parameter matrix of the fault, the physical model of the fault, the stress sequence in the stress profile and the time of action of different stress values, determine the large sample time before failure of each node.
[0093] In this embodiment, Monte Carlo and cumulative damage analysis were mainly used to determine the large-sample pre-failure time of each node. Specifically, the process is as follows: Based on the geometric structural parameters, material property parameters, process parameters, electrical parameters, stress parameters, and model correction factors used in the physical model of each node of the electronic product, and combined with the stress profile, the types of parameters to be sampled in Monte Carlo random sampling are determined, and the physical model parameter matrix is obtained through multiple samplings. The physical model parameter matrix is then substituted into the physical model, and combined with the stress sequence in the stress profile and the duration of different stress values, the damage to each node of the electronic product under different stress values is analyzed. Damage accumulation calculation is then performed to obtain the large-sample pre-failure time of each node of the equipment product.
[0094] S208. Based on the large sample time before failure of each node, determine the failure probability of each node. The failure information includes potential failure modes, potential failure mechanisms, failure physical models, failure detection methods, failure propagation paths, and failure probabilities.
[0095] The hierarchical structure of this embodiment includes three levels: system level, module level, and component level. The specific process for determining the failure probability of each node based on the large sample failure time of each node is as follows:
[0096] By utilizing large sample pre-failure times of each node at each component level of electronic products, and by fusing the failure time distributions of multiple potential failure mechanisms, the failure probability of each node at each component level of electronic products can be obtained.
[0097] By performing multi-point fault distribution fusion on the fault probabilities of each node in each component level within each module level of an electronic product, the fault probabilities of each node in each module level of the electronic product can be obtained.
[0098] By fusing the failure probabilities of each node in each module of an electronic product through multi-point fault distribution, the failure probabilities of the system-level nodes of the electronic product are obtained, i.e., the failure probabilities of the electronic product.
[0099] In one embodiment, such as Figure 3 As shown, Figure 3 This is a flowchart illustrating another electronic product analysis method provided in this application embodiment. This embodiment relates to an optional approach for constructing a fault transmission model based on fault information and various levels. Based on the above embodiment, S102 includes the following steps:
[0100] S301. Construct a hierarchical diagram of the electronic product according to each level, and establish the relationship between the function of each node and the corresponding node.
[0101] Specifically, each level includes multiple nodes, and each node is associated with its corresponding function.
[0102] S302. Establish the correlation between each node and its corresponding node's potential failure modes, potential failure mechanisms, failure physical models, failure detection methods, failure propagation paths, and failure probabilities.
[0103] Specifically, based on the hierarchical diagram of the electronic product and its associated functions, the collected potential failure modes, potential failure mechanisms, failure physical models, failure detection methods, failure propagation paths and failure probabilities are classified according to different product hierarchical objects. The potential failure modes, potential failure mechanisms, failure physical models, failure detection methods, failure propagation paths and failure probabilities occurring at different level nodes are represented graphically in the hierarchical diagram, corresponding to the node hierarchy and function.
[0104] It should be noted that the potential fault modes, potential fault mechanisms, fault physical models, fault detection methods, fault propagation paths, and fault probabilities in this embodiment are all derived from simulation analysis or actual data.
[0105] S303. Based on the potential failure modes, potential failure mechanisms, failure physical models, failure detection methods, failure propagation paths, failure probabilities, and actual failure information of each node, determine the failure propagation relationships between each node to complete the construction of the failure propagation model.
[0106] Specifically, in this embodiment, directed arrows are used to represent the fault propagation relationships between nodes. It should be noted that the nodes at both ends of the arrow can be at the same level or at different levels.
[0107] The electronic product method of this embodiment constructs a fault propagation model that can characterize the logical relationships and fault impact propagation relationships between different levels and between nodes at the same level in complex electronic products. It forms a set of technical methods for characterizing and analyzing the reliability and testability models of products from the fault mechanism of underlying components to the equipment and system level, which can significantly improve the credibility of the reliability and testability design analysis results of electronic products.
[0108] like Figure 4 As shown, Figure 4 This is a flowchart illustrating another electronic product analysis method provided in this application embodiment. This embodiment relates to an optional approach for performing fault impact analysis and fault tree analysis on electronic products based on a fault propagation model to obtain electronic product reliability analysis results. Based on the above embodiment, S103 includes the following steps:
[0109] S401. Based on the fault information and functions of each node in the fault propagation model, perform fault impact analysis on electronic products to obtain tabular fault impact analysis results.
[0110] Specifically, Fault Impact Analysis (FMECA) involves obtaining a tabular version of FMECA, which includes the following steps:
[0111] The fault information of each node at each level in the fault propagation model is input into the functional FMECA table as the fault mode of the corresponding electronic product node.
[0112] Input the functional information of each node at each level in the fault propagation model into the functional FMECA table, which serves as the function of the corresponding electronic product node.
[0113] The higher-level fault modes of each node in each level of the fault propagation model are input into the functional FMECA table as the fault impact of the corresponding electronic product node.
[0114] The fault modes of each node at each level in the fault propagation model are input into the functional FMECA table as the fault causes of the next higher level of the corresponding electronic product node.
[0115] The probability of failure at each node in each level of the fault propagation model is input into the functional FMECA table as the probability of failure mode occurrence for the corresponding electronic product node.
[0116] By following the steps above, the information from the fault propagation model is input into the corresponding positions in the functional FMECA table, automatically completing the initial functional FMECA. Functional FMECA can be used to analyze the reliability of electronic products.
[0117] S402. Based on the results of the fault impact analysis, analyze the causes and impacts of critical faults at each node.
[0118] Among them, critical failures refer to failures that have the greatest impact on electronic products, such as failures that can directly cause electronic products to malfunction.
[0119] S403. Based on the failure probability and severity of each node in the failure impact analysis results, determine the top event. Based on the graphical failure and transmission relationship of the failure transmission model and the logical relationship of the failure transmission model, generate a fault tree in reverse order modeling.
[0120] It should be noted that the method of generating fault trees by reverse modeling is well known to those in the field and will not be elaborated here.
[0121] S404. Perform quantitative and qualitative analysis on the fault tree to obtain reliability analysis results, which include the minimum cut set of the top event, the probability of the top event, the probability importance, the structural importance, and the critical importance.
[0122] It should be noted that the minimum cut set of the top event, the probability of the top event, the probability importance, the structural importance, and the critical importance are well known to those in the field and will not be elaborated here.
[0123] like Figure 5 As shown, Figure 5 This is a flowchart illustrating another electronic product analysis method provided in this application embodiment. This embodiment relates to an optional method for constructing a correlation matrix based on a fault transmission model. Based on the above embodiment, S104 includes the following steps:
[0124] S501. Find the fault modes of each node in the lowest level of each level, and form a fault mode set by combining the fault modes of the nodes in the lowest level.
[0125] S502. Locate all test points in the fault propagation model and combine the tests of all test points into a test set.
[0126] Specifically, a test point can be any point on the line connecting two nodes, or it can be the endpoint of the line connecting the nodes.
[0127] S503. Select the i-th test from the test set in order as the target test, where i is an integer greater than or equal to 1 and less than or equal to the total number of tests in the test set.
[0128] S504. Query the target test point to which the target test belongs from all test points, and find the output port through the connection between the target test point and the output port.
[0129] S505: Query all fault modes contained in the output port, draw a fault tree with each fault mode as the top event, and combine the fault trees into a fault tree set.
[0130] S506. Select the j-th fault mode from the fault mode set in order as the target fault mode. Input the target fault mode into all fault trees in the fault tree set to obtain the value of the element in the j-th row and i-th column of the correlation matrix, where j is an integer greater than or equal to 1 and less than or equal to the total number of all fault modes.
[0131] In one embodiment, the j-th fault mode is selected sequentially from the fault mode set as the target fault mode, and the target fault mode is input into all fault trees in the fault tree set to obtain the value of the element in the j-th row and i-th column of the correlation matrix, including:
[0132] If the fault impact analysis algorithm determines that the target fault mode is true and the top event has occurred, then the value of the element in the j-th row and i-th column of the correlation matrix is determined to be equal to the first preset value, where the first preset value is used to characterize the correlation between the target fault mode and the target test.
[0133] In this embodiment, the first preset value is 1, but is not limited to 1.
[0134] It should be noted that if, after a target failure mode occurs, the impact of the target failure mode can be propagated backward along the input and output ports and the connections between nodes in the model in the direction of functional execution, and reaches a test point, then the target failure mode is considered to be relevant to the reachable target test.
[0135] If the occurrence of the target failure mode in an electronic product indicates that the target test has failed, then the target failure mode is said to be related to the target test. If the passing of the target test indicates that the target failure mode has not occurred, then the target test is said to be related to the target failure mode. If the target failure mode and the target test can be mutually deduced, then they are said to be mutually related, or the target test is a symmetrical test.
[0136] In one embodiment, the electronic product analysis method further includes:
[0137] If the fault impact analysis algorithm determines that the target fault mode is true and the top event has not occurred, then the value of the element in the j-th row and i-th column of the correlation matrix is equal to the second preset value, where the second preset value is used to characterize that there is no correlation between the target fault mode and the target test.
[0138] In this embodiment, the second preset value is 0, but is not limited to 0.
[0139] In one specific embodiment, the set of failure modes is F = [F1, F2, ..., F...]. m The test set is T = [T1, T2, ..., T]. n The fault tree set is Tr = [Tr1, Tr2, ..., Tr]. o The specific process for constructing the correlation matrix is as follows:
[0140] 1) From the test set T = [T1, T2, ..., T n Select a test case Tj in sequence to begin analysis;
[0141] 2) Locate the test point to which test Tj belongs, and find the output port connected to the test point by connecting the test point to the output port;
[0142] 3) Query all fault modes contained in the output port, and draw a fault tree with each fault mode as the top event, forming a fault tree set Tr = [Tr1, Tr2, ..., Tr...]. o ];
[0143] 4) From the fault mode set F = [F1, F2, ..., Fm Select a fault mode Fi in sequence and substitute it into all fault trees in the fault tree set. Then, call the fault effect analysis algorithm to determine whether the fault tree top event will occur when only the fault mode Fi is true. If the fault tree top event will occur, then the fault mode Fi is... i With test T j It has correlation, and the corresponding position ft in the correlation matrix. ij The value of ft is assigned to 1; otherwise, if none of the fault tree top events occur, then ft ij =0;
[0144] Among them, the fault impact analysis algorithm mainly substitutes the fault mode value of the module into the model to solve the state value of each output port, which is a kind of fault propagation deduction process.
[0145] 5) Determine the next fault mode F in the fault mode set. i+1 With test T j The correlation is calculated until all fault modes are determined, and the vector T in the j-th column of the correlation matrix is completed. j =[ft 1j ,ft 2j ,…,ft mj ] T Results analysis.
[0146] 6) Determine the next test case T in the test set. j+1 The correlation with the fault mode set is used to complete the vector T in the (j+1)th column of the correlation matrix. j+1 =[ft 1j+1 ,ft 2j+1 ,…,ft mj+1 ] T The results analysis continued until all tests in the test set had undergone correlation analysis and the correlation matrix was constructed. The form of the correlation matrix is shown in Table 1.
[0147] Table 1. Correlation Matrix Form
[0148]
[0149] The electronic product analysis method provided in this embodiment constructs a correlation matrix to determine the correlation between failure modes and testing, that is, to determine the correlation between reliability and testability.
[0150] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0151] Based on the same inventive concept, this application also provides an electronic product analysis apparatus for implementing the electronic product analysis method described above. The solution provided by this apparatus is similar to the solution described in the above method; therefore, the specific limitations in one or more embodiments of the electronic product analysis apparatus provided below can be found in the limitations of the reliability and testability co-modeling method based on fault physics described above, and will not be repeated here.
[0152] In one embodiment, such as Figure 6 As shown, Figure 6 This is a structural block diagram of the electronic product analysis device provided in the embodiments of this application. The device 600 includes:
[0153] Simulation module 601 is used to perform simulation analysis on electronic products in order to obtain fault information and various levels of the electronic products;
[0154] Model building module 602 is used to build a fault propagation model based on fault information and each level;
[0155] The first acquisition module 503 is used to perform fault impact analysis and fault tree analysis on electronic products based on the fault propagation model in order to obtain the reliability analysis results of electronic products.
[0156] The second acquisition module 604 is used to construct a correlation matrix based on the fault transmission model and obtain the testability analysis results of electronic products based on the correlation matrix.
[0157] In one embodiment, the simulation module 601 includes:
[0158] The first determining module is used to determine the load profile of the electronic product based on the task profile of the electronic product.
[0159] The second determination module is used to determine the functions of each level of the electronic product and each node in each level, and to construct a digital prototype model of the electronic product.
[0160] The third determination module is used to establish a stress simulation model of the electronic product based on the digital prototype model, and apply the load profile to the stress simulation model to solve for the stress profile and key failure parts of the electronic product under the load profile.
[0161] The fourth determination module is used to determine the potential failure mechanism analysis results of each node of the electronic product based on the key failure points and actual failure data.
[0162] The fifth determination module is used to determine the fault detection method corresponding to different potential fault mechanisms and analyze the fault transmission path based on the analysis results of potential fault mechanisms and the functional structure of electronic products.
[0163] The sixth determination module is used to determine the pre-failure time of the potential failure mechanism of each node under the stress profile based on the failure physical model corresponding to the different potential failure mechanisms of each node in the electronic product.
[0164] The seventh determination module is used to determine the fault physical model parameter matrix based on the model parameters of the fault physical model of each node of the electronic product, and to determine the large sample pre-fault time of each node based on the fault physical model parameter matrix, the fault physical model, the stress sequence in the stress profile and the duration of different stress values.
[0165] The eighth determination module is used to determine the failure probability of each node based on the large sample failure time of each node.
[0166] In one embodiment, the model building module 602 includes:
[0167] The first association module is used to construct a hierarchical diagram of electronic products according to each level, and to establish the relationship between the function of each node and the corresponding node.
[0168] The second association module is used to establish the association between each node and the corresponding node's potential failure modes, potential failure mechanisms, failure physical models, failure detection methods, failure propagation paths, and failure probabilities.
[0169] The ninth determination module is used to determine the fault transmission relationship between nodes based on the potential fault modes, potential fault mechanisms, fault physical models, fault detection methods, fault propagation paths, fault probabilities, and actual fault information of each node, so as to complete the construction of the fault propagation model.
[0170] In one embodiment, the first acquisition module 603 includes:
[0171] The first analysis module is used to perform fault impact analysis on electronic products based on the fault information and functions of each node in the fault propagation model, so as to obtain tabular fault impact analysis results.
[0172] The first analysis module is used to analyze the causes and effects of critical faults at each node based on the results of the fault impact analysis.
[0173] The generation module is used to determine the top event based on the failure probability and severity of each node in the failure impact analysis results, and to generate a fault tree in reverse order modeling based on the graphical fault and transmission relationship of the fault transmission model and the logical relationship of the fault transmission model.
[0174] The acquisition module is used to perform quantitative and qualitative analysis on the fault tree to obtain reliability analysis results, which include the minimum cut set of the top event, the probability of the top event, the probability importance, the structural importance, and the critical importance.
[0175] In one embodiment, the second acquisition module 604 includes:
[0176] The first search module is used to search for the fault modes of each node in the lowest level of each level, and to form a fault mode set by combining the fault modes of the nodes in the lowest level.
[0177] The second search module is used to find all test points in the fault propagation model and combine the tests of all test points into a test set.
[0178] The first selection module is used to select the i-th test from the test set in sequence as the target test, where i is an integer greater than or equal to 1 and less than or equal to the total number of tests in the test set.
[0179] The second selection module is used to query the target test point to which the target test belongs from all test points, and find the output port through the connection between the target test point and the output port.
[0180] The query module is used to query all fault modes contained in the output port, draw a fault tree with each fault mode as the top event, and combine the fault trees into a fault tree set.
[0181] The selection module is used to select the j-th fault mode as the target fault mode in sequence from the fault mode set. The target fault mode is input into all fault trees in the fault tree set to obtain the value of the element in the j-th row and i-th column of the correlation matrix, where j is an integer greater than or equal to 1 and less than or equal to the total number of all fault modes.
[0182] In one embodiment, the selection module is specifically used to determine that when the fault impact analysis algorithm determines that the target fault mode is true and the top event has occurred, the value of the element in the j-th row and i-th column of the correlation matrix is equal to a first preset value, wherein the first preset value is used to characterize the correlation between the target fault mode and the target test.
[0183] In one embodiment, the selection module is further specifically used to determine that, when the fault impact analysis algorithm determines that the target fault mode is true and the top event has not occurred, the value of the element in the j-th row and i-th column of the correlation matrix is equal to a second preset value, wherein the second preset value is used to characterize that there is no correlation between the target fault mode and the target test.
[0184] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 7 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores electronic product analysis data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements an electronic product analysis method.
[0185] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0186] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:
[0187] Simulation analysis is performed on electronic products to obtain fault information and its various levels.
[0188] Construct a fault propagation model based on fault information and each level;
[0189] Based on the fault propagation model, fault impact analysis and fault tree analysis are performed on electronic products to obtain the reliability analysis results of electronic products.
[0190] Based on the fault propagation model, a correlation matrix is constructed, and the testability analysis results of electronic products are obtained from the correlation matrix.
[0191] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:
[0192] Simulation analysis is performed on electronic products to obtain fault information and its various levels.
[0193] Construct a fault propagation model based on fault information and each level;
[0194] Based on the fault propagation model, fault impact analysis and fault tree analysis are performed on electronic products to obtain the reliability analysis results of electronic products.
[0195] Based on the fault propagation model, a correlation matrix is constructed, and the testability analysis results of electronic products are obtained from the correlation matrix.
[0196] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0197] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0198] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A method for analyzing electronic products, characterized in that, include: The electronic product is simulated and analyzed to obtain its fault information and the fault levels at each stage. A fault propagation model is constructed based on the fault information and each of the aforementioned levels; Based on the fault propagation model, fault impact analysis and fault tree analysis are performed on the electronic product to obtain the reliability analysis results of the electronic product. Based on the fault transmission model, a correlation matrix is constructed, and the testability analysis results of the electronic product are obtained according to the correlation matrix. The step of performing simulation analysis on the electronic product to obtain fault information and its various levels includes: Determine the load profile of the electronic product based on the task profile of the electronic product; Determine the functions of each level of the electronic product and each node in each level, and construct a digital prototype model of the electronic product; Based on the digital prototype model, a stress simulation model of the electronic product is established, and the load profile is applied to the stress simulation model to obtain the stress profile and key failure points of the electronic product under the load profile. Based on the key failure locations and actual failure data, the potential failure mechanism analysis results for each node of the electronic product are determined, wherein the potential failure mechanism analysis results include potential failure modes, potential failure mechanisms, and failure physical models; Based on the analysis results of the potential fault mechanisms and the functional structure of the electronic product, the fault detection methods corresponding to different potential fault mechanisms are determined, and the fault propagation path is analyzed. Based on the fault physics model corresponding to the different potential fault mechanisms of each node of the electronic product, the pre-fault time of the potential fault mechanism of each node under the stress profile is determined. Based on the model parameters of the physical model of each node of the electronic product, the physical model of the fault is determined, and based on the physical model of the fault, the physical model, the stress sequence in the stress profile and the time of action of different stress values, the time before failure of each node is determined. Based on the large sample time before failure of each node, determine the failure probability of each node. The fault information includes the potential fault mode, potential fault mechanism, fault physical model, fault detection method, fault propagation path and fault probability.
2. The electronic product analysis method according to claim 1, characterized in that, The step of constructing a fault transmission model based on the fault information and each of the aforementioned levels includes: Construct a hierarchical diagram of the electronic product according to each of the aforementioned levels, and establish the functional relationship between each node and the corresponding node. Establish the correlation between each node and its corresponding potential failure modes, potential failure mechanisms, failure physical models, failure detection methods, failure propagation paths, and failure probabilities; Based on the potential failure modes, potential failure mechanisms, failure physical models, failure detection methods, failure propagation paths, failure probabilities, and actual failure information of each node, the failure propagation relationships between each node are determined to complete the construction of the failure propagation model.
3. The electronic product analysis method according to claim 1 or 2, characterized in that, The process of performing fault impact analysis and fault tree analysis on the electronic product based on the fault propagation model to obtain the reliability analysis results of the electronic product includes: Based on the fault information and function of each node in the fault transmission model, the electronic product is subjected to fault impact analysis to obtain tabular fault impact analysis results. Based on the failure impact analysis results, analyze the causes and impacts of the critical failures at each node; The top event is determined based on the failure probability and severity of each node in the failure impact analysis results. Based on the graphical failure and transmission relationship of the failure transmission model and the logical relationship of the failure transmission model, a fault tree is generated in reverse order modeling. The fault tree is subjected to quantitative and qualitative analysis to obtain the reliability analysis results, wherein the reliability analysis results include the minimum cut set of the top event, the probability of occurrence of the top event, the probability importance, the structural importance, and the critical importance.
4. The electronic product analysis method according to claim 3, characterized in that, The construction of the correlation matrix based on the fault transmission model includes: Find the fault modes of each node in the lowest level of each level, and form a fault mode set by the fault modes of the nodes in the lowest level. Find all test points in the fault propagation model and combine the tests of all test points into a test set. Select the i-th test from the test set in order as the target test, where i is an integer greater than or equal to 1 and less than or equal to the total number of tests in the test set; From all the test points, query the target test point to which the target test belongs, and find the output port through the connection between the target test point and the output port; Query all the fault modes contained in the output port, draw a fault tree with each fault mode as the top event, and form a fault tree set with each fault tree; Select the j-th fault mode from the fault mode set in sequence as the target fault mode, and input the target fault mode into all fault trees in the fault tree set to obtain the value of the element in the j-th row and i-th column of the correlation matrix, where j is an integer greater than or equal to 1 and less than or equal to the total number of all fault modes.
5. The electronic product analysis method according to claim 4, characterized in that, The step of sequentially selecting the j-th fault mode from the fault mode set as the target fault mode, and inputting the target fault mode into all fault trees in the fault tree set to obtain the value of the element in the j-th row and i-th column of the correlation matrix includes: If the fault impact analysis algorithm determines that the target fault mode is true and the top event occurs, then the value of the element in the j-th row and i-th column of the correlation matrix is determined to be equal to a first preset value, wherein the first preset value is used to characterize the correlation between the target fault mode and the target test.
6. The electronic product analysis method according to claim 5, characterized in that, The method further includes: If the fault impact analysis algorithm determines that the target fault mode is true and the top event has not occurred, then the value of the element in the j-th row and i-th column of the correlation matrix is determined to be equal to the second preset value, wherein the second preset value is used to characterize that there is no correlation between the target fault mode and the target test.
7. An electronic product analysis device, characterized in that, The device includes: The simulation module is used to perform simulation analysis on the electronic product to obtain the fault information and various levels of the electronic product; The model building module is used to build a fault transmission model based on the fault information and each of the levels; The first acquisition module is used to perform fault impact analysis and fault tree analysis on the electronic product based on the fault propagation model, so as to obtain the reliability analysis results of the electronic product. The second acquisition module is used to construct a correlation matrix based on the fault transmission model, and obtain the testability analysis results of the electronic product based on the correlation matrix. The step of performing simulation analysis on the electronic product to obtain fault information and its various levels includes: Determine the load profile of the electronic product based on the task profile of the electronic product; Determine the functions of each level of the electronic product and each node in each level, and construct a digital prototype model of the electronic product; Based on the digital prototype model, a stress simulation model of the electronic product is established, and the load profile is applied to the stress simulation model to obtain the stress profile and key failure points of the electronic product under the load profile. Based on the key failure locations and actual failure data, the potential failure mechanism analysis results for each node of the electronic product are determined, wherein the potential failure mechanism analysis results include potential failure modes, potential failure mechanisms, and failure physical models; Based on the analysis results of the potential fault mechanisms and the functional structure of the electronic product, the fault detection methods corresponding to different potential fault mechanisms are determined, and the fault propagation path is analyzed. Based on the fault physics model corresponding to the different potential fault mechanisms of each node of the electronic product, the pre-fault time of the potential fault mechanism of each node under the stress profile is determined. Based on the model parameters of the physical model of each node of the electronic product, the physical model of the fault is determined, and based on the physical model of the fault, the physical model, the stress sequence in the stress profile and the time of action of different stress values, the time before failure of each node is determined. Based on the large sample time before failure of each node, determine the failure probability of each node. The fault information includes the potential fault mode, potential fault mechanism, fault physical model, fault detection method, fault propagation path and fault probability.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1-6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 1-6.