Chip tool architecture implementation method, platform, electronic device and storage medium

Abstract

The application provides a chip tool architecture implementation method, platform, electronic equipment and storage medium, wherein the method comprises the following steps: based on a chip design system, performing chip design to obtain design data, the chip design comprising at least one of architecture design, parameter design, simulation design and layout design; based on a chip verification system, applying the design data to perform chip processing test, and recording process data of the chip processing test, the chip processing test comprising at least one of chip processing, chip packaging and performance test; the process data is used for adjusting the chip design and / or adjusting the chip processing test. The chip tool architecture implementation method, platform, electronic equipment and storage medium provided by the embodiment of the application fully consider the correlation between chip design and verification, form auxiliary control of the whole chain from chip design to final performance test, form a closed loop feedback loop, and help to realize design and production of large-scale and high-performance chips.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip tool architecture implementation method, platform, electronic device, and storage medium. Background Technology

[0002] With the rapid development of quantum computing, the performance requirements for quantum chips are becoming increasingly demanding. This, in turn, places higher demands on the management and control of each process in chip design and fabrication.

[0003] Currently, the main design aids for chips are CAD and other drafting software, and electromagnetic field simulation software such as HFSS. Chip fabrication tools include micro-nano fabrication instruments and equipment such as lithography machines and coating machines. However, these design and fabrication tools are independent of each other and cannot exchange data. This results in the data generated in each process not being effectively utilized, thus affecting chip performance and the efficiency of R&D iteration and upgrades. Summary of the Invention

[0004] This invention provides a chip tool architecture implementation method, platform, electronic device, and storage medium to solve the defects in the prior art where design and fabrication tools are independent of each other and cannot achieve data interaction, resulting in the ineffective use of data generated in each process, thereby affecting chip performance and R&D iteration efficiency.

[0005] This invention provides a chip tool architecture implementation method, applied to a chip tool architecture implementation platform, the chip tool architecture implementation platform including a chip design system and a chip verification system, the method comprising:

[0006] Based on the chip design system, chip design is performed to obtain design data, and the chip design includes at least one of architecture design, parameter design, simulation design, and layout design.

[0007] Based on the chip verification system, the design data is used to perform chip fabrication testing, and the process data of the chip fabrication testing is recorded. The chip fabrication testing includes at least one of chip fabrication, chip packaging, and performance testing.

[0008] The process data is used to adjust the chip design and / or the chip fabrication and testing.

[0009] According to the chip tool architecture implementation method provided by the present invention, the process data includes:

[0010] At least one of the following: process data, chip packaging requirements, chip packaging scheme, chip layout design requirements, chip interface information, chip performance feedback information, equipment performance feedback information, and noise environment feedback information;

[0011] The design data includes at least one of the following: chip architecture data, chip parameter requirements, chip structure dimensions, and chip layout.

[0012] According to the chip tool architecture implementation method provided by the present invention, at least one of the process data, chip packaging scheme, chip performance feedback information and equipment performance feedback information in the process data is used to adjust the architecture design in the chip design;

[0013] The chip performance feedback information and / or device performance feedback information in the process data are used to adjust the parameter design in the chip design;

[0014] The process data in the process data is used to adjust the simulation design in the chip design;

[0015] The chip layout design requirements in the process data are used to adjust the layout design in the chip design.

[0016] According to the chip tool architecture implementation method provided by the present invention, the chip performance feedback information in the process data is used to adjust the chip processing in the chip processing test;

[0017] The chip performance feedback information and noise environment feedback information in the process data are used to adjust the chip packaging during chip processing and testing.

[0018] The present invention also provides a chip tool architecture implementation platform, including: a chip design system and a chip verification system, wherein the chip verification system performs chip fabrication and testing process data, which is used to adjust the chip design performed by the chip design system, and / or to adjust the chip fabrication and testing.

[0019] The chip design system includes a serially connected architecture parameter layout design module and a first simulation module. The architecture parameter layout design module is used for architecture design, parameter design, and layout design.

[0020] Alternatively, the chip design system includes a chip architecture module, a parameter design module, and a layout design module connected in sequence, and further includes a second simulation module, which is disposed between the parameter design module and the layout design module, and / or after the layout design module.

[0021] According to the chip tool architecture implementation platform provided by the present invention, the first simulation module includes a first simulation calculation unit and a first comprehensive simulation unit, and the architecture parameter layout design module is located between the first simulation calculation unit and the first comprehensive simulation unit;

[0022] The second simulation module includes a second simulation calculation unit and a second comprehensive simulation unit. The second simulation calculation unit is located before the layout design module, and the second comprehensive simulation unit is located after the layout design module.

[0023] According to the chip tool architecture implementation platform provided by the present invention, the chip verification system includes a chip processing and packaging module and a performance testing module connected in sequence.

[0024] Alternatively, the chip verification system may include a chip processing module, a chip packaging module, and a performance testing module connected in sequence.

[0025] The chip tool architecture implementation platform provided by the present invention further includes:

[0026] A chip task requirement module, which is connected to the chip design system, is used to transmit task requirements to the chip design system so that the chip design system can perform chip design based on the task requirements.

[0027] A chip documentation module, which is connected to the chip verification system, is used to receive chip performance reports output by the chip verification system.

[0028] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the chip tool architecture implementation method as described above.

[0029] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the chip tool architecture implementation method as described above.

[0030] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the chip tool architecture implementation method as described above.

[0031] The chip tool architecture implementation method, platform, electronic device, and storage medium provided by this invention, based on a chip design system, perform chip design to obtain design data. Chip design includes at least one of architecture design, parameter design, simulation design, and layout design. Based on a chip verification system, the design data is applied to perform chip fabrication and testing, and process data of chip fabrication and testing is recorded. Chip fabrication and testing includes at least one of chip fabrication, chip packaging, and performance testing. The process data is used to adjust the chip design and / or adjust the chip fabrication and testing. By fully considering the correlation between chip design and verification, a complete chain of auxiliary control is formed from chip design, simulation, fabrication and packaging to final performance testing, and a closed-loop feedback loop is established. This can efficiently improve chip design, rapidly achieve chip iterative upgrades, and contribute to the design and production of large-scale, high-performance chips. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This is a flowchart illustrating the chip tool architecture implementation method provided by the present invention;

[0034] Figure 2 This is one of the structural schematic diagrams of the chip tool architecture implementation platform provided by the present invention;

[0035] Figure 3 This is the second schematic diagram of the chip tool architecture implementation platform provided by the present invention;

[0036] Figure 4 This is the third schematic diagram of the chip tool architecture implementation platform provided by the present invention;

[0037] Figure 5 This is the fourth schematic diagram of the chip tool architecture implementation platform provided by the present invention;

[0038] Figure 6 This is the fifth schematic diagram of the chip tool architecture implementation platform provided by the present invention;

[0039] Figure 7 This is the sixth schematic diagram of the chip tool architecture implementation platform provided by the present invention;

[0040] Figure 8 This is the seventh schematic diagram of the chip tool architecture implementation platform provided by the present invention;

[0041] Figure 9 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0043] With the rapid development of quantum computing, higher demands are being placed on the design, simulation, and fabrication processes of quantum chips, as well as the coordination, feedback, and management between these processes. It is foreseeable that when the number of qubits exceeds 100, traditional design, wiring, manufacturing, packaging, and testing methods will no longer meet the requirements for high-performance chip production. Achieving end-to-end chip production support management for quantum chips, and standardizing and normalizing each process, is an urgent problem to be solved.

[0044] Based on this, embodiments of the present invention provide a chip tool architecture implementation method that fully considers the inherent relationship between chip design and standardized manufacturing, effectively utilizes the data generated in each process, forms a feedback iterative loop, and thereby achieves rapid iterative upgrades of the chip.

[0045] Figure 1 This is a flowchart illustrating the chip tool architecture implementation method provided by the present invention. The execution entity of this method can be a chip tool architecture implementation platform, which includes a chip design system and a chip verification system. This platform can be implemented through software and / or hardware, and can be integrated into an electronic device, such as a personal computer, a cloud device, or a mobile device like a smartphone or tablet.

[0046] like Figure 1 As shown, the chip tool architecture implementation method provided in this embodiment of the invention includes:

[0047] Step 110: Based on the chip design system, perform chip design to obtain design data. Chip design includes at least one of architecture design, parameter design, simulation design, and layout design.

[0048] Specifically, in the chip development process, designers need to perform a lot of calculations and designs to obtain various design data for the chip.

[0049] Chip design here includes at least one of the following: architecture design, parameter design, simulation design, and layout design. Architecture design refers to conducting a feasibility analysis of the chip design task requirements, and based on this, determining the basic architecture and module decomposition to output the chip architecture. Specific types of chip architectures may include: one-dimensional chains, two-dimensional chains, mesh architectures, two-dimensional chips, three-dimensional chips, etc.

[0050] Parameter design involves determining the specific parameter requirements of the chip, which may include the chip's structural parameters, the connectivity between qubits, the coupling method and strength between qubits, the coupling method and strength between qubits and the resonant cavity and control lines, as well as relevant test parameters in subsequent testing stages.

[0051] Simulation design typically employs various simulation software to perform modeling and simulation, ensuring that chip functions, performance, throughput, and other indicators are achievable. For example, simulation results can be used to determine the chip's resonant cavity frequency and quality factor.

[0052] The layout design may include the substrate layout and the layout of each quantum device, as well as the quantum circuit design of each quantum device layout.

[0053] Every chip design process generates design data. For example, architecture design yields chip architecture data, parameter design yields chip parameter requirements, simulation design yields chip structure dimensions, and layout design yields chip layout.

[0054] Preferably, the chip in this embodiment of the invention is a quantum chip.

[0055] Step 120: Based on the chip verification system, apply the design data to perform chip fabrication testing, and record the process data of chip fabrication testing. Chip fabrication testing includes at least one of chip fabrication, chip packaging, and performance testing.

[0056] Process data is used to adjust chip design and / or chip fabrication and testing.

[0057] Specifically, the chip verification system is used to process and test the chip based on the design data obtained in step 110, and to record the process data obtained during chip processing and testing.

[0058] Chip fabrication testing includes at least one of chip fabrication, chip packaging, and performance testing. Chip fabrication and chip packaging refer to the completion of chip fabrication and packaging to obtain a quantum chip. Performance testing can be performed on the quantum chip, the equipment used to fabricate the chip, or the noise environment of the chip fabrication and packaging process. Alternatively, it can involve testing any two or all of the chip, equipment, and environment; this embodiment of the invention does not specifically limit this.

[0059] Given that existing technologies lack comprehensive auxiliary control for each process in the entire chain, from chip design, simulation, manufacturing and packaging to final performance testing, the data obtained in each process cannot be effectively utilized, which is detrimental to the standardization and normalization of each process and thus affects the efficiency of chip iteration and upgrades.

[0060] In this embodiment of the invention, process data obtained during chip fabrication and testing are recorded, and the process data is used to adjust the chip design and / or the chip fabrication and testing.

[0061] This can form a feedback loop, feeding back process data obtained during chip fabrication and testing to any one or more processes in chip design, thereby adjusting the chip design scheme; or feeding back process data to any one or more processes in chip fabrication and testing, adjusting the chip fabrication and testing scheme; or feeding back to both chip design and chip fabrication and testing simultaneously, adjusting both chip design and chip fabrication and testing.

[0062] The method provided in this invention, based on a chip design system, performs chip design to obtain design data. Chip design includes at least one of architecture design, parameter design, simulation design, and layout design. Based on a chip verification system, the design data is applied to perform chip fabrication and testing, and process data of the chip fabrication and testing is recorded. Chip fabrication and testing includes at least one of chip fabrication, chip packaging, and performance testing. The process data is used to adjust the chip design and / or to adjust the chip fabrication and testing. By fully considering the correlation between chip design and verification, a complete auxiliary control chain is formed from chip design, simulation, fabrication and packaging to final performance testing, creating a closed-loop feedback loop. This can efficiently improve chip design, rapidly achieve chip iterative upgrades, and contribute to the design and production of large-scale, high-performance chips.

[0063] Based on the above embodiments, the process data includes:

[0064] At least one of the following: process data, chip packaging requirements, chip packaging scheme, chip layout design requirements, chip interface information, chip performance feedback information, equipment performance feedback information, and noise environment feedback information;

[0065] Design data includes at least one of the following: chip architecture data, chip parameter requirements, chip structure dimensions, and chip layout.

[0066] Specifically, chip fabrication testing includes at least one of chip fabrication, chip packaging, and performance testing. Correspondingly, the process data of chip fabrication testing specifically includes at least one of the process data obtained from chip fabrication and chip packaging requirements. The process data may specifically include process-related data such as process scheme, process performance, and process accuracy.

[0067] The process data specifically includes at least one of the following: chip packaging scheme obtained from chip packaging, chip layout design requirements, and chip interface information;

[0068] The process data specifically includes at least one of the following: chip performance feedback information, equipment performance feedback information, and noise environment feedback information;

[0069] Chip design includes architecture design, parameter design, simulation design, and layout design. Accordingly, chip design data includes at least one of the following: chip architecture data obtained from architecture design, chip parameter requirements obtained from parameter design, chip structure dimensions obtained from simulation design, and chip layout obtained from layout design.

[0070] Based on the above embodiments, at least one of the process scheme, process performance, chip packaging scheme, chip performance feedback information and equipment performance feedback information in the process data is used to adjust the architecture design in the chip design;

[0071] Chip performance feedback information and / or device performance feedback information in the process data are used to adjust the parameter design in the chip design;

[0072] The process data, specifically the manufacturing process data, is used to adjust the simulation design in chip design.

[0073] The chip layout requirements in the process data are used to adjust the layout design in the chip design.

[0074] Specifically, in order to realize the architecture design feedback loop, the architecture design in the chip design can be adjusted based on at least one of the process scheme, process performance, chip packaging scheme, chip performance feedback information and equipment performance feedback information in the process data, thereby forming the architecture design feedback loop.

[0075] To implement a parameter design feedback loop, the parameter design in the chip design can be adjusted based on the chip performance feedback information and / or device performance feedback information in the process data, thereby forming a parameter design feedback loop.

[0076] To realize the simulation design feedback loop, the simulation design in the chip design can be adjusted based on the process parameters in the process data, thereby forming the simulation design feedback loop.

[0077] To realize the layout design feedback loop, the layout design in the chip design can be adjusted based on the chip layout drawing requirements in the process data, thereby forming the layout design feedback loop.

[0078] The method provided by this invention fully considers the inherent relationship between chip design and chip fabrication and testing, and forms corresponding feedback loops between process data and various processes in chip design, thereby adjusting and optimizing each design process, further improving the efficiency of chip R&D iteration and upgrading, and contributing to the design and production of large-scale, high-performance chips.

[0079] Based on any of the above embodiments, the chip performance feedback information in the process data is used to adjust the chip processing during chip processing testing;

[0080] The chip performance feedback information and noise environment feedback information in the process data are used to adjust the chip packaging during chip processing and testing.

[0081] Specifically, the process data obtained during chip fabrication and testing can be used not only to adjust the chip design, but also to adjust the chip fabrication and packaging.

[0082] In this embodiment, chip processing and packaging may include chip processing and chip packaging. In order to realize the chip processing feedback loop, the chip processing in chip processing and packaging can be adjusted based on the chip performance feedback information in the process data, thereby forming the chip processing feedback loop.

[0083] To realize the chip packaging feedback loop, the chip packaging process can be adjusted based on the chip performance feedback information and noise environment feedback information in the process data, thereby forming the chip packaging feedback loop.

[0084] The method provided by this invention fully considers the relationship between various processes in chip processing and testing, and forms corresponding feedback loops with chip processing and chip packaging respectively, thereby adjusting and optimizing chip processing and chip packaging, further improving the chip processing and packaging scheme, and contributing to the production of large-scale, high-performance chips.

[0085] The chip tool architecture implementation platform provided by the present invention is described below. The chip tool architecture implementation platform described below and the chip tool architecture implementation method described above can be referred to in correspondence.

[0086] Based on any of the above embodiments Figure 2 This is one of the structural diagrams of the chip tool architecture implementation platform provided by the present invention. The chip tool architecture implementation platform includes: a chip design system and a chip verification system. The chip verification system performs chip processing and testing process data, which is used to adjust the chip design performed by the chip design system, and / or adjust the chip processing and testing.

[0087] The chip design system includes a serially connected architecture parameter layout design module and a first simulation module. The architecture parameter layout design module is used for architecture design, parameter design, and layout design.

[0088] Alternatively, the chip design system may include a chip architecture module, a parameter design module, and a layout design module connected in sequence, and may also include a second simulation module, which may be located between the parameter design module and the layout design module, or after the layout design module.

[0089] Specifically, such as Figure 2 As shown, in one embodiment, the chip design system may include a serially connected architecture parameter layout design module and a first simulation module. The architecture parameter layout design module is used for architecture design, parameter design, and layout design, and the first simulation module is used for simulation calculation of the chip.

[0090] In one embodiment, Figure 3 This is the second schematic diagram of the chip tool architecture implementation platform provided by the present invention, as shown below. Figure 3 As shown, the chip design system includes a chip architecture module, a parameter design module, and a layout design module connected in sequence. It also includes a second simulation module, which can be placed after the layout design module to perform simulation calculations on the chip after the layout design is completed.

[0091] It should be noted that, in another embodiment, the second simulation module may be located between the parameter design module and the layout design module, that is, the second simulation module is used to perform simulation calculations on the chip before the layout design.

[0092] Based on any of the above embodiments, the first simulation module includes a first simulation calculation unit and a first comprehensive simulation unit, and the architecture parameter layout design module is located between the first simulation calculation unit and the first comprehensive simulation unit;

[0093] The second simulation module includes a second simulation calculation unit and a second comprehensive simulation unit. The second simulation calculation unit is located before the layout design module, and the second comprehensive simulation unit is located after the layout design module.

[0094] Specifically, the first simulation module may include a first simulation calculation unit and a first comprehensive simulation unit. The first simulation calculation unit is used to perform simulation calculations before the architecture parameter layout design module, and the first comprehensive simulation unit can be used to perform comprehensive simulations after the architecture parameter layout design module.

[0095] Figure 4 This is the third schematic diagram of the chip tool architecture implementation platform provided by the present invention, as shown below. Figure 4As shown, in one embodiment, the second simulation module includes a second simulation calculation unit and a second comprehensive simulation unit. The second simulation calculation unit is disposed before the layout design module, and the second comprehensive simulation unit is disposed after the layout design module.

[0096] Based on any of the above embodiments, the chip verification system includes a chip processing and packaging module and a performance testing module connected in sequence;

[0097] Alternatively, a chip verification system may include a chip fabrication module, a chip packaging module, and a performance testing module connected in sequence.

[0098] Specifically, Figure 5 This is the fourth structural schematic diagram of the chip tool architecture implementation platform provided by the present invention, as shown below. Figure 5 As shown, the chip verification system includes a chip processing and packaging module and a performance testing module connected in sequence.

[0099] In another embodiment, Figure 6 This is the fifth schematic diagram of the chip tool architecture implementation platform provided by the present invention, as shown below. Figure 6 As shown, the chip verification system includes a chip processing module, a chip packaging module, and a performance testing module connected in sequence.

[0100] Based on any of the above embodiments, the chip tool architecture implementation platform further includes:

[0101] The chip task requirement module is connected to the chip design system and is used to transmit task requirements to the chip design system so that the chip design system can perform chip design based on the task requirements.

[0102] The chip documentation module connects to the chip verification system and is used to receive chip performance reports output by the chip verification system.

[0103] Specifically, Figure 7 This is the sixth schematic diagram of the chip tool architecture implementation platform provided by the present invention, as shown below. Figure 7 As shown, the chip tool architecture implementation platform also includes:

[0104] The chip task requirement module is connected to the chip design system and outputs information about the number of qubits and their performance.

[0105] The chip documentation module connects to the chip verification system and is used to receive chip performance reports output by the chip verification system.

[0106] Based on any of the above embodiments Figure 8 This is the seventh structural schematic diagram of the chip tool architecture implementation platform provided by the present invention, as shown below. Figure 8As shown, the platform includes:

[0107] The chip task requirements module, chip architecture module, parameter design module, simulation calculation module, layout design module, chip fabrication module, chip packaging module, performance testing module, and chip documentation module are connected in sequence.

[0108] The chip architecture module obtains information on the number of bits and bit performance from the chip task requirements module, the packaging scheme from the chip packaging module, and chip performance feedback information and device performance feedback information from the performance testing module. The chip architecture module then passes the quantum chip architecture as its output to the parameter design module.

[0109] The parameter design module obtains quantum chip architecture information from the chip architecture module as input, and also receives chip performance feedback and device performance feedback from the performance testing module as input. Finally, the parameter design module outputs the specific chip parameter requirements and passes them to the simulation calculation module.

[0110] The simulation calculation module takes the specific chip parameter requirements output by the parameter design module as its input, and receives the process data information output by the chip fabrication module as its input. The simulation calculation module outputs the specific dimensional requirements of the chip structure and transmits them to the layout design module.

[0111] The layout design module receives the specific chip structure dimensions output by the simulation calculation module as input, and receives the chip layout requirements output by the chip packaging module as input. The layout design module then outputs the chip layout and transmits it to the chip fabrication module.

[0112] The chip fabrication module receives the chip layout from the layout design module as its input, and also receives chip performance feedback from the performance testing module as its input. The chip fabrication module outputs the process plan and process performance to the chip architecture module, outputs process data to the simulation calculation module, and outputs chip packaging requirements to the chip packaging module.

[0113] The chip packaging module receives chip packaging requirements from the chip fabrication module as input, and takes chip performance feedback and noise environment feedback from the performance testing module as input. The chip packaging module outputs a packaging solution and passes it to the chip architecture module, outputs chip layout requirements to the layout design module, and outputs chip interface information to the performance testing module.

[0114] The performance testing module receives chip interface information from the chip packaging module as input. It outputs chip performance feedback information and device performance feedback information to the chip architecture module and parameter design module, provides chip performance feedback information to the chip fabrication module, provides chip performance feedback information and noise environment feedback information to the chip packaging module, and outputs a chip performance report to the chip documentation module.

[0115] The platform provided by this invention fully considers the correlation between chip design and verification, forming an auxiliary control for the entire chain from chip design, simulation, processing and packaging to final performance testing, and forming a closed-loop feedback loop. This can efficiently improve chip design, quickly realize chip iterative upgrades, and help achieve the design and production of large-scale, high-performance chips.

[0116] Figure 9 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 9 As shown, the electronic device may include a processor 910, a communications interface 920, a memory 930, and a communication bus 940, wherein the processor 910, the communications interface 920, and the memory 930 communicate with each other via the communication bus 940. The processor 910 can call logical instructions in the memory 930 to execute a chip tool architecture implementation method. This method includes: performing chip design based on the chip design system to obtain design data, the chip design including at least one of architecture design, parameter design, simulation design, and layout design; applying the design data to perform chip fabrication testing based on the chip verification system, and recording the process data of the chip fabrication testing, the chip fabrication testing including at least one of chip fabrication, chip packaging, and performance testing; the process data is used to adjust the chip design and / or adjust the chip fabrication testing.

[0117] Furthermore, the logical instructions in the aforementioned memory 930 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0118] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the chip tool architecture implementation method provided by the above methods. The method includes: performing chip design based on the chip design system to obtain design data, wherein the chip design includes at least one of architecture design, parameter design, simulation design, and layout design; applying the design data to perform chip fabrication testing based on the chip verification system, and recording the process data of the chip fabrication testing, wherein the chip fabrication testing includes at least one of chip fabrication, chip packaging, and performance testing; the process data is used to adjust the chip design and / or to adjust the chip fabrication testing.

[0119] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the chip tool architecture implementation method provided by the methods described above. The method includes: performing chip design based on the chip design system to obtain design data, wherein the chip design includes at least one of architecture design, parameter design, simulation design, and layout design; applying the design data to perform chip fabrication testing based on the chip verification system, and recording the process data of the chip fabrication testing, wherein the chip fabrication testing includes at least one of chip fabrication, chip packaging, and performance testing; the process data is used to adjust the chip design and / or to adjust the chip fabrication testing.

[0120] The platform embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0121] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip tool architecture implementation method, characterized in that, Applied to a chip tool architecture implementation platform, the chip tool architecture implementation platform including a chip design system and a chip verification system, the method includes: Based on the chip design system, chip design is performed to obtain design data, and the chip design includes at least one of architecture design, parameter design, simulation design, and layout design. Based on the chip verification system, the design data is used to perform chip fabrication testing, and the process data of the chip fabrication testing is recorded. The chip fabrication testing includes at least one of chip fabrication, chip packaging, and performance testing. The process data is used to adjust the chip design and / or the chip fabrication and testing. Wherein, at least one of the process data, chip packaging scheme, chip performance feedback information, and equipment performance feedback information in the process data is used to adjust the architecture design in the chip design; the chip performance feedback information and / or equipment performance feedback information in the process data is used to adjust the parameter design in the chip design; the process data in the process data is used to adjust the simulation design in the chip design; and the chip layout drawing requirements in the process data are used to adjust the layout design in the chip design.

2. The chip tool architecture implementation method according to claim 1, characterized in that, The process data includes: At least one of the following: process data, chip packaging requirements, chip packaging scheme, chip layout design requirements, chip interface information, chip performance feedback information, equipment performance feedback information, and noise environment feedback information; The design data includes at least one of the following: chip architecture data, chip parameter requirements, chip structure dimensions, and chip layout.

3. The chip tool architecture implementation method according to claim 2, characterized in that, The chip performance feedback information in the process data is used to adjust the chip processing during the chip processing test; The chip performance feedback information and noise environment feedback information in the process data are used to adjust the chip packaging during chip processing and testing.

4. A chip tool architecture implementation platform, characterized in that, include: A chip design system and a chip verification system, wherein the chip design system is used to perform chip design to obtain design data, and the chip verification system is used to perform chip fabrication and testing based on the design data to obtain process data for chip fabrication and testing, and the process data is used to adjust the chip design performed by the chip design system, and / or adjust the chip fabrication and testing. The chip design system includes a serially connected architecture parameter layout design module and a first simulation module. The architecture parameter layout design module is used to perform architecture design, parameter design and layout design, and the first simulation module is used to perform simulation design. Alternatively, the chip design system includes a chip architecture module, a parameter design module, and a layout design module connected in sequence, and also includes a second simulation module. The second simulation module is disposed between the parameter design module and the layout design module, or disposed after the layout design module. The chip architecture module, the parameter design module, the layout design module, and the second simulation module are used sequentially to perform architecture design, parameter design, layout design, and simulation design. Wherein, at least one of the process data, chip packaging scheme, chip performance feedback information, and equipment performance feedback information in the process data is used to adjust the architecture design in the chip design; the chip performance feedback information and / or equipment performance feedback information in the process data is used to adjust the parameter design in the chip design; the process data in the process data is used to adjust the simulation design in the chip design; and the chip layout drawing requirements in the process data are used to adjust the layout design in the chip design.

5. The chip tool architecture implementation platform according to claim 4, characterized in that, The first simulation module includes a first simulation calculation unit and a first integrated simulation unit, and the architecture parameter layout design module is located between the first simulation calculation unit and the first integrated simulation unit; The second simulation module includes a second simulation calculation unit and a second comprehensive simulation unit. The second simulation calculation unit is located before the layout design module, and the second comprehensive simulation unit is located after the layout design module.

6. The chip tool architecture implementation platform according to claim 4, characterized in that, The chip verification system includes a chip processing and packaging module and a performance testing module connected in sequence. Alternatively, the chip verification system may include a chip processing module, a chip packaging module, and a performance testing module connected in sequence.

7. The chip tool architecture implementation platform according to claim 4, characterized in that, Also includes: A chip task requirement module, which is connected to the chip design system, is used to transmit task requirements to the chip design system so that the chip design system can perform chip design based on the task requirements. A chip documentation module, which is connected to the chip verification system, is used to receive chip performance reports output by the chip verification system.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the chip tool architecture implementation method as described in any one of claims 1 to 3.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the chip tool architecture implementation method as described in any one of claims 1 to 3.

Images