Control circuit and memory for a delay-locked loop circuit

Abstract

The disclosure provides a control circuit and a memory of a delay-locked loop circuit, comprising: a signal adjusting module receiving a first clock signal and a read pulse signal, for generating at least one sampling clock signal based on the first clock signal, and generating and outputting a first pulse signal based on the at least one sampling clock signal and the read pulse signal; a main signal generating module receiving the read pulse signal, for generating and outputting a main signal based on the read pulse signal; a slave signal generating module connected with the signal adjusting module, for generating and outputting a slave signal based on the received first pulse signal; and an enable signal generating module connected with the main signal generating module and the slave signal generating module, for generating and outputting an enable signal based on the received main signal and slave signal, the enable signal being used for starting or stopping the delay-locked loop circuit. The disclosure controls the starting time and the starting duration of the delay-locked loop based on the read pulse signal and the sampling clock signal, without setting a mode register, and optimizes the control circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of memory, and in particular, to a control circuit of a delay-locked loop circuit and a memory. BACKGROUND

[0002] When a dynamic random access memory (DRAM) performs a read operation, a delay-locked loop (DLL) needs to be turned on to eliminate the clock offset between the internal clock and the external clock, so as to ensure that the external clock, the data strobe signal (DQS), and the data output signal (DQ) are aligned on the edges.

[0003] In the related art, the DLL control circuit is relatively complex, and needs to refer to the time length parameters related to the read operation set in the mode register to determine the turn-on time of the delay-locked loop circuit. The time length parameters related to the read operation include, for example, the column address strobe (Latency, CL), the burst length (BL), and the like.

[0004] Therefore, how to optimize the control circuit of the DLL is a problem to be solved. SUMMARY

[0005] The present disclosure provides a control circuit of a delay-locked loop circuit and a memory, which optimizes the control circuit of the delay-locked loop.

[0006] According to some embodiments, the first aspect of the present disclosure provides a control circuit of a delay-locked loop circuit, comprising: a signal conditioning module, a master signal generation module, a slave signal generation module, and an enable signal generation module.

[0007] The signal conditioning module receives a first clock signal and a read pulse signal, generates at least one sampling clock signal based on the first clock signal, and generates and outputs a first pulse signal based on the at least one sampling clock signal and the read pulse signal.

[0008] The master signal generation module receives the read pulse signal, and generates and outputs a master signal based on the read pulse signal.

[0009] The slave signal generation module is connected to the signal conditioning module, and generates and outputs a slave signal based on the received first pulse signal.

[0010] The enable signal generation module is connected to the master signal generation module and the slave signal generation module, and generates and outputs an enable signal based on the received master signal and slave signal. The enable signal is used to turn on or turn off the delay-locked loop circuit.

[0011] In some embodiments, the signal adjusting module is configured to determine a starting time of an active level of the first pulse signal according to the at least one sampling clock signal; the main signal generating module is configured to control a starting time and an ending time of an active level of the main signal according to the read pulse signal; the slave signal generating module is configured to control a starting time of an active level of the slave signal according to the first pulse signal; and the enable signal generating module is configured to determine a starting time of an active level of the enable signal according to the main signal and determine an ending time of an active level of the enable signal according to the slave signal.

[0012] In some embodiments, the number of the at least one sampling clock signal is one; and the signal adjusting module comprises a first adjusting unit and a first output unit.

[0013] The input end of the first adjusting unit receives the first clock signal, and is configured to generate and output a first sampling clock signal based on the first clock signal, wherein a clock period of the first sampling clock signal is T1.

[0014] The first input end of the first output unit receives the first sampling clock signal, and the second input end of the first output unit receives the read pulse signal; the first output unit is configured to sample the read pulse signal based on the first sampling clock signal, generate and output a first pulse signal.

[0015] The starting time of the active level of the first pulse signal is a time when a trigger edge of the first sampling clock signal is sampled to the active level of the read pulse signal; and the active level maintenance time of the first pulse signal is one clock period T1 of the first sampling clock signal.

[0016] In some embodiments, the first adjusting unit comprises a plurality of first flip-flops connected in cascade.

[0017] The clock control end of the first first flip-flop is connected to the input end of the first adjusting unit, and receives the first clock signal.

[0018] The inverting output end of each first flip-flop is connected to the input end of itself; and the clock control end of each first flip-flop except the first first flip-flop is connected to the non-inverting output end of the previous first flip-flop.

[0019] The non-inverting output end of the last first flip-flop outputs the first sampling clock signal.

[0020] In some embodiments, the first output unit comprises a first delay unit and a second flip-flop.

[0021] The input end of the first delay unit is connected to the second input end of the first output unit, and receives the read pulse signal; and the first delay unit is configured to generate and output a delayed read pulse signal.

[0022] The input end of the second flip-flop is connected with the delayed read pulse signal; the clock control end of the second flip-flop is used as the first input end of the first output unit and receives the first sampling clock signal; the inverted output end of the second flip-flop outputs the first pulse signal; and the second flip-flop is used for sampling the delayed read pulse signal based on the first sampling clock signal.

[0023] In some embodiments, the number of the at least one sampling clock signal is two; and the signal adjusting module comprises a second adjusting unit, a third adjusting unit and a second output unit.

[0024] The input end of the second adjusting unit receives the first clock signal, and is used for generating and outputting a second sampling clock signal based on the first clock signal, wherein the clock period of the second sampling clock signal is T2.

[0025] The input end of the third adjusting unit receives the second sampling clock signal, and is used for generating and outputting a third sampling clock signal based on the second sampling clock signal, wherein the clock period of the third sampling clock signal is T3.

[0026] The first input end of the second output unit receives the second sampling clock signal, the second input end of the second output unit receives the third sampling clock signal, and the third input end of the second output unit receives the read pulse signal; the second output unit is used for sampling the read pulse signal based on the third sampling clock signal, generating and outputting a second pulse signal, and sampling the second pulse signal based on the second sampling clock signal, generating and outputting a first pulse signal.

[0027] The starting moment of the effective level of the second pulse signal is the moment when the trigger edge of the third sampling clock signal is sampled to the effective level of the read pulse signal; the effective level maintenance time of the second pulse signal is one clock period T3 of the third sampling clock signal; the starting moment of the effective level of the first pulse signal is the moment when the trigger edge of the second sampling clock signal is first sampled to the effective level of the second pulse signal; and the effective level maintenance time of the first pulse signal is one clock period T3 of the third sampling clock signal.

[0028] In some embodiments, the second output unit comprises a second delay unit, a third flip-flop and a fourth flip-flop.

[0029] The input end of the second delay unit is used as the third input end of the second output unit and receives the read pulse signal; and the second delay unit is used for generating and outputting a delayed read pulse signal.

[0030] The input end of the third flip-flop receives the delayed read pulse signal; the clock control end of the third flip-flop serves as the first input end of the second output unit and receives the third sampling clock signal 64T; the positive phase output end of the third flip-flop outputs the second pulse signal; and the third flip-flop is configured to sample the delayed read pulse signal based on the third sampling clock signal.

[0031] The input end of the fourth flip-flop receives the second pulse signal; the clock control end of the fourth flip-flop serves as the second input end of the second output unit and receives the second sampling clock signal 16T; the inverting output end of the fourth flip-flop outputs the first pulse signal; and the fourth flip-flop is configured to sample the second pulse signal based on the second sampling clock signal.

[0032] In some embodiments, the second adjusting unit includes a plurality of fifth flip-flops connected in cascade;

[0033] The clock control end of the first fifth flip-flop serves as the input end of the second adjusting unit and receives the first clock signal;

[0034] The inverting output end of each fifth flip-flop is connected to the input end of the fifth flip-flop; and the clock control end of each fifth flip-flop except the first fifth flip-flop is connected to the positive phase output end of the previous fifth flip-flop;

[0035] The positive phase output end of the last fifth flip-flop outputs the second sampling clock signal.

[0036] In some embodiments, the third adjusting unit includes a plurality of sixth flip-flops connected in cascade;

[0037] The clock control end of the first sixth flip-flop serves as the input end of the third adjusting unit and receives the second sampling clock signal;

[0038] The inverting output end of each sixth flip-flop is connected to the input end of the sixth flip-flop; and the clock control end of each sixth flip-flop except the first sixth flip-flop is connected to the positive phase output end of the previous sixth flip-flop;

[0039] The positive phase output end of the last sixth flip-flop outputs the third sampling clock signal.

[0040] In some embodiments, the slave signal generation module includes a third delay unit, a first inverter and a first NAND gate;

[0041] The first input end of the first NAND gate serves as the input end of the slave signal generation module and receives the first pulse signal; the input end of the third delay unit is connected to the first input end of the first NAND gate; the output end of the third delay unit is connected to the input end of the first inverter; the output end of the first inverter is connected to the second input end of the first NAND gate; and the output end of the first NAND gate outputs the slave signal.

[0042] In some embodiments, the main signal generation module comprises a second inverter;

[0043] An input terminal of the second inverter is configured to receive the read pulse signal, and an output terminal of the second inverter is configured to output the main signal.

[0044] In some embodiments, the main signal generation module comprises a third inverter and a first OR gate;

[0045] A first input terminal of the first OR gate is configured to receive the read pulse signal, and a second input terminal of the first OR gate is configured to receive an activation pulse signal; wherein the activation pulse signal is generated before the read pulse signal;

[0046] An output terminal of the first OR gate is connected to an input terminal of the third inverter, and an output terminal of the third inverter is configured to output the main signal.

[0047] In some embodiments, the enable signal generation module comprises a reset-set flip-flop; the reset-set flip-flop comprises a second NAND gate and a third NAND gate;

[0048] A first input terminal of the second NAND gate is configured to receive the main signal as a first input terminal of the enable signal generation module, a second input terminal of the second NAND gate is connected to an output terminal of the third NAND gate, and a second input terminal of the third NAND gate is configured to receive the slave signal as a second input terminal of the enable signal generation module;

[0049] A first input terminal of the third NAND gate is connected to an output terminal of the second NAND gate, and an output terminal of the second NAND gate is configured to output the enable signal as an output terminal of the enable signal generation module;

[0050] A reset terminal of the third NAND gate is connected to a first reset signal, and the first reset signal is configured to indicate a reset of the reset-set flip-flop.

[0051] In some embodiments, the control circuit further comprises a reset control module;

[0052] A first input terminal of the reset control module is configured to receive the read pulse signal, and a second input terminal of the reset control module is configured to receive a second reset signal;

[0053] The reset control module is configured to generate and output a reset control signal based on the read pulse signal and the second reset signal; wherein the reset control signal is connected to a reset terminal of the signal conditioning module, and is configured to indicate a reset of the signal conditioning module.

[0054] In some embodiments, the reset control module comprises a fourth NAND gate, a fourth delay unit, a fourth inverter, a fifth NAND gate, and a fifth inverter;

[0055] The first input end of the fourth NAND gate is the first input end of the reset control module, and receives the reading pulse signal; the input end of the fourth delay unit is connected to the first input end of the fourth NAND gate; the output end of the fourth delay unit is connected to the input end of the fourth inverter; the output end of the fourth inverter is connected to the second input end of the fourth NAND gate; and the output end of the fourth NAND gate is connected to the second input end of the fifth NAND gate.

[0056] The first input end of the fifth NAND gate is the second input end of the reset control module, and receives the second reset signal; the output end of the fifth NAND gate is connected to the input end of the fifth inverter; and the output end of the fifth inverter is the output end of the reset control module, and outputs the reset control signal.

[0057] In some embodiments, the control circuit further comprises a feedback control module.

[0058] The first input end of the feedback control module receives the enable signal, the second input end of the feedback control module receives the internal clock signal, and the output end of the feedback control module outputs the first clock signal; wherein the clock period of the internal clock signal is the same as the clock period of the first clock signal.

[0059] The feedback control module is configured to control whether the signal adjustment module receives the first clock signal based on the enable signal.

[0060] In some embodiments, the feedback control module comprises a sixth NAND gate, a fifth delay unit and a sixth inverter.

[0061] The first input end of the sixth NAND gate is the first input end of the feedback control module, and receives the enable signal; the second input end of the sixth NAND gate is the second input end of the feedback control module, and receives the internal clock signal; the output end of the sixth NAND gate is connected to the input end of the fifth delay unit; the output end of the fifth delay unit is connected to the input end of the sixth inverter; and the output end of the sixth inverter is the output end of the feedback control module, and outputs the first clock signal.

[0062] According to some embodiments, the second aspect of the present disclosure provides a memory comprising the control circuit of the delay-locked loop circuit according to the first aspect.

[0063] The control circuit and the memory of the delay-locked loop circuit provided by the embodiment of the present disclosure comprise a signal adjusting module, a main signal generating module, a slave signal generating module and an enable signal generating module; the signal adjusting module receives a first clock signal and a read pulse signal, generates at least one sampling clock signal based on the first clock signal, and generates and outputs a first pulse signal based on the at least one sampling clock signal and the read pulse signal; the main signal generating module receives the read pulse signal, generates and outputs a main signal based on the read pulse signal; the slave signal generating module is connected to the signal adjusting module, generates and outputs a slave signal based on the received first pulse signal; the enable signal generating module is connected to the main signal generating module and the slave signal generating module, generates and outputs an enable signal based on the received main signal and slave signal, and the enable signal is used to start or stop the delay-locked loop circuit. The embodiment of the present disclosure controls the starting time and the starting duration of the delay-locked loop circuit based on the read pulse signal and the sampling clock signal, does not need to refer to a mode register, and optimizes the control circuit. BRIEF DESCRIPTION OF DRAWINGS

[0064] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the present disclosure.

[0065] Figure 1 It is a structural schematic diagram of a control circuit of a typical delay-locked loop circuit.

[0066] Figure 2 It is a timing diagram of a control circuit of a typical delay-locked loop circuit.

[0067] Figure 3 It is a structural schematic diagram of a control circuit of a delay-locked loop circuit provided by the embodiment of the present disclosure.

[0068] Figure 4 It is a circuit diagram of a control circuit of a delay-locked loop circuit provided by the embodiment of the present disclosure.

[0069] Figure 5 It is a timing diagram of a control circuit of a delay-locked loop circuit provided by the embodiment of the present disclosure.

[0070] Figure 6 It is a circuit diagram of another main signal generating module provided by the embodiment of the present disclosure.

[0071] Figure 7 It is a circuit diagram of another control circuit of a delay-locked loop circuit provided by the embodiment of the present disclosure.

[0072] Figure 8 It is a timing diagram of another control circuit of a delay-locked loop circuit provided by the embodiment of the present disclosure.

[0073] Figure 9 Another circuit diagram for generating the second sampling clock signal and the third sampling clock signal is provided for the embodiments of the present disclosure.

[0074] The specific embodiments of the present disclosure have been shown through the above drawings, and will be described in more detail hereinafter. The drawings and the written description are not intended to limit the scope of the present disclosure in any way, but to explain the concept of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0075] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, the same numbers are used to indicate the same or similar components. The embodiments described in the following exemplary embodiments do not represent all the embodiments consistent with the present disclosure. Rather, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0076] When performing a read operation, a dynamic random access memory (DRAM) needs to generate a data strobe signal (DQS) to tell the host the corresponding sampling time point of each bit of data output by the current read operation, in addition to taking data from the storage array to the data output port (DQ). The DQS signal generated internally by the DRAM is derived from the internal clock division operation, and the internal clock is generated by the external clock through internal delay, that is, there is a skew between the internal clock and the external clock. According to the requirements of the Standard Performance Evaluation Corporation (SPEC), the edges of the final external clock, DQS, and DQ are aligned, and at least the edges of the internal clock and the external clock are aligned. The clock output by the delay-locked loop (DLL) is a clock signal with the skew eliminated, which can be used by subsequent modules to generate DQS and other signals.

[0077] In the related art, the control circuit of the delay-locked loop circuit is relatively complex, and needs to refer to the time length parameters related to the read operation set in the mode register to determine the start time of the delay-locked loop circuit. The time length parameters related to the read operation include, for example, column address strobe (Latency, CL), burst length (BL), etc. The CL is the time from the read command to the first data output. The BL is the number of storage units involved in continuous transmission in burst mode, and the burst mode refers to a mode in which adjacent storage units in the same row continuously transmit data.

[0078] Figure 1 This is a schematic diagram of the control circuit structure of a typical delay phase-locked loop circuit, such as... Figure 1 As shown, the circuit includes registers, a calculator, and a generator. The mode register calculates the time required to complete each read operation based on preset BL and CL information. For example, the cycle for completing one read operation is CL + BL / 2 (from the issuance of the read command to the output of the last bit of data). Assuming BL = 16, considering the 2-bit CRC checksum added due to Cyclic Redundancy Check (CRC), BL = 18. According to the SPEC requirements, the maximum value of CL that can be set in the mode register is 66 seconds, so the maximum time of the read operation cycle, Tmax = 18 / 2 + 66 = 75 seconds. The calculator generates master and slave signals based on the clock signal, the read command, and the required time (CL + BL / 2) provided by the mode register. The generator generates an enable signal based on the master and slave signals to turn the delay-locked loop (PLL) circuit on and off.

[0079] Figure 2 This is a timing diagram of the control circuit for a typical delay phase-locked loop (PLL) circuit, showing the waveforms of the clock signal, master signal, slave signal, and enable signal. Here, 1RD represents the time when the first read command is issued; 2RD represents the time when the second read command is issued; 3RD represents the time when the third read command is issued; and 4RD represents the time when the fourth read command is issued.

[0080] For the master signal, slave signal, and enable signal, the effective voltage level is taken as high. The start time of the effective voltage level of the enable signal is its rising edge, responding to the rising edge of the master signal. The end time of the effective voltage level of the enable signal is its falling edge, responding to the rising edge of the slave signal. The rising edge of the master signal corresponds to the time when each read command is issued. For the slave signal, there are two cases: if no new read command is issued within (CL+BL / 2) after the time when the read command is issued, then the rising edge of the slave signal corresponds to the time (CL+BL / 2) elapsed after the time when the read command is issued; if a new read command is issued within (CL+BL / 2) after the time when the read command is issued, then the rising edge of the slave signal corresponds to the time delayed by (CL+BL / 2) based on the new read command.

[0081] like Figure 2As shown, the time interval between 2RD and 1RD is greater than the time length (CL+BL / 2) required for the completion of the read operation, and the rising edge of the signal is generated at the time point (CL+BL / 2) after 1RD. The time interval between 3RD and 2RD is less than the time length (CL+BL / 2) required for the completion of the read operation, the time interval between 4RD and 3RD is less than the time length (CL+BL / 2) required for the completion of the read operation, and therefore the signal remains low between 2RD and 4RD, and correspondingly, the enable signal remains high during this period, that is, the delay-locked loop circuit is always on during this period. After 4RD, no new read command is issued, and therefore the rising edge of the signal is generated at the time point (CL+BL / 2) after 4RD, and correspondingly, the enable signal falls to low, that is, the delay-locked loop circuit is closed.

[0082] The above Figure 1 The control circuit of the delay-locked loop circuit shown is relatively complex, and how to optimize the control circuit of the DLL is a problem to be solved in the field.

[0083] Based on this, the control circuit of the delay-locked loop circuit and the memory provided by the embodiments of the present disclosure control the start time and the start length of the delay-locked loop through the read pulse signal and the sampling clock signal, without referring to the mode register, and the optimization of the control circuit is realized.

[0084] The technical solutions of the present disclosure and how the technical solutions of the present disclosure solve the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in detail in some embodiments. The embodiments of the present disclosure will be described below with reference to the drawings.

[0085] Embodiment one

[0086] Figure 3 A structural schematic diagram of a control circuit of a delay-locked loop circuit provided by the embodiments of the present disclosure is shown. As shown in the figure, Figure 2 The control circuit of the delay-locked loop circuit includes a signal conditioning module, a master signal generation module, a slave signal generation module, and an enable signal generation module.

[0087] The signal adjusting module receives the first clock signal and the read pulse signal, and is configured to generate at least one sampling clock signal based on the first clock signal, and generate and output the first pulse signal based on the at least one sampling clock signal and the read pulse signal; the main signal generating module receives the read pulse signal, and is configured to generate and output the main signal based on the read pulse signal; the slave signal generating module is connected to the signal adjusting module, and is configured to generate and output the slave signal based on the received first pulse signal; and the enable signal generating module is connected to the main signal generating module and the slave signal generating module, and is configured to generate and output the enable signal based on the received main signal and slave signal, and the enable signal is used to turn on or turn off the DLL circuit.

[0088] Specifically, the present embodiment establishes the association of the enable signal with the read pulse signal and the sampling clock signal through the main signal and the slave signal, and then the control of the DLL circuit can be realized through the read pulse signal and the first pulse signal. The present embodiment does not need to introduce the mode register and the parameters such as the CL information and the BL information set in the mode register, simplifies the control of the DLL output clock, and is also conducive to simplifying the control circuit.

[0089] Further, according to Figure 1 and Figure 2 It can be known that in the related technology using the mode register, the continuous opening duration of the DLL circuit in the single read pulse signal scenario is (CL+BL / 2). Since there is an upper limit for the setting of the CL information in the mode register, and there is an upper limit for (CL+BL / 2), the continuous opening duration of the DLL circuit in the single read pulse signal scenario in the related technology has an upper limit. The present embodiment controls the continuous opening duration of the DLL circuit in the single read pulse signal scenario through the circuit, and the range can be set larger, which is suitable for the memory with a longer read operation period, improves the application range, and optimizes the control circuit.

[0090] Further, the present embodiment controls the enable signal through the read pulse signal, turns on the DLL circuit when the clock output by the DLL circuit is needed, and controls the effective level duration of the enable signal through the sampling clock signal, turns off the DLL circuit when the clock output by the DLL circuit is not needed, achieves the effect of saving current, and improves the performance of the DRAM chip.

[0091] In some embodiments, the signal adjusting module is configured to determine the starting time of the effective level of the first pulse signal according to the at least one sampling clock signal; the main signal generating module is configured to control the starting time and the ending time of the effective level of the main signal according to the read pulse signal; the slave signal generating module is configured to determine the starting time of the effective level of the slave signal according to the first pulse signal; and the enable signal generating module is configured to determine the starting time of the effective level of the enable signal according to the main signal, and determine the ending time of the effective level of the enable signal according to the slave signal.

[0092] Specifically, based on the association between the enable signal and the read pulse signal and the sampling clock signal, the level of the enable signal is valid when the read pulse signal arrives, to control the DLL circuit to be turned on; and the level of the enable signal is continuously valid according to at least one sampling clock signal, to control the DLL circuit to be continuously turned on. The minimum value of the duration of the valid level of the enable signal needs to be greater than or equal to the duration required for each read operation to be completed, to ensure that each read operation can be successfully completed.

[0093] Further, the duration of the valid level of the enable signal is related to the clock period of the sampling clock signal. The at least one sampling clock signal generated by the signal conditioning module can be one or more, so that the duration of the valid level of the enable signal can be determined by the clock period of one sampling clock signal, or can be determined by the clock periods of multiple sampling clock signals being superimposed. The duration of the valid level of the enable signal can be set according to the duration required for the actual read operation period to be completed. Optionally, the first clock signal is frequency-division generated into one or more sampling clock signals through frequency-division technology.

[0094] Figure 4 a circuit diagram of a control circuit of a delay-locked loop circuit provided by an embodiment of the present disclosure; Figure 5 a timing diagram of a control circuit of a delay-locked loop circuit provided by an embodiment of the present disclosure. The following will be described in combination with Figure 4 and Figure 5 The control circuit of the delay-locked loop circuit is described by taking generation of one sampling clock signal as an example.

[0095] In some embodiments, the number of the at least one sampling clock signal is one; and the signal conditioning module comprises a first conditioning unit and a first output unit.

[0096] The input end of the first conditioning unit receives the first clock signal, for generating and outputting a first sampling clock signal based on the first clock signal, wherein the clock period of the first sampling clock signal is T1.

[0097] The first input end of the first output unit receives the first sampling clock signal, and the second input end of the first output unit receives the read pulse signal; the first output unit is configured to sample the read pulse signal based on the first sampling clock signal, to generate and output a first pulse signal;

[0098] The starting time of the valid level of the first pulse signal is the time when the trigger edge of the first sampling clock signal is sampled to the read pulse signal being at the valid level; and the valid level maintenance time of the first pulse signal is one clock period T1 of the first sampling clock signal.

[0099] In some embodiments, the first adjusting unit comprises a plurality of first flip-flops connected in cascade; a clock control end of a first flip-flop is used as an input end of the first adjusting unit and receives the first clock signal; an inverted output end of each flip-flop is connected with an input end of the flip-flop; a clock control end of each flip-flop except the first flip-flop is connected with a positive output end of a flip-flop in a previous stage; and a positive output end of a last flip-flop outputs the first sampling clock signal.

[0100] Specifically, referring to Figure 4 , the first adjusting unit comprises five first flip-flops (D1-1 to D1-5) connected in cascade. The clock period of the first clock signal is taken as 2T, i.e. CLK-2T; and the first clock signal with the clock period of 2T is divided by the frequency divider comprising the five first flip-flops to generate the first sampling clock signal with the clock period of 64T, i.e. CLK-64T.

[0101] In the first adjusting unit, the number of flip-flops connected in cascade can be adjusted to adjust the clock period of the first sampling clock signal. Specifically, as shown in Figure 4 , the clock signal CLK-32T with the clock period of 32T can be generated by using four flip-flops connected in cascade with the reference clock of 2T. In addition, the clock signal with the clock period of 128T can be generated by using six flip-flops connected in cascade. The clock period of the first sampling clock signal can be set according to actual requirements.

[0102] Referring to the waveform diagram shown in Figure 5 , due to the sequential response of the signals and the delay of the flip-flops themselves, the trigger edges of the signals output by the flip-flops connected in cascade will have a certain offset, and the offset duration between two adjacent flip-flops will not exceed 2T. Specifically, the trigger edge of CLK-4T lags behind the trigger edge of CLK-2T; it can be known that the trigger edge of CLK-8T lags behind the trigger edge of CLK-4T; and so on, the trigger edge of the signal with a longer clock period lags behind the trigger edge of the signal with a shorter clock period.

[0103] In some embodiments, the first output unit comprises a first delay unit and a second flip-flop D2. An input end of the first delay unit is used as a second input end of the first output unit and receives the read pulse signal RD_CMD; the first delay unit is used for generating and outputting a delayed read pulse signal RD_DLY;

[0104] An input end of the second flip-flop D2 is connected with the delayed read pulse signal RD_DLY; a clock control end of the second flip-flop D2 is used as a first input end of the first output unit and receives the first sampling clock signal; the second flip-flop D2 is used for sampling the delayed read pulse signal based on the first sampling clock signal, and a first pulse signal is output from an inverted output end of the second flip-flop D2.

[0105] Specifically, referring to Figure 4 and Figure 5 , the first delay unit generates a delayed read pulse signal RD DLY based on the read pulse signal RD CMD. The first delay unit needs to have a reasonable delay duration to ensure that the valid level of the delayed read pulse signal RD DLY can be sampled by the first trigger edge of the first sampling clock signal, thereby controlling the level state of the first pulse signal. The above setting establishes the control relationship of the read pulse signal RD CMD to the first pulse signal through the RD DLY signal.

[0106] Further, the duration of the valid level of the delayed read pulse signal RD DLY is equal to the duration of the valid level of the read pulse signal RD CMD, which is taken as 2T in this embodiment. In some embodiments, other signals can also be generated to establish the control relationship of the read pulse signal RD CMD to the first pulse signal, and the duration of the valid level of the generated other signals can not be equal to the duration of the valid level of the read pulse signal RD CMD.

[0107] Further, in this embodiment, the valid level of the delayed read pulse signal RD DLY is taken as a high level. In some embodiments, the valid level of the RD DLY signal can also be set to a low level, and the related circuit is adjusted to ensure that the control relationship of the read pulse signal RD CMD to the first pulse signal can be established through the RD DLY signal.

[0108] In this embodiment, the high level of the delayed read pulse signal RD DLY is sampled by the first rising edge of the first sampling clock signal CLK-64T, so that the first pulse signal / RD_64T output by the inverted output end of the second flip-flop D2 is flipped to 0. The duration of the high level of the RD DLY signal is taken as 2T, which is less than the clock period 64T of the first sampling clock signal CLK-64T. Therefore, when no new RD DLY signal is generated, the next rising edge of the first sampling clock signal CLK-64T will sample the low level of the RD DLY signal, so that the first pulse signal / RD_64T output by the inverted output end of the second flip-flop D2 is flipped to 1. Therefore, the duration of the low level of this first pulse signal / RD_64T is equal to one clock period 64T of the first sampling clock signal.

[0109] Further, the first delay unit can be a delay element, and the delay duration of the first delay unit is the delay duration of the selected delay element; the first delay unit can also be composed of multiple delay elements in series, and the delay duration of the first delay unit is the sum of the delay durations of the selected multiple delay elements. For example, Figure 4In the embodiment, the first delay unit includes a delay device A and a delay device B in series, and thus the superposition of the delay effects of the delay device A and the delay device B serves as the delay effect of the first delay unit. The embodiment does not limit the number of delay device elements included in the first delay unit, as long as the delay effect of the first delay unit can enable the valid level of the delayed read pulse signal RD DLY to be sampled by the first trigger edge of the first sampling clock signal CLK 64T.

[0110] In addition, in actual applications, there is a certain lag between the input and the output of the flip-flop, which is reflected in Figure 5 In the waveform diagram shown in the figure, the falling edge of the first pulse signal RD 64T lags behind the trigger edge of the first sampling clock signal CLK 64T.

[0111] The following describes the slave signal generation module to which the first pulse signal is connected.

[0112] In some embodiments, the slave signal generation module includes a third delay unit, a first inverter S1, and a first NAND gate Q1. The first input end of the first NAND gate Q1 serves as the input end of the slave signal generation module and receives the first pulse signal; the input end of the third delay unit is connected to the first input end of the first NAND gate Q1; the output end of the third delay unit is connected to the input end of the first inverter S1; the output end of the first inverter S1 is connected to the second input end of the first NAND gate Q1; and the output end of the first NAND gate Q1 outputs the slave signal RD SLAVER.

[0113] Specifically, referring to Figure 4 and Figure 5 , the first pulse signal RD 64T is delayed by the third delay unit (for example, a delay device C) and inverted by the first inverter S1. The first pulse signal after the delay and inversion is subjected to a NAND logic operation with itself to obtain the slave signal RD SLAVER. The starting time of the valid level of the slave signal RD SLAVER corresponds to the ending time of the valid level of the first pulse signal RD 64T. The duration of the valid level of the slave signal RD SLAVER is equal to the total delay duration of the third delay unit and the first inverter.

[0114] Further, the third delay unit needs to have a reasonable delay duration, so that the duration of the valid level of the slave signal RD SLAVER is not too short or too long. Too short or too long may lead to the generation of an error enable signal, which in turn affects the control of the DLL circuit. Among them, Figure 5 In the embodiment, the duration of the valid level of the slave signal RD SLAVER is taken as an example of 4T.

[0115] Specifically, the third delay unit can be one delay element, and the delay time of the third delay unit is the delay time of the selected delay element. The third delay unit can also be a plurality of delay elements connected in series, and the delay time of the third delay unit is the sum of the delay times of the plurality of delay elements. The number of delay elements included in the third delay unit is not limited in this embodiment, as long as the correct enable signal is generated subsequently.

[0116] In some embodiments, the main signal generation module includes a second inverter S2. An input end of the second inverter S2 is configured to receive the read pulse signal, and an output end of the second inverter S2 is configured to output the main signal RD_MASTER.

[0117] Specifically, as shown in Figure 4 and Figure 5 , the active level of the main signal RD_MASTER is taken as a low level. The falling edge of the main signal RD_MASTER corresponds to the rising edge of the read pulse signal RD_CMD, and the rising edge of the main signal RD_MASTER corresponds to the falling edge of the read pulse signal RD_CMD. The duration of the active level of the main signal RD_MASTER is the same as the duration of the active level of the read pulse signal RD_CMD. The active level of the main signal RD_MASTER can also be a high level. This embodiment is not limited, as long as the correct enable signal is generated in the subsequent enable signal generation module in cooperation with the slave signal RD_SLAVER.

[0118] The enable signal generation module to which the main signal RD_MASTER and the slave signal RD_SLAVER are connected is described below.

[0119] In some embodiments, the enable signal generation module includes a reset-set flip-flop. The reset-set flip-flop includes a second NAND gate Q2 and a third NAND gate Q3.

[0120] The first input end of the second NAND gate Q2 is the first input end of the enable signal generation module, and receives the main signal RD_MASTER. The second input end of the second NAND gate Q2 is connected with the output end of the third NAND gate Q3. The second input end of the third NAND gate Q3 is the second input end of the enable signal generation module, and receives the slave signal RD_SLAVER. The first input end of the third NAND gate Q3 is connected with the output end of the second NAND gate Q2. The output end of the second NAND gate Q2 is the output end of the enable signal generation module, and outputs the enable signal RD_DLL_CLK_EN. The reset end of the third NAND gate Q3 is connected with a first reset signal RESETB1, and the first reset signal RESETB1 is used to indicate the reset of the reset-set flip-flop. The first reset signal RESETB1 is used to reset the reset-set flip-flop at power-on initialization.

[0121] Specifically, the corresponding relationship of the input and output of the reset-set flip-flop is: if the master signal RD_MASTER is 0 and the slave signal RD_SLAVE is 1, the enable signal RD_DLL_CLK_EN is 1. If the master signal RD_MASTER is 0 and the slave signal RD_SLAVE is 0, the state of the enable signal RD_DLL_CLK_EN is unstable. If the master signal RD_MASTER is 1 and the slave signal RD_SLAVE is 0, the enable signal RD_DLL_CLK_EN is 0. If the master signal RD_MASTER is 1 and the slave signal RD_SLAVE is 1, the enable signal RD_DLL_CLK_EN maintains the previous output signal.

[0122] Referring to Figure 5 The control timing of the control circuit of the delay-locked loop circuit provided in the embodiment is described by taking the single read pulse signal scenario as an example. It is assumed that the initial state of the master signal RD_MASTER is 1, the initial state of the slave signal RD_SLAVE is 1, and the initial state of the enable signal RD_DLL_CLK_EN is 0. When the master signal RD_MASTER flips to 0 in response to the read pulse signal RD_CMD, the enable signal RD_DLL_CLK_EN flips to 1. When the master signal RD_MASTER flips to 1 after a preset time delay, the enable signal RD_DLL_CLK_EN maintains the previous output signal 1. Until the slave signal RD_SLAVE flips to 0 in response to the end time of the active level of the first pulse signal RD_64T, the enable signal RD_DLL_CLK_EN flips to 0.

[0123] In combination Figure 5 , the DLL starts to output the clock when the read pulse signal RD_CMD arrives; and the DLL stops to output the clock after a time delay of 64T plus a plurality of delay time durations after the read pulse signal RD_CMD arrives. The duration of the clock output by the DLL can be adjusted by the clock period of the sampling clock signal, so that the duration of the clock output by the DLL meets the requirement of the duration of the read operation.

[0124] Figure 6 Another circuit diagram of a master signal generation module provided in the embodiment of the disclosure is provided. In some embodiments, the master signal generation module includes a third inverter S3 and a first OR gate P1. The first input end of the first OR gate P1 receives a read pulse signal RD_CMD, and the second input end of the first OR gate P1 receives an active pulse signal Active_CMD. The active pulse signal Active_CMD is generated before the read pulse signal RD_CMD. The output end of the first OR gate P1 is connected with the input end of the third inverter S3, and the output end of the third inverter S3 is used to output a master signal RD_MASTER.

[0125] The embodiment introduces an activation pulse signal according to the working characteristics of the DRAM that issues the activation pulse signal before starting the read operation, and controls the starting time and ending time of the effective level of the main signal together with the read pulse signal, and further controls the starting time of the DLL.

[0126] Specifically, when the DRAM receives the activation pulse signal, the DLL output clock starts to jump, reducing the starting time of the DLL circuit output clock. In actual application, since the read pulse signal to the enable signal, and then the enable signal to the DLL circuit, and the output of the DLL circuit driving to open all need time, in order to prevent the DLL circuit output clock from appearing deviation, the activation pulse signal issued before the read pulse signal is used to open the DLL circuit. Corresponding to the waveform chart, the enable signal is 1 when the read pulse signal arrives, instead of the previous 0.

[0127] In some embodiments, the control circuit further includes a reset control module. The first input end of the reset control module receives the read pulse signal RD_CMD, and the second input end of the reset control module receives the second reset signal RESETB2; the reset control module is used to generate and output a reset control signal RSTDT based on the read pulse signal RD_CMD and the second reset signal RESETB2; wherein the reset control signal RSTDT is connected to the reset end of the signal adjustment module, and is used to instruct the signal adjustment module to reset.

[0128] The second reset signal RESETB2 is used to reset the reset control module at the initial power-on. The read pulse signal RD_CMD controls the starting time of the effective level of the reset control signal RSTDT, and the reset control signal RSTDT instructs the signal adjustment module to reset. Specifically, refer to Figure 4 The signal adjustment module includes a plurality of flip-flops, and the reset end of each flip-flop is connected to the reset control signal RSTDT, and is used to reset according to the reset control signal RSTDT. Wherein, each time the read pulse signal RD_CMD arrives, the signal adjustment module is reset, and each flip-flop is restarted accordingly. Further, when a new read pulse signal RD_CMD arrives during the DLL continuous output clock, the time of the DLL ending output clock is recalculated with the latest read pulse signal RD_CMD as the starting point.

[0129] In some embodiments, the reset control module includes a fourth delay unit, a fourth inverter S4, a fourth NAND gate, a fifth NAND gate Q5, and a fifth inverter

[0130] The first input end of the fourth NAND gate Q4 is the first input end of the reset control module, and receives the read pulse signal RD_CMD; the input end of the fourth delay unit is connected to the first input end of the fourth NAND gate Q4; the output end of the fourth delay unit is connected to the input end of the fourth inverter S4; the output end of the fourth inverter S4 is connected to the second input end of the fourth NAND gate Q4; and the output end of the fourth NAND gate Q4 is connected to the second input end of the fifth NAND gate Q5.

[0131] The first input end of the fifth NAND gate Q5 is the second input end of the reset control module, and receives the second reset signal RESETB2; the output end of the fifth NAND gate Q5 is connected to the input end of the fifth inverter S5; and the output end of the fifth inverter S5 is the output end of the reset control module, and outputs the reset control signal RSTDT.

[0132] Referring to Figure 4 and Figure 5 , taking the high level of the reset control signal RSTDT as an example, the duration of the effective level of the reset control signal RSTDT is the delay duration of the fourth delay unit, which needs to be less than the duration of the effective level of the read pulse signal RD_CMD. In some embodiments, the reset control signal RSTDT can also be active at a low level. Specifically, the corresponding RSTDT signal can be generated according to the reset level requirements of each flip-flop in the signal conditioning module in the actual circuit.

[0133] Further, taking the high level of the second reset signal RESETB2 as an example, it is set to 1 after power-on. According to the derivation of the logic gate delay, the starting time of the effective level of the reset control signal RSTDT is later than the starting time of the effective edge of the read pulse signal. Each time the read pulse signal RD_CMD arrives, the reset control signal RSTDT generates a rising edge so that each flip-flop in the signal conditioning module restarts, and the internal clock Internal Clock (i.e., CLK-2T) generates a first rising edge. Further, when a new read pulse signal RD_CMD arrives during the duration of the DLL output clock, the time of the end of the DLL output clock is recalculated from the latest read pulse signal RD_CMD. If the effective level of the second reset signal RESETB2 is a low level, the same technical effects can also be achieved on the basis of the circuit of the reset control module shown in Figure 4 .

[0134] As shown in Figure 5 , the external clock External Clock always generates a rising edge and a falling edge, while the internal clock Internal Clock generates a rising edge and a falling edge after power-on. The clock period of the internal clock can be twice the clock period of the external clock, and the method of generating the internal clock from the external clock can refer to related technologies.

[0135] In some embodiments, the control circuit further comprises a feedback control module; a first input terminal of the feedback control module receives the enable signal, a second input terminal of the feedback control module receives the internal clock signal Internal Clock, and an output terminal of the feedback control module outputs the first clock signal; wherein the clock period of the internal clock signal Internal Clock is the same as the clock period of the first clock signal. The feedback control module is configured to control whether the signal adjustment module receives the first clock signal based on the enable signal RD DLL CLK EN.

[0136] Specifically, taking the case that the high level of the enable signal is to turn on the DLL circuit and the low level of the enable signal is to turn off the DLL circuit as an example. When the enable signal is at the low level, the feedback control module is configured to make the signal adjustment module unable to receive the first clock signal, and thus unable to generate the sampling clock signal; on the contrary, the feedback control module is configured to make the signal adjustment module able to receive the first clock signal, thereby reducing power consumption.

[0137] Further, in some embodiments, the feedback control module comprises a sixth NAND gate Q6, a fifth delay unit, and a sixth inverter; a first input terminal of the sixth NAND gate Q6 is configured as the first input terminal of the feedback control module and receives the enable signal, a second input terminal of the sixth NAND gate Q6 is configured as the second input terminal of the feedback control module and receives the internal clock signal; an output terminal of the sixth NAND gate Q6 is connected with an input terminal of the fifth delay unit; an output terminal of the fifth delay unit is connected with an input terminal of the sixth inverter S6, and an output terminal of the sixth inverter S6 is configured as the output terminal of the feedback control module and outputs the first clock signal.

[0138] Specifically, the enable signal and the internal clock signal are subjected to NAND logic calculation. When the enable signal is at the low level, the logic calculation result is at the low level regardless of whether the internal clock signal is at the low level or the high level. When the enable signal is at the high level, the logic calculation result is at the high level if the internal clock signal is at the low level, and the logic calculation result is at the low level if the internal clock signal is at the high level.

[0139] Further, in order to make the phase of the first clock signal consistent with that of the internal clock signal, the fifth delay unit and the sixth inverter S6 are configured to make the first clock signal output by the feedback control module at the high level when the enable signal is at the high level, and make the first clock signal output by the feedback control module at the low level when the enable signal is at the low level.

[0140] The embodiment also provides a memory comprising the control circuit of the delay-locked loop circuit as described above.

[0141] The control circuit and the memory of the delay-locked loop circuit provided by the embodiment comprise: a signal adjusting module, which generates at least one sampling clock signal based on a first clock signal and generates a first pulse signal in combination with a read pulse signal; a main signal generating module, which generates a main signal based on the read pulse signal; a slave signal generating module, which generates a slave signal based on the first pulse signal; and an enabling signal generating module, which generates an enabling signal based on the main signal and the slave signal to turn on or turn off the delay-locked loop circuit; wherein the sampling clock signal controls the starting moment of the effective level of the first pulse signal; the read pulse signal controls the starting moment of the effective level of the main signal; the first pulse signal controls the starting moment of the effective level of the slave signal; and the main signal and the slave signal control the starting moment and the ending moment of the effective level of the enabling signal, respectively. The disclosure controls the starting moment and the starting duration of the delay-locked loop based on the read pulse signal and the sampling clock signal, without setting a mode register, and optimizes the control circuit.

[0142] Embodiment two

[0143] Figure 7 The circuit diagram of another control circuit of a delay-locked loop circuit provided by the embodiment of the disclosure is provided. Figure 8 The timing diagram of another control circuit of a delay-locked loop circuit provided by the embodiment of the disclosure is provided. The control circuit of the delay-locked loop circuit is described below in combination with Figure 7 and Figure 8 The control circuit of the delay-locked loop circuit is described by taking the generation of one sampling clock signal as an example.

[0144] In some embodiments, the number of the at least one sampling clock signal is two; and the signal adjusting module comprises a second adjusting unit, a third adjusting unit and a second output unit.

[0145] The input end of the second adjusting unit receives the first clock signal, for generating and outputting a second sampling clock signal based on the first clock signal, wherein the clock period of the second sampling clock signal is T2; and the input end of the third adjusting unit receives the second sampling clock signal, for generating and outputting a third sampling clock signal based on the second sampling clock signal, wherein the clock period of the third sampling clock signal is T3.

[0146] The first input end of the second output unit receives the second sampling clock signal, the second input end of the second output unit receives the third sampling clock signal, and the third input end of the second output unit receives the read pulse signal; the second output unit is configured to sample the read pulse signal based on the third sampling clock signal to generate and output a second pulse signal, and sample the second pulse signal based on the second sampling clock signal to generate and output the first pulse signal;

[0147] The starting moment of the effective level of the second pulse signal is the moment when the trigger edge of the third sampling clock signal is sampled to the effective level of the reading pulse signal. The effective level maintenance time of the second pulse signal is one clock cycle T3 of the third sampling clock signal. The starting moment of the effective level of the first pulse signal is the moment when the trigger edge of the second sampling clock signal is sampled to the effective level of the second pulse signal for the first time. The effective level maintenance time of the first pulse signal is one clock cycle T3 of the third sampling clock signal.

[0148] In some embodiments, the second adjusting unit includes a plurality of fifth flip-flops in cascade. The clock control end of the first fifth flip-flop is used as the input end of the second adjusting unit and receives the first clock signal. The inverting output end of each fifth flip-flop is connected with the input end thereof. The clock control end of each fifth flip-flop except the first fifth flip-flop is connected with the non-inverting output end of the previous fifth flip-flop. The non-inverting output end of the last fifth flip-flop outputs the second sampling clock signal.

[0149] Specifically, referring to Figure 7 , the second adjusting unit includes three fifth flip-flops (D5-1, D5-2, D5-3) in cascade. The clock cycle of the first clock signal is taken as an example of 2T, i.e. CLK-2T. The frequency divider formed by the three fifth flip-flops in cascade divides the first clock signal with the clock cycle of 2T to generate the second sampling clock signal with the clock cycle of 16T, i.e. CLK-16T. The clock cycle of the second sampling clock signal can be adjusted by setting the number of the flip-flops in cascade in the second adjusting unit. The clock cycle of the second sampling clock signal can be set according to actual requirements.

[0150] Referring to Figure 7 , due to the sequential response of the signals and the delay of the flip-flops themselves, the trigger edges of the signals output by the flip-flops in cascade will have a certain offset, and the offset duration between the adjacent two flip-flops will not exceed 2T. Specifically, the trigger edge of CLK-4T lags behind the trigger edge of CLK-2T. It can be known that the trigger edge of CLK-8T lags behind the trigger edge of CLK-4T. In this way, the trigger edge of the signal with a longer clock cycle lags behind the trigger edge of the signal with a shorter clock cycle.

[0151] In some embodiments, the third adjusting unit includes a plurality of sixth flip-flops in cascade. The clock control end of the first sixth flip-flop is used as the input end of the third adjusting unit and receives the second sampling clock signal. The inverting output end of each sixth flip-flop is connected with the input end thereof. The clock control end of each sixth flip-flop except the first sixth flip-flop is connected with the non-inverting output end of the previous sixth flip-flop. The non-inverting output end of the last sixth flip-flop outputs the third sampling clock signal.

[0152] Specifically, referring toFigure 7 The third adjusting unit includes two cascaded sixth flip-flops (D6-1, D6-2). The clock period of the second sampling clock signal is taken as 16T, that is, CLK16T; the frequency divider formed by the two cascaded sixth flip-flops is used to divide the second sampling clock signal with the clock period of 16T to generate the third sampling clock signal with the clock period of 64T, that is, CLK-64T. The clock period of the third sampling clock signal can be adjusted by setting the number of the cascaded flip-flops in the third adjusting unit. The clock period of the third sampling clock signal can be set according to actual requirements.

[0153] In some embodiments, Figure 9 Another circuit diagram for generating the second sampling clock signal and the third sampling clock signal is provided for the embodiments of the present disclosure. As shown in Figure 9 The clock period of the second sampling clock signal is taken as 16T, the clock period of the third sampling clock signal is taken as 64T, and the clock period of the first clock signal is taken as 2T. The frequency divider formed by the three cascaded flip-flops (Dm-1 to Dm-3) is used to divide the first clock signal with the clock period of 2T to generate the second sampling clock signal with the clock period of 16T. The frequency divider formed by the five cascaded flip-flops (Dn-1 to Dn-5) is used to divide the first clock signal with the clock period of 2T to generate the third sampling clock signal with the clock period of 64T. Figure 9 Compared with the circuit for generating the second sampling clock signal and the third sampling clock signal shown in Figure 7 More flip-flop elements and circuit board area are required, and the energy consumption is higher.

[0154] In some embodiments, the second output unit includes a second delay unit, a third flip-flop D3 and a fourth flip-flop D4.

[0155] The input end of the second delay unit serves as the third input end of the second output unit and receives the read pulse signal RD_CMD; the second delay unit is used to generate and output a delayed read pulse signal RD_DLY;

[0156] The input end of the third flip-flop D3 receives the delayed read pulse signal; the clock control end of the third flip-flop D3 serves as the first input end of the second output unit and receives the third sampling clock signal; the third flip-flop D3 is used to sample the delayed read pulse signal RD_DLY based on the third sampling clock signal and output a second pulse signal from the noninverting output end of the third flip-flop D3;

[0157] An input terminal of the fourth flip-flop D4 receives the second pulse signal; a clock control terminal of the fourth flip-flop D4 serves as a second input terminal of the second output unit and receives the second sampling clock signal; and the fourth flip-flop D4 is configured to sample the second pulse signal based on the second sampling clock signal and output the first pulse signal from an inverting output terminal of the fourth flip-flop D4.

[0158] Specifically, referring to Figure 7 and Figure 8 , the second delay unit generates a delayed read pulse signal RD DLY based on the read pulse signal RD CMD. The second delay unit needs to have a reasonable delay duration to ensure that the valid level of the delayed read pulse signal RD DLY can be sampled by the first trigger edge of the third sampling clock signal, thereby controlling the level state of the first pulse signal. The above setting establishes the control relationship of the read pulse signal RD_CMD on the first pulse signal through the RD DLY signal.

[0159] Further, the duration of the valid level of the delayed read pulse signal RD DLY is equal to the duration of the valid level of the read pulse signal RD_CMD, which is 4T in this embodiment. In some embodiments, other signals can be generated to establish the control relationship of the read pulse signal RD_CMD on the first pulse signal, and the duration of the valid level of the generated other signals can not be equal to the duration of the valid level of the read pulse signal RD_CMD.

[0160] The function and effect of the second output unit will be described below with the high-level validity of the delayed read pulse signal RD DLY as an example.

[0161] The valid level of the delayed read pulse signal RD DLY is taken as an example of high level. The high level of the delayed read pulse signal RD DLY is sampled by the first rising edge of the third sampling clock signal CLK-64T, so that the second pulse signal RD_64T output by the non-inverting output terminal of the third flip-flop D3 is flipped to 1. The duration of the high level of the RD DLY signal is taken as an example of 2T, which is less than the clock period 64T of the third sampling clock signal CLK-64T. When no new RD DLY signal is generated, the next rising edge of the third sampling clock signal CLK-64T will sample the low level of the RD DLY signal, so that the second pulse signal RD_64T output by the non-inverting output terminal of the third flip-flop D3 is flipped to 0. Therefore, the duration of the high level (i.e. the valid duration) of the second pulse signal RD_64T is equal to one clock period 64T of the third sampling clock signal.

[0162] Further, the high level of the second pulse signal RD_64T is sampled by the trigger edge of the second sampling clock signal CLK-16T connected to the clock control end of the fourth flip-flop D4, so that the first pulse signal / RD_80T outputted by the inverse output end of the fourth flip-flop D4 flips to 0. After that, the high level of the second pulse signal RD_64T is continuously sampled by three trigger edges of the second sampling clock signal CLK-16T; until the low level of the second pulse signal RD_64T is sampled by the trigger edge of the second sampling clock signal CLK-16T, so that the first pulse signal / RD_80T outputted by the inverse output end of the fourth flip-flop D4 flips to 1.

[0163] Due to the sequential response of the third flip-flop D3 and the fourth flip-flop D4 and their own delay, the starting time of the effective level of the first pulse signal / RD_80T lags behind the starting time of the effective level of the second pulse signal RD_64T, and the lag time is equal to one clock period 16T of the second sampling clock signal CLK-16T. And, the ending time of the effective level of the first pulse signal / RD_80T lags behind the ending time of the effective level of the second pulse signal RD_64T, and the lag time is equal to one clock period 16T of the second sampling clock signal CLK-16T. Therefore, the duration of the effective level of the first pulse signal / RD_80T is equal to the duration of the effective level of the second pulse signal RD_64T, which is equal to one clock period 64T of the third sampling clock signal.

[0164] Further, the time interval between the ending time of the effective level of the first pulse signal and the starting time of the effective level of the second pulse signal is one clock period of the second sampling clock signal plus one clock period of the third sampling clock signal (i.e. 64T+16T equals 80T). Wherein, the starting time of the effective level of the second pulse signal is the time when the effective level of the delayed read pulse signal RD_DLY is sampled by the trigger edge of the third sampling clock signal. Therefore, the lag time of the ending time of the effective level of the first pulse signal relative to the time when the delayed read pulse signal RD_DLY is sampled by the trigger edge of the third sampling clock signal is the superposition of the clock period of the second sampling clock signal and the clock period of the third sampling clock signal (i.e. 80T).

[0165] Further, if the delayed read pulse signal RD_DLY is low level effective, the second output unit can be added to the circuit shown in the figure, so that the functional effect of the second output unit is the same as described above. Figure 7 The circuit shown in the figure can be added with an inverter, so that the functional effect of the second output unit is the same as described above.

[0166] Based on the above analysis, it can be known that in the embodiment, the third flip-flop D3 and the fourth flip-flop D4 of the second output unit are used to make the continuous opening time length of the DLL circuit in the single read pulse signal scenario equal to the superposition of the clock period of the second sampling clock signal and the clock period of the third sampling clock signal.

[0167] Alternatively, the continuous opening time length of the DLL circuit of 96T can also be obtained by the third flip-flop D3 and the fourth flip-flop D4 superimposing the clock period 64T and the clock period 32T. The embodiment does not limit the clock periods of the two sampling clock signals superimposed, and the clock periods can be respectively set according to the required time length of the read operation completion.

[0168] In some embodiments, the required time length of the read operation completion is 75T. The continuous opening time length of the DLL circuit controlled by one sampling clock signal can be 128T, and the continuous opening time length of the DLL circuit controlled by two sampling clock signals can be 80T, which is beneficial to reduce power consumption.

[0169] In addition, in actual application, there is a certain lag between the input and the output of the flip-flop, which is reflected in the waveform diagram shown in FIG. 6. Figure 8 In the waveform diagram shown in FIG. 6, the rising edge of the second pulse signal RD_64T lags behind the trigger edge of the third sampling clock signal CLK-64T.

[0170] The second delay unit needs to have a reasonable delay time length to ensure that the effective level of the delayed read pulse signal RD_DLY can be sampled by the trigger edge of the third sampling clock signal CLK-64T connected to the clock control end of the third flip-flop D3.

[0171] Specifically, the second delay unit can be a delay element, and the delay time length of the second delay unit is the delay time length of the selected delay element. The second delay unit can also be composed of multiple delay elements connected in series, and the delay time length of the second delay unit is the sum of the delay time lengths of the multiple delay elements selected. Figure 7 In the embodiment shown in FIG. 5, the second delay unit includes the delay element A and the delay element B connected in series, and therefore, the superposition of the delay effects of the delay element A and the delay element B serves as the delay effect of the second delay unit.

[0172] The embodiment does not limit the number of delay element included in the second delay unit, as long as the delay effect of the second delay unit can make the effective level of the delayed read pulse signal RD_DLY be sampled by the first trigger edge of the third sampling clock signal CLK-64T.

[0173] Figure 7The scheme and effect of the master signal generation module, the slave signal generation module, the reset-set flip-flop, the feedback control module and the reset control module in the control circuit of the delay-locked loop circuit can refer to Embodiment One, and will not be described again.

[0174] The embodiment also provides a memory comprising the control circuit of the delay-locked loop circuit as described above.

[0175] The control circuit of the delay-locked loop circuit and the memory provided by the embodiment comprise: a signal conditioning module, which generates at least one sampling clock signal according to a first clock signal and generates a first pulse signal in combination with a read pulse signal; a master signal generation module, which generates a master signal according to the read pulse signal; a slave signal generation module, which generates a slave signal according to the first pulse signal; and an enable signal generation module, which generates an enable signal according to the master signal and the slave signal to turn on or turn off the delay-locked loop circuit; wherein the sampling clock signal controls a starting moment of an effective level of the first pulse signal; the read pulse signal controls a starting moment of an effective level of the master signal; the first pulse signal controls a starting moment of an effective level of the slave signal; and the master signal and the slave signal control a starting moment and an ending moment of an effective level of the enable signal, respectively. The disclosure controls the starting moment and the starting duration of the delay-locked loop based on the read pulse signal and the sampling clock signal, without setting a mode register, and optimizes the control circuit.

[0176] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. The disclosure is intended to cover any variations, uses or adaptive changes of the disclosure that follow the general principles of the disclosure and include known or customary practices in the art. The specification and examples are only regarded as illustrative, and the true scope and spirit of the disclosure are indicated by the following claims.

[0177] It should be understood that the disclosure is not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the disclosure is limited only by the appended claims.

Claims

1. A control circuit for a delay phase-locked loop circuit, characterized in that, include: Signal conditioning module, main signal generation module, slave signal generation module, enable signal generation module; The signal conditioning module receives a first clock signal and a read pulse signal, and is used to generate at least one sampling clock signal based on the first clock signal, and to generate and output a first pulse signal based on the at least one sampling clock signal and the read pulse signal; The main signal generation module receives the read pulse signal and is used to generate and output a main signal based on the read pulse signal; The slave signal generation module is connected to the signal conditioning module and is used to generate and output a slave signal based on the received first pulse signal; The enable signal generation module is connected to the main signal generation module and the slave signal generation module, and is used to generate and output an enable signal based on the received main signal and the slave signal. The enable signal is used to turn the delay phase-locked loop circuit on or off.

2. The control circuit according to claim 1, characterized in that, The signal conditioning module is used to determine the start time of the effective level of the first pulse signal based on the at least one sampling clock signal; The main signal generation module is used to control the start and end times of the effective level of the main signal according to the read pulse signal; The slave signal generation module is used to control and determine the start time of the effective level of the slave signal based on the first pulse signal; The enable signal generation module is used to determine the start time of the effective level of the enable signal based on the master signal and the end time of the effective level of the enable signal based on the slave signal.

3. The control circuit according to claim 1, characterized in that, The number of the at least one sampling clock signal is one; the signal conditioning module includes a first conditioning unit and a first output unit; The input terminal of the first adjustment unit receives the first clock signal and is used to generate and output a first sampling clock signal based on the first clock signal, wherein the clock period of the first sampling clock signal is T1; The first input terminal of the first output unit receives the first sampling clock signal, and the second input terminal of the first output unit receives the read pulse signal; the first output unit is used to sample the read pulse signal based on the first sampling clock signal, generate and output the first pulse signal. Wherein, the start time of the effective level of the first pulse signal is the moment when the reading pulse signal is at an effective level after the trigger edge of the first sampling clock signal is sampled; the duration of the effective level of the first pulse signal is one clock cycle T1 of the first sampling clock signal.

4. The control circuit according to claim 3, characterized in that, The first adjustment unit includes a plurality of cascaded first triggers; The clock control terminal of the first flip-flop serves as the input terminal of the first adjustment unit, receiving the first clock signal; The inverted output of the first flip-flop in each stage is connected to its own input. Except for the first first flip-flop, the clock control terminals of all other first flip-flops are connected to the positive output terminal of the previous stage flip-flop. The first sampling clock signal is output at the positive output terminal of the first flip-flop in the last stage.

5. The control circuit according to claim 3, characterized in that, The first output unit includes a first delay unit and a second flip-flop; The input terminal of the first delay unit serves as the second input terminal of the first output unit, receiving the read pulse signal; The first delay unit is used to generate and output the delayed read pulse signal; The input of the second flip-flop is connected to the delayed read pulse signal; The clock control terminal of the second flip-flop serves as the first input terminal of the first output unit, receiving the first sampling clock signal; The inverted output terminal of the second flip-flop outputs the first pulse signal; The second trigger is used to sample the delayed read pulse signal based on the first sampling clock signal.

6. The control circuit according to claim 1, characterized in that, The number of the at least one sampling clock signal is two; the signal conditioning module includes a second conditioning unit, a third conditioning unit, and a second output unit; The input terminal of the second adjustment unit receives the first clock signal and is used to generate and output a second sampling clock signal based on the first clock signal, wherein the clock period of the second sampling clock signal is T2; The input terminal of the third adjustment unit receives the second sampling clock signal and is used to generate and output a third sampling clock signal based on the second sampling clock signal, wherein the clock period of the third sampling clock signal is T3; The first input terminal of the second output unit receives the second sampling clock signal, the second input terminal of the second output unit receives the third sampling clock signal, and the third input terminal of the second output unit receives the read pulse signal; the second output unit is used to sample the read pulse signal based on the third sampling clock signal to generate and output a second pulse signal, and to sample the second pulse signal based on the second sampling clock signal to generate and output a first pulse signal; Wherein, the effective level of the second pulse signal begins at the moment when the trigger edge of the third sampling clock signal samples the read pulse signal at an effective level; the effective level of the second pulse signal is maintained for one clock cycle T3 of the third sampling clock signal; the effective level of the first pulse signal begins at the moment when the trigger edge of the second sampling clock signal first samples the second pulse signal at an effective level; the effective level of the first pulse signal is maintained for one clock cycle T3 of the third sampling clock signal.

7. The control circuit according to claim 6, characterized in that, The second output unit includes a second delay unit, a third flip-flop, and a fourth flip-flop; The input terminal of the second delay unit serves as the third input terminal of the second output unit, receiving the read pulse signal; The second delay unit is used to generate and output the delayed read pulse signal; The input terminal of the third trigger receives the delayed read pulse signal; The clock control terminal of the third flip-flop serves as the first input terminal of the second output unit, receiving the third sampling clock signal; The second pulse signal is output at the non-inverting output terminal of the third flip-flop; The third trigger is used to sample the delayed read pulse signal based on the third sampling clock signal; The input terminal of the fourth flip-flop receives the second pulse signal; The clock control terminal of the fourth flip-flop serves as the second input terminal of the second output unit, receiving the second sampling clock signal, and the inverted output terminal of the fourth flip-flop outputs the first pulse signal. The fourth flip-flop is used to sample the second pulse signal based on the second sampling clock signal.

8. The control circuit according to claim 6, characterized in that, The second adjustment unit includes multiple cascaded fifth triggers; The clock control terminal of the first fifth flip-flop serves as the input terminal of the second adjustment unit, receiving the first clock signal; The inverted output of the fifth flip-flop in each stage is connected to its own input. Except for the first fifth flip-flop, the clock control terminals of all other fifth flip-flops are connected to the positive output terminal of the previous fifth flip-flop. The second sampling clock signal is output at the non-inverting output of the fifth flip-flop in the final stage.

9. The control circuit according to claim 6, characterized in that, The third adjustment unit includes multiple cascaded sixth triggers; The clock control terminal of the first sixth flip-flop serves as the input terminal of the third adjustment unit, receiving the second sampling clock signal; The inverted output of the sixth flip-flop in each stage is connected to its own input. Except for the first sixth flip-flop, the clock control terminals of all other sixth flip-flops are connected to the positive output terminal of the previous sixth flip-flop. The third sampling clock signal is output at the positive output terminal of the last sixth flip-flop.

10. The control circuit according to claim 1, characterized in that, The signal generation module includes a third delay unit, a first inverter, and a first NAND gate; The first input terminal of the first NAND gate serves as the input terminal of the slave signal generation module, receiving the first pulse signal; the input terminal of the third delay unit is connected to the first input terminal of the first NAND gate; the output terminal of the third delay unit is connected to the input terminal of the first inverter; the output terminal of the first inverter is connected to the second input terminal of the first NAND gate; and the output terminal of the first NAND gate outputs the slave signal.

11. The control circuit according to claim 1, characterized in that, The main signal generation module includes a second inverter; The input terminal of the second inverter is used to receive the read pulse signal, and the output terminal of the second inverter is used to output the main signal.

12. The control circuit according to claim 1, characterized in that, The main signal generation module includes a third inverter and a first OR gate; The first input terminal of the first OR gate receives the read pulse signal, and the second input terminal of the first OR gate receives an activation pulse signal; wherein the activation pulse signal is generated before the read pulse signal; The output of the first OR gate is connected to the input of the third inverter, and the output of the third inverter is used to output the main signal.

13. The control circuit according to claim 1, characterized in that, The enable signal generation module includes a reset-set flip-flop; the reset-set flip-flop includes a second NAND gate and a third NAND gate; The first input terminal of the second NAND gate serves as the first input terminal of the enable signal generation module, receiving the main signal; the second input terminal of the second NAND gate is connected to the output terminal of the third NAND gate. The second input terminal of the third NAND gate serves as the second input terminal of the enable signal generation module, receiving the slave signal; the first input terminal of the third NAND gate is connected to the output terminal of the second NAND gate; the output terminal of the second NAND gate serves as the output terminal of the enable signal generation module, outputting the enable signal. The reset terminal of the third NAND gate is connected to a first reset signal, which is used to indicate that the reset-set trigger is reset.

14. The control circuit according to any one of claims 1-13, characterized in that, The control circuit also includes a reset control module; The first input terminal of the reset control module receives the read pulse signal, and the second input terminal of the reset control module receives the second reset signal; The reset control module is used to generate and output a reset control signal based on the read pulse signal and the second reset signal; wherein the reset control signal is connected to the reset terminal of the signal conditioning module and is used to instruct the signal conditioning module to reset.

15. The control circuit according to claim 14, characterized in that, The reset control module includes a fourth NAND gate, a fourth delay unit, a fourth inverter, a fifth NAND gate, and a fifth inverter; The first input terminal of the fourth NAND gate serves as the first input terminal of the reset control module, receiving the read pulse signal; The input terminal of the fourth delay unit is connected to the first input terminal of the fourth NAND gate; the output terminal of the fourth delay unit is connected to the input terminal of the fourth inverter; the output terminal of the fourth inverter is connected to the second input terminal of the fourth NAND gate; the output terminal of the fourth NAND gate is connected to the second input terminal of the fifth NAND gate. The first input terminal of the fifth NAND gate serves as the second input terminal of the reset control module, receiving the second reset signal; the output terminal of the fifth NAND gate is connected to the input terminal of the fifth inverter; the output terminal of the fifth inverter serves as the output terminal of the reset control module, outputting the reset control signal.

16. The control circuit according to claim 1, characterized in that, The control circuit also includes a feedback control module; The first input terminal of the feedback control module receives the enable signal, the second input terminal of the feedback control module receives the internal clock signal, and the output terminal of the feedback control module outputs the first clock signal; wherein, the clock period of the internal clock signal is the same as the clock period of the first clock signal; the feedback control module is used to control whether the signal conditioning module receives the first clock signal based on the enable signal.

17. The control circuit according to claim 16, characterized in that, The feedback control module includes: a sixth NAND gate, a fifth delay unit, and a sixth inverter; The first input terminal of the sixth NAND gate serves as the first input terminal of the feedback control module, receiving the enable signal; the second input terminal of the sixth NAND gate serves as the second input terminal of the feedback control module, receiving the internal clock signal; the output terminal of the sixth NAND gate is connected to the input terminal of the fifth delay unit; the output terminal of the fifth delay unit is connected to the input terminal of the sixth inverter; the output terminal of the sixth inverter serves as the output terminal of the feedback control module, outputting the first clock signal.

18. A memory, characterized in that, The control circuit includes the delay phase-locked loop circuit as described in any one of claims 1-17.

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