A HEMT device based on dual-threshold coupling of gate dielectric and its manufacturing method

Abstract

The present invention relates to a HEMT device based on dual-threshold coupling of a gate dielectric and a preparation method thereof. The method includes: preparing an epitaxial substrate, which sequentially includes a substrate layer, a nucleation layer, a buffer layer, and a barrier layer from bottom to top; fabricating a source electrode and a drain electrode on the buffer layer; fabricating an electrically isolated region of an active region on the barrier layer; growing a dielectric layer on the source electrode, the drain electrode, and the barrier layer; fabricating a gate electrode in a preset combined groove of the dielectric layer, wherein the gate electrode is located between the source electrode and the drain electrode, and the preset combined groove is formed by a combination of a plurality of grooves arranged at intervals in the dielectric layer along the gate width direction; photolithographing a metal interconnection region on the source electrode and the drain electrode in a metal interconnection opening region and the dielectric layer that is not etched by opening, so as to form a metal interconnection layer by evaporation. The barrier layer of the present invention is completely protected by the dielectric layer, thereby avoiding the degradation of the electrical performance of the device caused by etching damage.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and relates to a GaN-based HEMT device with dual-threshold coupling based on a gate dielectric and a preparation method thereof. Background Art

[0002] In recent years, gallium nitride-based high electron mobility transistors (HEMTs) have emerged as a new generation of solid-state microwave power devices. They possess a high two-dimensional electron gas density and high electron mobility, enabling the generation of high output currents, achieving low on-resistance, and high transconductance, thereby facilitating high operating frequencies and power-added efficiencies. These electrical characteristics endow GaN-based HEMT devices with broad application prospects in the communication field and make them core electronic devices driving the development of mobile communication base station technology. For communication systems, GaN-based HEMT devices also need to address the linearity issue. To date, GaN-based HEMTs have mainly focused on output power, efficiency, and operating frequency. However, the linearity problem caused by the non-linear characteristics of GaN devices has always been the biggest obstacle hindering the development of communication systems. To better improve the linearity of devices, extensive research has been conducted in recent years. Maintaining the peak value of the transconductance within a wide gate voltage range is a fundamental requirement for high-linearity devices. Currently, many methods for adjusting the transconductance flatness have been reported. They mainly include: gate recess technology, tapered gate recess technology (TRG), and Fin structure. However, all three of these technologies have some drawbacks in fabricating high-performance HEMT devices, resulting in unsatisfactory device performance.

[0003] In 2009, Eldad Bahat-Treidel et al. proposed using gate recess technology to change the transconductance value of devices and paralleling two or more device units with different gate recess depths. Due to different recess depths, the control ability of the gate over the channel varies, thereby generating different transconductance distributions. Their superposition will produce a more flat transconductance distribution with a good transconductance peak, thus improving the linearity of the device. However, during the recess etching process, the damage introduced by plasma etching in the area under the gate will introduce interface states, leading to an increase in gate leakage current and causing device efficiency degradation.

[0004] The graded groove gate technology is an innovative method to improve linearity. It is equivalent to combining multiple device units with different gate groove depths in a gradually changing manner from deep to shallow to achieve linearity improvement. On the one hand, this structure can improve the gate control ability of the device by adjusting the distance between the gate and the channel. On the other hand, different barrier layer thicknesses can be obtained at different positions, and the turn-on voltages of each device unit are different and approximately continuous. When the transconductance value of the previous device unit decreases, the transconductance value of the next device unit increases, so as to maintain the total transconductance curve at the peak level within a wide gate voltage range. All in all, this technology combines the advantages of different barrier layer thicknesses and gate groove technologies to achieve the maximum flattening of the transconductance curve. However, for the graded groove structure, Cl-based plasma etching will generate a high density of trap states, causing a series of problems such as device threshold voltage drift, current collapse, and device reliability. In addition, it is difficult to precisely control the graded groove depth, which requires high etching technology and increases the complexity of the process.

[0005] Using the Fin structure to improve the linearity of the device, by paralleling devices with different Fin widths, different threshold turn-ons of the device are realized, thereby improving the linearity of the device. This technology transforms the device from a planar structure to a three-dimensional structure, increasing the area controlled by the gate, improving the gate control ability of the device, and weakening the short-channel effect. However, during the etching process of the Fin structure, inevitable large etching damage will be generated, and the interface state problems caused by these damages cannot be completely removed, thus bringing serious problems to the gate reliability of the device; at the same time, etching will release the lattice stress at the AlGaN / GaN heterojunction interface, reducing the two-dimensional electron gas concentration and resulting in a decrease in the output current of the device. In addition, the Fin structure will cause a decrease in the current drive ability under the same gate width, resulting in the degradation of the device output power and seriously affecting the working characteristics of the device.

[0006] In summary, all these three technologies involve the etching of heterojunction materials during the device preparation process, so etching damage is inevitably generated. In addition, after the material is etched, the ratio of the constituent elements of the material will be mismatched. For GaN materials, after Cl-based ICP etching, the ratio of Ga and N on the material surface will change significantly, the content of N will decrease significantly, a large number of N vacancies will be formed, resulting in an increase in leakage current and a decrease in breakdown voltage. The more serious the etching damage, the greater the reverse leakage of the Schottky, and the barrier height and ideality factor will be affected. Summary of the Invention

[0007] To solve the above problems existing in the prior art, the present invention provides a HEMT device based on dual-threshold coupling of gate dielectrics and its manufacturing method. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0008] An embodiment of the present invention provides a preparation method of a HEMT device based on dual-threshold coupling of a gate dielectric, including the following steps:

[0009] Prepare an epitaxial substrate, which sequentially includes a substrate layer, a nucleation layer, a buffer layer, and a barrier layer from bottom to top;

[0010] Fabricate a source electrode and a drain electrode on the buffer layer;

[0011] Fabricate an electrically isolated region of the active region on the barrier layer;

[0012] Grow a dielectric layer on the source electrode, the drain electrode, and the barrier layer;

[0013] Fabricate a gate electrode in a preset combined groove of the dielectric layer, where the gate electrode is located between the source electrode and the drain electrode, and the preset combined groove is composed of a plurality of grooves arranged at intervals in the dielectric layer along the gate width direction;

[0014] Lithograph a metal interconnect region on the source electrode and the drain electrode in the metal interconnect opening region and the dielectric layer that is not etched by opening, so as to evaporate and form a metal interconnect layer.

[0015] In an embodiment of the present invention, the material of the buffer layer is GaN, and the material of the barrier layer includes one of AlGaN, InAlN, and AlN.

[0016] In an embodiment of the present invention, fabricating a source electrode and a drain electrode on the buffer layer includes:

[0017] Lithograph a source electrode region and a drain electrode region on the barrier layer;

[0018] Fabricate the source electrode and the drain electrode in the source electrode region and the drain electrode region respectively;

[0019] Use an annealing process to sink the source electrode and the drain electrode into the buffer layer to complete the fabrication of the source electrode and the drain electrode.

[0020] In an embodiment of the present invention, fabricating an electrically isolated region of the active region on the barrier layer includes:

[0021] Lithograph an electrically isolated region on the barrier layer;

[0022] Etch the barrier layer of the electrically isolated region and a part of the depth of the buffer layer to form the electrically isolated region of the active region.

[0023] In an embodiment of the present invention, growing a dielectric layer on the barrier layer includes:

[0024] A dielectric layer is grown on the barrier layer by using the PECVD process.

[0025] In one embodiment of the present invention, fabricating a gate electrode on a preset combined groove of the dielectric layer includes:

[0026] Photolithographing a preset combined groove area on the dielectric layer;

[0027] Etching the dielectric layer within the preset combined groove area to form a preset combined groove;

[0028] Photolithographing a gate electrode area within all grooves of the preset combined groove to fabricate the gate electrode within the gate electrode area.

[0029] In one embodiment of the present invention, the depth of all grooves of the preset combined groove is equal to the thickness of the dielectric layer, or the depth of all grooves of the preset combined groove increases successively along the gate width direction.

[0030] In one embodiment of the present invention, photolithographing a metal interconnect area on the source electrode and the drain electrode in the metal interconnect opening area and the dielectric layer that is not etched with openings to evaporate and form a metal interconnect layer includes:

[0031] Photolithographing a metal interconnect opening area on the dielectric layer of the source electrode and the drain electrode;

[0032] Using an etching process to remove the dielectric layer within the metal interconnect opening area to expose the source electrode and the drain electrode within the metal interconnect opening area;

[0033] Photolithographing a metal interconnect area on the source electrode and the drain electrode within the metal interconnect opening area and the dielectric layer that is not etched with openings;

[0034] Evaporating and forming a metal interconnect layer on the source electrode and the drain electrode within the metal interconnect area and the dielectric layer.

[0035] In one embodiment of the present invention, the source electrode and the drain electrode are a metal stack structure composed of Ti, Al, Ni, and Au from bottom to top, the gate electrode is a metal stack structure composed of Ni, Au, and Ni from bottom to top, and the metal interconnect layer is a metal stack structure composed of Ti and Au from bottom to top.

[0036] Another embodiment of the present invention provides a HEMT device based on dual-threshold coupling of a gate dielectric. The HEMT device is fabricated by using the preparation method of the HEMT device based on dual-threshold coupling of a gate dielectric described in any one of the above embodiments. The HEMT device includes:

[0037] An epitaxial substrate, which sequentially includes a substrate layer, a nucleation layer, a buffer layer, and a barrier layer from bottom to top;

[0038] A source electrode, located at one end of the buffer layer;

[0039] A drain electrode, located at the other end of the buffer layer;

[0040] An electrical isolation layer, located on the barrier layer in the active region;

[0041] A dielectric layer, located on the barrier layer, the source electrode, and the drain electrode. Among them, a plurality of grooves arranged at intervals are provided in the dielectric layer along the gate width direction;

[0042] A gate electrode, located in a plurality of grooves arranged at intervals in the dielectric layer along the gate width direction;

[0043] A metal interconnection layer, located on the source electrode, the drain electrode, and the dielectric layer in the metal interconnection region.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0045] Since during the entire preparation process, the barrier layer of the present invention is completely protected by the dielectric layer, the degradation of the electrical performance of the device caused by etching damage is avoided. The solution of the present invention solves the problem of linearity in the application of GaN-based HEMT devices in the communication field, and is easy to implement in terms of process preparation, overcoming a series of problems caused by etching damage in the prior art.

[0046] Through the following detailed description with reference to the accompanying drawings, other aspects and features of the present invention become apparent. However, it should be understood that the drawings are designed only for the purpose of explanation and not as a limitation of the scope of the present invention, because it should refer to the appended claims. It should also be understood that, unless otherwise indicated, the drawings are not necessarily drawn to scale, and they are only intended to conceptually illustrate the structures and processes described herein. Description of the Drawings

[0047] Figure 1 It is a schematic flow chart of a preparation method of a HEMT device based on dual-threshold coupling of gate dielectric provided by an embodiment of the present invention;

[0048] Figure 2 It is a schematic structural diagram of a HEMT device based on dual-threshold coupling of gate dielectric provided by an embodiment of the present invention;

[0049] Figure 3 It is a main cross-sectional view of a HEMT device based on dual-threshold coupling of gate dielectric provided by an embodiment of the present invention;

[0050] Figure 4A side cross-sectional view of the structure of a HEMT device based on dual-threshold coupling of a gate dielectric provided by an embodiment of the present invention;

[0051] Figure 5 A top view of a HEMT device based on dual-threshold coupling of a gate dielectric provided by an embodiment of the present invention. Specific embodiments

[0052] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0053] Embodiment 1

[0054] Please refer to Figures 1 to 5 , Figure 1 A schematic flow chart of a preparation method of a HEMT device based on dual-threshold coupling of a gate dielectric provided by an embodiment of the present invention, Figure 2 A schematic structural diagram of a HEMT device based on dual-threshold coupling of a gate dielectric provided by an embodiment of the present invention, Figure 3 A front cross-sectional view of a HEMT device based on dual-threshold coupling of a gate dielectric provided by an embodiment of the present invention, Figure 4 A side cross-sectional view of the structure of a HEMT device based on dual-threshold coupling of a gate dielectric provided by an embodiment of the present invention, Figure 5 A top view of a HEMT device based on dual-threshold coupling of a gate dielectric provided by an embodiment of the present invention. The present invention provides a preparation method of a HEMT device based on dual-threshold coupling of a gate dielectric, and the preparation method includes the following steps:

[0055] Step 1: Prepare an epitaxial substrate, which sequentially includes a substrate layer (Substrate), a nucleation layer (Nuclear layer), a buffer layer (buffer), and a barrier layer (barrier) from bottom to top.

[0056] Preferably, the material of the substrate layer includes one of sapphire, SiC, and Si.

[0057] Preferably, the material of the nucleation layer includes AlN.

[0058] Preferably, the material of the buffer layer is GaN.

[0059] Preferably, the material of the barrier layer includes one of AlGaN, InAlN, and AlN.

[0060] Step 2: Fabricate a source electrode (S) and a drain electrode (D) on the buffer layer.

[0061] Step 2.1: Lithograph the source electrode region and the drain electrode region on the barrier layer.

[0062] Step 2.11: Place the epitaxial substrate on a hot plate for baking.

[0063] Specifically, place the epitaxial substrate on a hot plate at 200 °C for 5 min.

[0064] Step 2.12: Apply a lift-off resist on the barrier layer and place the sample on a hot plate for baking.

[0065] Specifically, apply a lift-off resist on the barrier layer with a spin-coated thickness of 0.35 μm, and place the sample on a hot plate at 200 °C for 5 min.

[0066] Step 2.13: Apply and spin a photoresist on the lift-off resist and place the sample on a hot plate for baking.

[0067] Specifically, apply and spin a photoresist on the lift-off resist with a spin-coated thickness of 0.77 μm, and place the sample on a hot plate at 90 °C for 1 min.

[0068] Step 2.14: Place the sample with the applied and spun photoresist into a lithography machine to expose the coated surface. Then, place the exposed sample into a developer to remove the photoresist and lift-off resist, and then rinse it with ultrapure water and dry it with nitrogen to form the source electrode region and the drain electrode region.

[0069] Step 2.2: Fabricate the source electrode and the drain electrode in the source electrode region and the drain electrode region respectively.

[0070] Step 2.21: Place the sample with the photolithography patterns of the source electrode and the drain electrode into a plasma asher for bottom film treatment.

[0071] Preferably, the time for bottom film treatment is 5 min.

[0072] Step 2.22: Place the sample into an electron beam evaporation chamber and evaporate ohmic metal on the barrier layer within the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form the source electrode and the drain electrode.

[0073] Preferably, the source electrode and the drain electrode are a metal stack structure composed of four layers of metals: Ti, Al, Ni, and Au from bottom to top.

[0074] Step 2.23: Strip the sample after the ohmic metal evaporation to remove the ohmic metal, photoresist, and lift-off resist outside the source electrode and the drain electrode, and then rinse the sample with ultrapure water and dry it with nitrogen.

[0075] Step 2.3: Use an annealing process to sink the source electrode and the drain electrode into the buffer layer to complete the fabrication of the source electrode and the drain electrode.

[0076] Specifically, the sample after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing treatment, so that the ohmic metal on the barrier layer in the source electrode and the drain electrode sinks to the buffer layer, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel.

[0077] Preferably, the process conditions for annealing are: the annealing atmosphere is N2, the annealing temperature is 830 °C, and the annealing time is 30 s.

[0078] Step 3: Fabricate an electrically isolated region of the active region on the barrier layer.

[0079] Step 3.1: Photolithograph the electrically isolated region on the barrier layer.

[0080] Step 3.11: Bake the sample on a hot plate.

[0081] Specifically, bake the sample on a hot plate at 200 °C for 5 min.

[0082] Step 3.12: Apply and spin coat the photoresist, and bake the sample on a hot plate.

[0083] Specifically, apply and spin coat the photoresist, with a spin coating speed of 3500 rpm, and bake the sample on a hot plate at 90 °C for 1 min.

[0084] Step 3.13: Place the sample in a lithography machine to expose the photoresist in the electrically isolated region, then place the exposed sample in a developer to remove the photoresist in the electrically isolated region, and rinse it with ultrapure water and dry it with nitrogen.

[0085] Step 3.2: Etch the barrier layer and a part of the buffer layer with a certain depth in the electrically isolated region to form an electrically isolated region of the active region, where the electrically isolated region is located on one side of the source electrode away from the drain electrode and on one side of the drain electrode away from the source electrode.

[0086] Step 3.21: Use the ICP (Inductively Coupled Plasma) process to etch the barrier layer and a part of the buffer layer with a certain depth in the electrically isolated region in sequence to achieve mesa isolation of the active region.

[0087] Preferably, the total etching depth is 100 nm.

[0088] Step 3.22: Place the sample in acetone solution, stripping solution, acetone solution and ethanol solution in sequence for cleaning to remove the photoresist outside the electrically isolated region, then rinse the sample with ultrapure water and dry it with nitrogen.

[0089] Step 4: Grow a dielectric layer on the source electrode, the drain electrode and the barrier layer.

[0090] Step 4.1: Perform surface cleaning on the sample that has completed electrical isolation of the active region.

[0091] Step 4.11: Place the sample in an acetone solution for ultrasonic cleaning.

[0092] Specifically, place the sample in an acetone solution for ultrasonic cleaning for 3 minutes, with an ultrasonic intensity of 2.5.

[0093] Step 4.12: Place the sample in a stripping solution for water bath heating.

[0094] Specifically, place the sample in a stripping solution at 60 °C for water bath heating for 15 minutes.

[0095] Step 4.13: Place the sample in an acetone solution and an ethanol solution in sequence for ultrasonic cleaning.

[0096] Specifically, place the sample in an acetone solution and an ethanol solution in sequence for ultrasonic cleaning for 3 minutes, with an ultrasonic intensity of 2.5.

[0097] Step 4.14: Rinse the sample with ultrapure water and dry it with nitrogen.

[0098] Step 4.2: Use the PECVD (Plasma Enhanced Chemical Vapor Deposition) process to grow a dielectric layer on the source electrode, drain electrode, and barrier layer.

[0099] Preferably, the thickness of the dielectric layer is 5 nm - 10 nm.

[0100] Preferably, the material of the dielectric layer includes one of SiN, SiO2, Al2O3, and AlN.

[0101] Step 5: Fabricate a gate electrode in the preset combined grooves of the dielectric layer, where the gate electrode is located between the source electrode and the drain electrode, and the preset combined grooves are composed of a plurality of grooves arranged at intervals in the dielectric layer along the gate width direction (the width direction of the gate electrode).

[0102] Step 5.1: Lithograph the area of the preset combined grooves on the dielectric layer.

[0103] Step 5.11: Bake the sample on a hot plate.

[0104] Specifically, bake the sample on a hot plate at 200 °C for 5 minutes.

[0105] Step 5.12: Apply and spin the photoresist, and bake the sample on a hot plate.

[0106] Specifically, spin coating and spin drying of photoresist are carried out, with a spin drying speed of 3500 rpm, and the sample is baked on a hot plate at 90 °C for 1 min.

[0107] Step 5.13: Place the sample in a lithography machine and expose the photoresist within the preset combined groove area (i.e., the arrayed groove area).

[0108] Step 5.14: Place the exposed sample in a developer to remove the photoresist within the preset combined groove area, and then rinse it with ultrapure water and dry it with nitrogen.

[0109] Step 5.2: Etch the dielectric layer within the preset combined groove area to form a preset combined groove.

[0110] Preferably, the depth of all grooves in the preset combined groove is equal to the thickness of the dielectric layer, or the depth of all grooves in the preset combined groove increases successively along the gate width direction.

[0111] Use the ICP etching process to remove the dielectric layer within the preset combined groove area.

[0112] Preferably, the etching conditions are as follows: the reaction gas is CF4 or O2, the reaction chamber pressure is 10 mTorr, and the RF powers of the upper electrode and the lower electrode are 100 W and 10 W respectively.

[0113] Step 5.3: Lithograph the gate electrode area within all grooves of the preset combined groove to fabricate a gate electrode (G) within the gate electrode area.

[0114] Step 5.31: Lithograph the gate electrode area within the preset combined groove area.

[0115] Step 5.311: Place the sample on a hot plate for baking.

[0116] Specifically, place the sample on a hot plate at 200 °C for 5 min.

[0117] Step 5.312: Spin coat and spin dry the stripping glue on the dielectric layer outside the preset combined groove area, and then place the sample on a hot plate for baking.

[0118] Specifically, spin coat and spin dry the stripping glue on the dielectric layer outside the preset combined groove area, with a spin drying thickness of 0.35 μm, and then place the sample on a hot plate at 200 °C for 5 min.

[0119] Step 5.313: Spin coat and spin dry the photoresist on the stripping glue, and then place the sample on a hot plate for baking.

[0120] Specifically, photoresist is spin-coated and spun on the stripping glue, and the thickness of the spun photoresist is 0.77 μm. Then the sample is baked on a hot plate at 90 °C for 1 min.

[0121] Step 5.314: Place the sample with the spin-coated and spun photoresist into a lithography machine to expose the photoresist in the gate electrode region.

[0122] Step 5.315: Place the exposed sample into a developer to remove the photoresist and stripping glue in the gate electrode region, and then rinse it with ultrapure water and dry it with nitrogen.

[0123] Step 5.32: Evaporate the gate electrode in the gate electrode region.

[0124] Step 5.321: Place the sample with the gate electrode lithography pattern into a plasma asher for bottom film treatment.

[0125] Preferably, the time for bottom film treatment is 5 min.

[0126] Step 5.322: Place the sample into an electron beam evaporation system. After the vacuum degree of the reaction chamber of the electron beam evaporation system reaches 2×10 -6 Torr, evaporate the gate metal on the photoresist inside and outside the gate electrode region.

[0127] Step 5.323: Strip the sample after the gate metal evaporation to remove the gate metal, photoresist and stripping glue outside the gate electrode region. After rinsing the sample with ultrapure water and drying it with nitrogen, the gate electrode is formed.

[0128] Preferably, the gate electrode is a metal stack structure composed of three layers of metals, Ni, Au and Ni from bottom to top.

[0129] Step 6: Lithograph the metal interconnection region on the source electrode, drain electrode in the metal interconnection opening region and the unetched dielectric layer to evaporate and form the metal interconnection layer.

[0130] Step 6.1: Lithograph the metal interconnection opening region on the dielectric layer of the source electrode and drain electrode.

[0131] Step 6.11: Bake the sample on a hot plate.

[0132] Specifically, bake the sample on a hot plate at 200 °C for 5 min.

[0133] Step 6.12: Spin-coat and spin the photoresist, and then bake the sample on a hot plate.

[0134] Specifically, spin-coat and spin the photoresist at a spinning speed of 3500 rpm, and then bake the sample on a hot plate at 90 °C for 1 min.

[0135] Step 6.13: Place the sample in a lithography machine to expose the photoresist in the metal interconnect via area.

[0136] Step 6.14: Place the exposed sample in a developer to remove the photoresist in the metal interconnect via area, and then rinse it with ultrapure water and dry it with nitrogen.

[0137] Step 6.2: Use an etching process to remove the dielectric layer in the metal interconnect via area to expose the source and drain electrodes in the metal interconnect via area.

[0138] Specifically, use an ICP etching process to remove the dielectric layer in the metal interconnect via area.

[0139] Preferably, the reaction gas is CF4 or O2, the reaction chamber pressure is 10 mTorr, and the RF powers of the upper and lower electrodes are 100 W and 10 W respectively.

[0140] Step 6.3: Lithograph the metal interconnect area on the source and drain electrodes in the metal interconnect via area and the unetched dielectric layer.

[0141] Step 6.31: Place the sample after metal interconnect via etching on a hot plate for baking.

[0142] Specifically, place the sample after metal interconnect via etching on a 200 °C hot plate for 5 minutes.

[0143] Step 6.32: Apply and spin the lift-off resist on the source and drain electrodes in the metal interconnect via area and the unetched dielectric layer, and then place the sample on a hot plate for baking.

[0144] Specifically, apply and spin the lift-off resist on the source and drain electrodes in the metal interconnect via area and the unetched dielectric layer, with a spin coating thickness of 0.35 μm, and then place the sample on a 200 °C hot plate for 5 minutes.

[0145] Step 6.33: Apply and spin the photoresist on the lift-off resist, and then place the sample on a hot plate for baking.

[0146] Specifically, apply and spin the photoresist on the lift-off resist, with a spin coating thickness of 0.77 μm, and then place the sample on a 90 °C hot plate for 1 minute.

[0147] Step 6.34: Place the sample after applying and spinning the photoresist in a lithography machine to expose the photoresist in the metal interconnect area, then place the exposed sample in a developer to remove the photoresist and lift-off resist in the metal interconnect area, and then rinse it with ultrapure water and dry it with nitrogen.

[0148] Step 6.4: Evaporate a metal interconnect layer on the source electrode, drain electrode within the metal interconnect region, and the dielectric layer.

[0149] Step 6.41: Place the sample with the metal interconnect region into a plasma asher for bottom film treatment.

[0150] Preferably, the time for bottom film treatment is 5 min.

[0151] Step 6.42: Place the sample into an electron beam evaporation chamber. After the vacuum degree of the reaction chamber of the electron beam evaporation chamber reaches 2×10 -6 Torr, evaporate interconnect metal on the source electrode, drain electrode, and dielectric layer within the metal interconnect region, and on the photoresist outside the metal interconnect region to form a metal interconnect layer for electrode lead-out.

[0152] Preferably, the metal interconnect layer is a metal stack structure composed of two layers of metal, Ti and Au, from bottom to top.

[0153] Step 6.43: Strip the sample after the evaporation of interconnect metal to remove the metal, photoresist, and stripping glue outside the metal interconnect layer region. Rinse the sample with ultrapure water and dry it with nitrogen to complete the device fabrication.

[0154] The present invention avoids the etching of the GaN heterojunction barrier layer. That is, a dielectric layer is first grown on the barrier layer, and then the coupled plasma etching technology is used to etch specific regions of the dielectric layer along the gate width direction. The dielectric layer under the gate in the etched region is etched away, and the gate electrode is in direct contact with the barrier layer, while in the unetched region, there is a thicker dielectric layer between the gate electrode and the barrier layer, which makes the control ability of the gate electrode on the channel different in different regions, thus forming different threshold voltages in different regions. According to the application requirements, two or more device units are connected in parallel to achieve the gradual turn-on of different devices along the gate width direction, improving the flatness of the transconductance.

[0155] The present invention ensures that there is a certain thickness of dielectric layer under the previously unetched region, and etches the unetched region to different depths, so that the thickness of the dielectric layer under the gate in different regions is different, and different etching depths correspond to different threshold voltages, so that the device can have a wider gate voltage swing.

[0156] Embodiment 2

[0157] Please refer to Figures 2 to 5 , Figure 2 which is a schematic structural diagram of a HEMT device based on dual-threshold coupling of gate dielectrics provided by an embodiment of the present invention, Figure 3 which is a main cross-sectional view of a HEMT device based on dual-threshold coupling of gate dielectrics provided by an embodiment of the present invention, Figure 4A side cross-sectional view of the structure of a HEMT device based on dual-threshold coupling of a gate dielectric provided by an embodiment of the present invention. Figure 5 A top view of a HEMT device based on dual-threshold coupling of a gate dielectric provided by an embodiment of the present invention. Based on the above embodiments, the present invention further provides a HEMT device based on dual-threshold coupling of a gate dielectric. The HEMT device based on dual-threshold coupling of a gate dielectric is prepared by the preparation method of the HEMT device based on dual-threshold coupling of a gate dielectric described in the above embodiments. The HEMT device includes:

[0158] An epitaxial substrate, which sequentially includes a substrate layer, a nucleation layer, a buffer layer, and a barrier layer from bottom to top;

[0159] A source electrode located at one end of the buffer layer;

[0160] A drain electrode located at the other end of the buffer layer;

[0161] An electrical isolation layer located on the barrier layer of the active region;

[0162] A dielectric layer located on the barrier layer, the source electrode, and the drain electrode. Among them, a plurality of grooves arranged at intervals are provided in the dielectric layer along the gate width direction;

[0163] A gate electrode located in a plurality of grooves arranged at intervals in the dielectric layer along the gate width direction;

[0164] A metal interconnection layer located on the source electrode, the drain electrode, and the dielectric layer in the metal interconnection region.

[0165] In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0166] In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or specific data points described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or specific data points described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0167] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as falling within the protection scope of the present invention.

Claims

1. A preparation method of a HEMT device based on dual-threshold coupling of a gate dielectric, characterized in that, Including the following steps: Preparing an epitaxial substrate, which sequentially includes a substrate layer, a nucleation layer, a buffer layer, and a barrier layer from bottom to top; Fabricating a source electrode and a drain electrode on the buffer layer; Fabricating an electrically isolated region of the active region on the barrier layer; Growing a dielectric layer on the source electrode, the drain electrode, and the barrier layer; Fabricating a gate electrode in a preset combined groove of the dielectric layer, wherein the gate electrode is located between the source electrode and the drain electrode, and the preset combined groove is formed by a combination of a plurality of grooves arranged at intervals in the dielectric layer along the gate width direction; fabricating a gate electrode on the preset combined groove of the dielectric layer includes: Photolithographing a preset combined groove region on the dielectric layer; Etching the dielectric layer within the preset combined groove region to form a preset combined groove; wherein, the dielectric layer is etched using a coupled plasma etching technique, and the etching conditions include: the reaction gas is CF4 or O2; Photolithographing a gate electrode region within all the grooves of the preset combined groove to fabricate the gate electrode within the gate electrode region; Photolithographing a metal interconnect region on the source electrode, the drain electrode in the metal interconnect opening region, and the dielectric layer that has not been etched with openings to evaporate and form a metal interconnect layer.

2. The preparation method of the HEMT device based on dual-threshold coupling of gate dielectrics according to claim 1, characterized in that, The material of the buffer layer is GaN, and the material of the barrier layer includes one of AlGaN, InAlN, and AlN.

3. The manufacturing method of the HEMT device based on dual-threshold coupling of gate dielectrics according to claim 1, characterized in that, Fabricating a source electrode and a drain electrode on the buffer layer includes: Photolithographing a source electrode region and a drain electrode region on the barrier layer; Respectively fabricating the source electrode and the drain electrode within the source electrode region and the drain electrode region; Using an annealing process to sink the source electrode and the drain electrode into the buffer layer to complete the fabrication of the source electrode and the drain electrode.

4. The manufacturing method of the HEMT device based on dual-threshold coupling of gate dielectrics according to claim 1, characterized in that, Fabricating an electrically isolated region of the active region on the barrier layer includes: Photolithographing an electrically isolated region on the barrier layer; Etching the barrier layer of the electrically isolated region and a part of the depth of the buffer layer to form the electrically isolated region of the active region.

5. The manufacturing method of the HEMT device based on dual-threshold coupling of gate dielectrics according to claim 1, characterized in that, Growing a dielectric layer on the barrier layer includes: Growing a dielectric layer on the barrier layer using a PECVD process.

6. The manufacturing method of the HEMT device based on dual-threshold coupling of gate dielectrics according to claim 1, characterized in that, Photolithographing a metal interconnect region on the source electrode, the drain electrode in the metal interconnect opening region, and the dielectric layer that has not been etched with openings to evaporate and form a metal interconnect layer includes: Photolithographing a metal interconnect opening region on the dielectric layer of the source electrode and the drain electrode; Using an etching process to remove the dielectric layer within the metal interconnect opening region to expose the source electrode and the drain electrode within the metal interconnect opening region; Photolithographing a metal interconnect region on the source electrode, the drain electrode within the metal interconnect opening region, and the dielectric layer that has not been etched with openings; Evaporating and forming a metal interconnect layer on the source electrode, the drain electrode within the metal interconnect region, and the dielectric layer.

7. The manufacturing method of the HEMT device based on dual-threshold coupling of gate dielectrics according to claim 1, characterized in that, The source electrode and the drain electrode are a metal stack structure composed of Ti, Al, Ni, and Au from bottom to top, the gate electrode is a metal stack structure composed of Ni, Au, and Ni from bottom to top, and the metal interconnection layer is a metal stack structure composed of Ti and Au from bottom to top.

8. A HEMT device based on dual-threshold coupling of gate dielectrics, characterized in that, The HEMT device is fabricated by the fabrication method according to any one of claims 1 to 7, and the HEMT device includes: an epitaxial substrate, which sequentially includes a substrate layer, a nucleation layer, a buffer layer, and a barrier layer from bottom to top; a source electrode located at one end of the buffer layer; a drain electrode located at the other end of the buffer layer; an electrical isolation layer located on the barrier layer in the active region; a dielectric layer located on the barrier layer, the source electrode, and the drain electrode, wherein a plurality of grooves arranged at intervals are provided in the dielectric layer along the gate width direction; a gate electrode located in a plurality of grooves arranged at intervals in the dielectric layer along the gate width direction; a metal interconnection layer located on the source electrode, the drain electrode, and the dielectric layer in the metal interconnection region.

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