Self-aligned etch back for vertical three-dimensional (3D) memory

Abstract

Systems, methods, and apparatuses are provided for self-aligned etch-back for vertical three-dimensional (3D) memory. An example method includes depositing a layer of first dielectric material, semiconductor material, and second dielectric material to form a vertical stack, forming a first vertical opening to form an elongated vertical column of a first vertical sidewall in the vertical stack, and forming a second vertical opening through the vertical stack to expose a second vertical sidewall. Further, the example method includes removing portions of the semiconductor material to form a first horizontal opening, and depositing a fill material in the first horizontal opening. The method can further include forming a third vertical opening to expose a third vertical sidewall in the vertical stack, and selectively removing the fill material to form a plurality of second horizontal openings in which horizontally oriented storage nodes are to be formed.

Description

Technical Field

[0001] This disclosure relates generally to memory devices, and more specifically to self-aligned etchback for vertical three-dimensional (3D) memory. Background Technology

[0002] Memory is commonly implemented in electronic systems such as computers, cell phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and can include Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, Nnitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), etc.

[0003] With shrinking design rules, less semiconductor space is available for manufacturing memories containing DRAM arrays. A corresponding memory cell for DRAM may include access means (e.g., transistors) having first and second source / drain regions separated by a channel region. A gate may be opposite to and separated from the channel region by a gate dielectric. Access lines, such as word lines, are electrically connected to the gate of the DRAM cell. The DRAM cell may include memory nodes, such as capacitor cells, coupled to digital lines via access means. Access means may be activated (e.g., for selecting a cell) via access lines coupled to access transistors. Capacitors may store charge corresponding to the data value (e.g., logic "1" or "0") of the corresponding cell. Summary of the Invention

[0004] One aspect of this disclosure relates to a method for forming a vertically stacked memory cell array, the array having horizontally oriented access means and horizontally oriented memory nodes, the method comprising: vertically depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material in repeated iterations to form a vertical stack; forming a plurality of first vertical openings having a first horizontal direction and a second horizontal direction, extending through the vertical stack and primarily in the second horizontal direction to form an elongated column of vertical pillars having first vertical sidewalls in the vertical stack; conformally depositing a conductive material on the gate dielectric material in the plurality of first vertical openings; and removing the gate dielectric material in the plurality of first vertical openings. The conductive material is used to form a plurality of individual vertical conductive lines along the first vertical sidewall; a third dielectric material is deposited in the plurality of first vertical openings; a plurality of second vertical openings are formed in the third dielectric material to expose the second vertical sidewalls in the vertical stack; a plurality of first horizontal openings are formed in the layer of the semiconductor material; a filler material is deposited to fill the plurality of first horizontal openings in the elongated vertical column; a third vertical opening is formed to expose the third vertical sidewalls of the vertical stack adjacent to the memory node region; and the filler material is selectively removed along the second horizontal direction to form a plurality of second horizontal openings in which the horizontally oriented memory nodes will be formed.

[0005] Another aspect of this disclosure relates to a method for forming a vertically stacked memory cell array having horizontally oriented access means and horizontally oriented memory nodes, the method comprising: vertically depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material in repeated iterations to form a vertical stack; performing etching to form a plurality of first vertical openings having a first horizontal direction and a second horizontal direction, extending through the vertical stack and primarily in the second horizontal direction to form an elongated column of vertical pillars having first vertical sidewalls in the vertical stack; conformally depositing a conductive material on the gate dielectric material in the plurality of first vertical openings; and performing etching to remove portions of the conductive material in the plurality of first vertical openings, thereby along the The first vertical sidewalls form a plurality of individual vertical conductive lines; a third dielectric material is deposited in the plurality of first vertical openings; etching is performed to form a plurality of second vertical openings in the third dielectric material, thereby exposing the second vertical sidewalls in the vertical stack; lateral etching is performed to form a plurality of first horizontal openings in the layer of the semiconductor material; a selective filler material selective for the semiconductor material is deposited to fill the plurality of first horizontal openings in the elongated vertical column; etching is performed to form a plurality of third vertical openings, thereby exposing the third vertical sidewalls in the vertical stack adjacent to the access device region; and etching is performed to selectively remove the filler material along the second horizontal direction, thereby forming a plurality of second horizontal openings in which access devices are to be formed.

[0006] Another aspect of this disclosure relates to a memory device comprising a vertically stacked memory cell array having horizontally oriented access means and horizontally oriented memory nodes. The memory device includes: the vertically stacked memory cell array having horizontally oriented access means and horizontally oriented memory nodes, the vertically stacked memory cell array comprising: the horizontally oriented access means having a first source / drain region and a second source / drain region separated by a channel, and having a gate opposite to the channel and separated from it by a gate dielectric; vertically oriented conductive lines coupled to the gate and separated from the channel by the gate dielectric; and self-aligned memory nodes formed in the vertically stacked memory cell array. Attached Figure Description

[0007] Figure 1A This is a schematic illustration of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0008] Figure 1B This is a perspective view illustrating a portion of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0009] Figure 2A This is a schematic illustration of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0010] Figure 2B This is a perspective view illustrating a portion of a horizontal access device in a vertical three-dimensional (3D) memory array according to several embodiments of the present disclosure.

[0011] Figures 3A-3B This is a perspective view illustrating a portion of a horizontal access device in a vertical three-dimensional (3D) memory cell according to several embodiments of the present disclosure.

[0012] Figure 4 An example method for forming a vertically stacked memory cell array according to several embodiments of the present disclosure is shown, which is a stage in a semiconductor manufacturing process for forming a vertically stacked memory cell array having horizontal access means.

[0013] Figures 5A-5B Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process.

[0014] Figures 6A-6E Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process.

[0015] Figures 7A-7D Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process.

[0016] Figures 8A-8B Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process.

[0017] Figures 9A-9F Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process.

[0018] Figures 10A-10E Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process.

[0019] Figure 11A-11EExamples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process.

[0020] Figures 12A-12E Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process.

[0021] Figures 13A-13E Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process.

[0022] Figure 14 Examples of horizontally oriented access devices coupled to horizontally oriented storage nodes are shown according to several embodiments of the present disclosure.

[0023] Figure 15 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Detailed Implementation

[0024] Embodiments of this disclosure describe self-aligned etchback of a vertical three-dimensional (3D) memory. A filler material is deposited in a first horizontal opening in a semiconductor material layer formed in a vertically stacked memory cell array. Selective etching is used to remove the filler material to form a second horizontal opening in the semiconductor material layer of the vertically stacked memory cells. The selective etching is selective to the semiconductor material of the layer in which the filler material is deposited. Memory node material is deposited in the second horizontal opening to form a horizontal memory node.

[0025] The second horizontal opening is formed by selectively removing filler material via selective etching, rather than by removing portions of the semiconductor material through timed etching, increasing control over the etching process. As the size of vertical 3D memory decreases and aspect ratios increase, it becomes more difficult to control the expected etch-back distance relative to the vertical opening with a high aspect ratio using timed etching; therefore, different layers of semiconductor material may unintentionally have different etch-back lengths. As used herein, the term "etch-back distance" refers to the horizontal distance over which a portion of the material within a material layer has been removed. Different etch-back distances can lead to non-uniform component formation, such as memory nodes and / or access devices. For example, non-uniformity in the size and surface area of ​​capacitors formed as memory nodes can cause variations in charge storage capacity. Unintended variations in charge storage can lead to inaccurate memory cell reads and / or device performance failures. Non-uniformity in other components can cause similar problems. As used herein, the term "gate-induced drain leakage" refers to the tunneling-based leakage current generated when the gate overlaps with the drain. Using selective etching to selectively remove filler material can reduce, for example, eliminate any differences in etch-back distance, and thus mitigate any GIDL.

[0026] The diagrams in this document follow a numbering convention, where the first one or more digits correspond to the diagram number, and the remaining digits identify the elements or components in the diagram. Similar elements or components between different diagrams can be identified by using similar digits. For example, reference numeral 101 in Figure 1 can refer to element "01," and a similar element can be represented as 201 in Figure 2. Multiple similar elements within a diagram can be represented by a reference numeral followed by a hyphen and another digit or letter. For example, 103-1 can refer to element 103-1 in Figure 1, and 103-2 can refer to element 103-2, which can be similar to element 103-1. Such similar elements can be generally referred to without a hyphen and additional digits or letters. For example, elements 103-1 and 103-2, or other similar elements, can be generally represented as 103.

[0027] Figure 1A This is a block diagram of a device according to several embodiments of the present disclosure. Figure 1A A circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure is shown. Figure 1AThe cell array shown can have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each of the sub-cell arrays (e.g., sub-cell array 101-2) can contain multiple access lines 107-1, 107-2, ..., 107-Q (which may also be referred to as word lines). Additionally, each of the sub-cell arrays (e.g., sub-cell array 101-2) can contain multiple digital lines 103-1, 103-2, ..., 103-Q (which may also be referred to as bit lines, data lines, or sensing lines). Figure 1A The diagram shows access lines 107-1, 107-2, ..., 107-Q extending in a first direction (D1) 109, and digital lines 103-1, 103-2, ..., 103-Q extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, digital lines 103-1, 103-2, ..., 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).

[0028] A memory cell (e.g., 110) may include access means (e.g., access transistors) and memory nodes located at the intersections of each access line 107-1, 107-2, ..., 107-Q and each digital line 103-1, 103-2, ..., 103-Q. Data can be written to or read from the memory cell using the access lines 107-1, 107-2, ..., 107-Q and the digital lines 103-1, 103-2, ..., 103-Q. Access lines 107-1, 107-2, ..., 107-Q can electrically interconnect memory cells along the horizontal rows of each sub-cell array 101-1, 101-2, ..., 101-N, and digital lines 103-1, 103-2, ..., 103-Q can electrically interconnect memory cells along the vertical columns of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) can be located between an access line (e.g., 107-2) and a digital line (e.g., 103-2). Each memory cell can be uniquely addressed by a combination of access lines 107-1, 107-2, ..., 107-Q and digital lines 103-1, 103-2, ..., 103-Q.

[0029] Access lines 107-1, 107-2, ..., 107-Q may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Access lines 107-1, 107-2, ..., 107-Q may extend in a first direction (D1) 109. Access lines 107-1, 107-2, ..., 107-Q in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0030] Digital lines 103-1, 103-2, ..., 103-Q may be or be contained in conductive patterns, such as metal lines, extending in a vertical direction relative to the substrate (e.g., in a third direction (D3) 111). Digital lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0031] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 107-2), and a first conductive node (e.g., a first source / drain region) of an access means (e.g., a transistor) of memory cell 110 may be connected to a digital line (e.g., 103-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node, such as a capacitor. A second conductive node (e.g., a second source / drain region) of an access means (e.g., a transistor) of memory cell 110 may be connected to a storage node, such as a capacitor. Although the references to first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as “first” and / or “second” have a particular meaning. It is desirable that only one source / drain region is connected to a digital line (e.g., 103-2), and the other may be connected to a storage node.

[0032] Figure 1B This illustration shows a three-dimensional (3D) semiconductor memory device according to some embodiments of the present disclosure, such as... Figure 1A The sub-cell array 101-2 shown is a perspective view of the vertically oriented stacking of memory cells in the array.

[0033] like Figure 1B As shown, substrate 100 may have a bonding formed thereon. Figure 1A One of the described array of sub-cells (e.g., 101-2). For example, substrate 100 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0034] like Figure 1B As shown in the example embodiment, memory cells (e.g., extending in a vertical direction such as third direction (D3) 111) may be fabricated on the substrate 100. Figure 1A The memory cells 110 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 1A The memory cells 110 are formed in multiple vertical layers, such as a first layer (L1), a second layer (L2), and a third layer (L3). They can be arranged vertically (e.g., along the vertical direction). Figure 1A The diagram shows a third-party (D3) 111) arrangement (e.g., “stacked”) of repeating vertical layers L1, L2, and L3. Each of the repeating vertical layers L1, L2, and L3 may contain multiple discrete components (e.g., regions) of horizontally oriented access devices 129 (e.g., transistors) and memory nodes (e.g., capacitors), including access lines 107-1, 107-2, ..., 107-Q connectors and digital lines 103-1, 103-2, ..., 103-Q connectors. The multiple discrete components of the horizontally oriented access devices 129 (e.g., transistors) may be formed in multiple stacks of vertical repeating layers within each layer, and may be similar to Figure 1A The second direction (D2) 105 shown in the figure extends horizontally in the second direction (D2) 105.

[0035] A plurality of discrete components of a horizontally oriented access device 129 (e.g., a transistor) may include a first source / drain region 121 and a second source / drain region 123 separated by a channel region 125 extending laterally in a second direction (D2) 105 and formed in the body of the access device. In some embodiments, the channel region 125 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 121 and the second source / drain region 123 may comprise an n-type dopant region formed in the p-type doped body of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 121 and the second source / drain region 123 may comprise a p-type dopant formed in the n-type doped body of the access device to form a p-type conductive transistor. By way of example, but not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in a relatively doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0036] Storage node 127 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 1BAs shown, storage node 127 (e.g., a capacitor) may be connected to a second source / drain region 123 of the access device. Storage nodes may be or contain memory elements capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g. Figure 1A Each memory node associated with an access device in memory cell 110 can be similarly located in a memory node with a memory node ... Figure 1A The second direction (D2) 105 shown in the figure extends on the second direction (D2) 105.

[0037] like Figure 1B As shown, multiple horizontally oriented access lines 107-1, 107-2, ..., 107-Q are in a manner similar to... Figure 1A The first direction (D1) 109 extends along the first direction (D1) 109. Multiple horizontally oriented access lines 107-1, 107-2, ..., 107-Q can be similar to... Figure 1A Access lines 107-1, 107-2, ..., 107-Q are shown. Multiple horizontally oriented access lines 107-1, 107-2, ..., 107-Q may be arranged (e.g., "stacked") along a third direction (D3) 111. Multiple horizontally oriented access lines 107-1, 107-2, ..., 107-Q may comprise a conductive material. For example, the conductive material may comprise one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0038] In each of the vertical hierarchies (L1)113-1, (L2)113-2, and (L3)113-P, the horizontally oriented memory cells (e.g.) Figure 1AThe memory cells 110 in the memory may be horizontally spaced apart from each other in the first direction (D1) 109. However, the multiple discrete components of the horizontally oriented access device 129 extending laterally in the second direction (D2) 105 (e.g., the first source / drain region 121 and the second source / drain region 123 separated by the channel region 125), and the multiple horizontally oriented access lines 107-1, 107-2, ..., 107-Q extending laterally in the first direction (D1) 109 may be formed in different vertical layers within each level. For example, a plurality of horizontally oriented access lines 107-1, 107-2, ..., 107-Q extending in the first direction (D1) 109 may be formed on the top surface of the channel region 125 opposite to and electrically coupled to the channel region 125, separated from the channel region 125 by the gate dielectric 104, and orthogonal to the horizontally oriented access device 129 (e.g., a transistor) extending laterally in the second direction (D2) 105. In some embodiments, the plurality of horizontally oriented access lines 107-1, 107-2, ..., 107-Q extending in the first direction (D1) 109 are formed in a higher vertical layer within a layer (e.g., within layer (L1)), which is further away from the substrate 100 than the layer in which discrete components of the horizontally oriented access device (e.g., the first source / drain region 121 and the second source / drain region 123 separated by the channel region 125) are formed.

[0039] like Figure 1B As shown in the example embodiment, digital lines 103-1, 103-2, ..., 103-Q extend in a vertical direction relative to the substrate 100 (e.g., on a third direction (D3) 111). Furthermore, as... Figure 1B As shown, a sub-cell array (e.g., Figure 1AThe digital lines 103-1, 103-2, ..., 103-Q in the sub-cell array 101-2 can be spaced apart from each other in the first direction (D1) 109. The digital lines 103-1, 103-2, ..., 103-Q can be provided to extend vertically relative to the substrate 100 in the third direction (D3) 111 in a form that is vertically aligned with the source / drain region 121 that serves as the first source / drain region 121, or as shown, to be vertically adjacent to the first source / drain region 121 that extends laterally in the second direction (D2) 105 of each of the horizontally oriented access devices 129 (e.g., transistors), but adjacent to each other in the first direction (D1) 109 at the level (e.g., the first level (L1)). Each of the digital lines 103-1, 103-2, ..., 103-Q may extend vertically in a third direction (D3) on the sidewall of the corresponding of a plurality of horizontally oriented access devices 129 (e.g., transistors) stacked vertically. In some embodiments, the plurality of vertically oriented digital lines 103-1, 103-2, ..., 103-Q extending in the third direction (D3) 111 may be directly and / or connected to the side surface of the first source / drain region 121 via additional contacts comprising metal silicide.

[0040] For example, the first (e.g., 103-1) of the vertically extending digital line may be adjacent to the sidewall of the first source / drain region 121 of the first horizontally oriented access device 129 (e.g., transistor) in the first level (L1) 113-1, the sidewall of the first source / drain region 121 of the first horizontally oriented access device 129 (e.g., transistor) in the second level (L2) 113-2, and the sidewall of the first source / drain region 121 of the first horizontally oriented access device 129 (e.g., transistor) in the third level (L3) 113-P, etc. Similarly, the second vertically extending digital line (e.g., 103-2) may be adjacent to the sidewall of the first source / drain region 121 of the second horizontally oriented access device 129 (e.g., transistor) in the first level (L1) 113-1, and spaced apart from the first horizontally oriented access device 129 (e.g., transistor) in the first direction (D1) 109. Furthermore, the second vertically extending digital line (e.g., 103-2) may be adjacent to the sidewall of the first source / drain region 121 of the second horizontally oriented access device 129 (e.g., transistor) in the second level (L2) 113-2, and the sidewall of the first source / drain region 121 of the second horizontally oriented access device 129 (e.g., transistor) in the third level (L3) 113-P, etc. The embodiments are not limited to a specific number of levels.

[0041] The vertically extending digital lines 103-1, 103-2, ..., 103-Q may contain conductive materials, such as doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. The digital lines 103-1, 103-2, ..., 103-Q may correspond to... Figure 1A The described digital line (DL).

[0042] like Figure 1B As shown in the example embodiment, the conductive body contact 195 may be formed to extend along the end surface of a horizontally oriented access device 129 (e.g., a transistor) in each of the levels (L1) 113-1, (L2) 113-2, and (L3) 113-P above the substrate 100 in a first direction (D1) 109. The body contact may be connected to each memory cell (e.g., Figure 1A The body, such as the body region, of the horizontally oriented access device 129 (e.g., a transistor) in the memory cell 110. The body contacts may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0043] although Figure 1B Not shown, but insulating material may fill other spaces in the vertically stacked memory cell array. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0044] Figure 2A This is a block diagram of a device according to several embodiments of the present disclosure. Figure 2A A circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure is shown. Figure 2A The diagram shows that the cell array may have multiple sub-cell arrays 201-1, 201-2, ..., 201-N. Sub-cell arrays 201-1, 201-2, ..., 201-N may be arranged along a second direction (D2) 205. Each of the sub-cell arrays, such as sub-cell array 201-2, may contain multiple access lines 207-1, 207-2, ..., 207-Q (which may also be referred to as word lines). Additionally, each of the sub-cell arrays, such as sub-cell array 201-2, may contain multiple digital lines 203-1, 203-2, ..., 203-Q (which may also be referred to as bit lines, data lines, or sensing lines). Figure 2A The diagram shows digital lines 203-1, 203-2, ..., 203-Q extending in the first direction (D1) 209, and access lines 207-1, 207-2, ..., 207-Q extending in the third direction (D3) 211.

[0045] The first direction (D1) 209 and the second direction (D2) 205 can be considered to be in a horizontal (“XY”) plane. The third direction (D3) 211 can be considered to be in a vertical (“Z”) direction (e.g., transverse to the XY plane). Therefore, according to the embodiments described herein, access lines 207-1, 207-2, ..., 207-Q extend in a vertical direction (e.g., the third direction (D3) 211).

[0046] The memory cell (e.g., 210) may include access means (e.g., access transistors) and memory nodes located at the intersections of each access line 207-1, 207-2, ..., 207-Q and each digital line 203-1, 203-2, ..., 203-Q. The memory cell can be written to or read from using the access lines 207-1, 207-2, ..., 207-Q and the digital lines 203-1, 203-2, ..., 203-Q. Digital lines 203-1, 203-2, ..., 203-Q can electrically interconnect memory cells along the horizontal columns of each sub-cell array 201-1, 201-2, ..., 201-N, and access lines 207-1, 207-2, ..., 207-Q can electrically interconnect memory cells along the vertical rows of each sub-cell array 201-1, 201-2, ..., 201-N. A memory cell (e.g., 210) can be located between an access line (e.g., 207-2) and a digital line (e.g., 203-2). Each memory cell can be uniquely addressed by a combination of access lines 207-1, 207-2, ..., 207-Q and digital lines 203-1, 203-2, ..., 203-Q.

[0047] Digital lines 203-1, 203-2, ..., 203-Q may be or comprise conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Digital lines 203-1, 203-2, ..., 203-Q may extend in a first direction (D1) 209. Digital lines 203-1, 203-2, ..., 203-Q in a sub-cell array (e.g., 201-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 211).

[0048] Access lines 207-1, 207-2, ..., 207-Q may be or be contained in conductive patterns (e.g., metal lines) extending in a vertical direction relative to the substrate (e.g., in a third direction (D3) 211). Access lines in a sub-cell array (e.g., 201-2) may be spaced apart from each other in a first direction (D1) 209.

[0049] The gate of a memory cell (e.g., memory cell 210) may be connected to an access line (e.g., 207-2), and the first conductive node (e.g., a first source / drain region) of the access means (e.g., a transistor) of memory cell 210 may be connected to a digital line (e.g., 203-2). Each of the memory cells (e.g., memory cell 210) may be connected to a storage node (e.g., a capacitor). The second conductive node (e.g., a second source / drain region) of the access means (e.g., a transistor) of memory cell 210 may be connected to a storage node (e.g., a capacitor). The storage node (e.g., a capacitor) may be formed of a ferroelectric and / or dielectric material, such as zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), lead zirconate titanate (PZT, Pb[Zr(x)Ti(1-x)]O3), barium titanate (BaTiO3), aluminum oxide (e.g., Al2O3), combinations of these with or without dopants, or other suitable materials.

[0050] Although this document uses the references of first and second source / drain regions to refer to two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" have a specific meaning. It is only desirable that one of the source / drain regions is connected to a digital line (e.g., 203-2), and the other is connected to a memory node.

[0051] Figure 2B This illustration shows a three-dimensional (3D) semiconductor memory device (e.g., according to some embodiments of the present disclosure) Figure 2A The sub-cell array 201-2 shown in Figure 3 is a perspective view of a portion of the vertically oriented stack of memory cells in the array. Figure 2B The unit cell of the 3D semiconductor memory device shown in the figure (e.g.) Figure 2A A perspective view of the memory cell 210 shown in the figure.

[0052] like Figure 2B As shown, substrate 200 may have a bonding formed thereon. Figure 2A One of the described array of sub-cells (e.g., 201-2). For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0053] like Figure 2B As shown in the example embodiment, memory cells extending in a vertical direction (e.g., third direction (D3) 211) can be fabricated on the substrate 200. Figure 2A The memory cells 210 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 2AThe memory cells 210 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). They can be arranged along the vertical direction (e.g., ...). Figure 2A The diagram shows a third-party (D3) 211) arrangement (e.g., “stacked”) of repeating vertical layers L1, L2, and L3. Each of the repeating vertical layers L1, L2, and L3 may contain multiple discrete components (e.g., regions) of horizontally oriented access devices 229 (e.g., transistors) and memory nodes (e.g., capacitors), including access lines 207-1, 207-2, ..., 207-Q connectors and digital lines 203-1, 203-2, ..., 203-Q connectors. The multiple discrete components of the horizontally oriented access devices 229 (e.g., transistors) may be formed in multiple stacks of vertical repeating layers within each layer, and may be similar to Figure 2A The second direction (D2) 205 shown in the figure extends horizontally on the second direction (D2) 205.

[0054] A plurality of discrete components of a horizontally oriented access device 229 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225 extending laterally in a second direction (D2) 205 and formed in the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise an n-type dopant region formed in the p-type doped body of the access device to form an n-type conductive transistor. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise a p-type dopant formed in the n-type doped body of the access device to form a p-type conductive transistor. By way of example, but not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in a relatively doped body region of a polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0055] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of access device 229. For example... Figure 2B As shown, storage node 227 (e.g., a capacitor) may be connected to the second source / drain region 223 of the access device. Storage nodes may be or contain memory elements capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g. Figure 2A Each memory node associated with an access device in memory cell 210 can be similarly located in a memory node with a memory access device ... Figure 2AThe second direction (D2) 205 shown in the figure extends on the second direction (D2) 205.

[0056] like Figure 2B As shown, multiple horizontally oriented digital lines 203-1, 203-2, ..., 203-Q are similar to... Figure 2A Extending along the first direction (D1) 209. Multiple horizontally oriented digital lines 203-1, 203-2, ..., 203-Q can be similar to... Figure 2A The digital lines 203-1, 203-2, ..., 203-Q are shown in the figure. Multiple horizontally oriented digital lines 203-1, 203-2, ..., 203-Q may be arranged (e.g., "stacked") along a third direction (D3) 211. The multiple horizontally oriented digital lines 203-1, 203-2, ..., 203-Q may contain a conductive material. For example, the conductive material may contain one or more of the following: doped semiconductors (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or metal-semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, the embodiments are not limited to these examples.

[0057] In each of the vertical hierarchies (L1)213-1, (L2)213-2, and (L3)213-P, the horizontally oriented memory cells (e.g.) Figure 2AThe memory cells 210 in the memory may be horizontally spaced apart from each other in the first direction (D1) 209. However, the multiple discrete components of the horizontally oriented access device 229 extending laterally in the second direction (D2) 205 (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225), and the multiple horizontally oriented digital lines 203-1, 203-2, ..., 203-Q extending laterally in the first direction (D1) 209 may be formed in different vertical layers within each level. For example, the multiple horizontally oriented digital lines 203-1, 203-2, ..., 203-Q extending laterally in the first direction (D1) 209 may be disposed on the top surface of the first source / drain region 221 and electrically contacted with the top surface, and orthogonal to the horizontally oriented access device 229 (e.g., transistors) extending laterally in the second direction (D2) 205. In some embodiments, a plurality of horizontally oriented digital lines 203-1, 203-2, ..., 203-Q extending in the first direction (D1) 209 are formed in a higher vertical layer within a layer hierarchy (e.g., within layer (L1)), which is further away from the substrate 200 than the layer in which discrete components of the horizontally oriented access devices (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) are formed. In some embodiments, the plurality of horizontally oriented digital lines 203-1, 203-2, ..., 203-Q extending in the first direction (D1) 209 may be directly and / or connected to the top surface of the first source / drain region 221 via additional contacts comprising metal silicide.

[0058] like Figure 2B As shown in the example embodiment, access lines 207-1, 207-2, ..., 207-Q extend in a vertical direction relative to substrate 200 (e.g., on third direction (D3) 211). Furthermore, as... Figure 2B As shown, a sub-cell array (e.g., Figure 2A Access lines 207-1, 207-2, ..., 207-Q in the sub-cell array 201-2 can be spaced apart from each other in a first direction (D1) 209. Access lines 207-1, 207-2, ..., 207-Q can be provided that extend vertically in a third direction (D3) 211 relative to the substrate 200 between a pair of horizontally oriented access devices 229 (e.g., transistors) extending laterally in a second direction (D2) 205, but are adjacent to each other in a layer (e.g., a first layer (L1)) in the first direction (D1) 209. Each of access lines 207-1, 207-2, ..., 207-Q can extend vertically in a third direction (D3) on the sidewall of the corresponding of a plurality of vertically stacked horizontally oriented access devices 229 (e.g., transistors).

[0059] For example, the first vertically extending access line (e.g., 207-1) may be adjacent to the sidewall of the channel region 225 of the first horizontally oriented access device 229 (e.g., transistor) in the first level (L1) 213-1, the sidewall of the channel region 225 of the first horizontally oriented access device 229 (e.g., transistor) in the second level (L2) 213-2, and the sidewall of the channel region 225 of the first horizontally oriented access device 229 (e.g., transistor) in the third level (L3) 213-P, etc. Similarly, the second vertically extending access line (e.g., 207-2) may be adjacent to the sidewall of the channel region 225 of the second horizontally oriented access device 229 (e.g., transistor) in the first level (L1) 213-1, and spaced apart from the first horizontally oriented access device 229 (e.g., transistor) in the first direction (D1) 209. Furthermore, the second vertically extending access line (e.g., 207-2) may be adjacent to the sidewall of the channel region 225 of the second horizontally oriented access device 229 (e.g., transistor) in the second level (L2) 213-2, and the sidewall of the channel region 225 of the second horizontally oriented access device 229 (e.g., transistor) in the third level (L3) 213-P, etc. The embodiments are not limited to a specific number of levels.

[0060] The vertically extending access lines 207-1, 207-2, ..., 207-Q may contain conductive materials, such as doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. Access lines 207-1, 207-2, ..., 207-Q may correspond to... Figure 2A The described access line (AL).

[0061] like Figure 2B As shown in the example embodiment, the conductive body contact 295 may be formed to extend along the end surface of a horizontally oriented access device 229 (e.g., a transistor) in a first direction (D1) 209 along the end surface of each layer (L1) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200. The body contact 295 may be connected to each memory cell (e.g., Figure 2A The body of the horizontally oriented access device 229 (e.g., a transistor) in the memory cell 210. The body contacts 295 may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0062] although Figure 2BNot shown, but insulating material may fill other spaces in the vertically stacked memory cell array. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0063] Figure 3A A more detailed illustration is shown of a vertically stacked array of memory cells according to some embodiments of the present disclosure (e.g., Figure 1A and 1B The unit cells (e.g., within the sub-cell array 101-2) in the sub-cell array 101-2 Figure 1A and 1B (Memory unit 110 in the middle). For example Figure 3A As shown, the first source / drain region 321 and the second source / drain region 323 may be impurity-doped regions of a horizontally oriented access device 329 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 may be similar to the first source / drain region 221 and the second source / drain region 223 shown in FIG. 2. The first and second source / drain regions may be separated by a channel 325 formed in a body (e.g., a body region) of the semiconductor material of the horizontally oriented access device 329 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 may be formed by an n-type or p-type dopant doped in the body region. The embodiments are not limited thereto.

[0064] For example, in an n-type conductive transistor configuration, the body region of the horizontally oriented access device 329 (e.g., a transistor) may be formed of a lightly doped p-type (p-) semiconductor material. In one embodiment, the body region and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 may comprise a lightly doped p-type (e.g., a lower dopant concentration (p-)) polycrystalline silicon (Si) material composed of boron (B) atoms as an impurity dopant for the polycrystalline silicon. The first source / drain region 321 and the second source / drain region 323 may also comprise metals and / or metal composite materials formed using atomic layer deposition processes, etc., containing at least one of the following: ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), a highly doped degenerate semiconductor material, and / or indium oxide (In₂O₃) or indium tin oxide (In₂-xSnxO₃). However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor material refers to a semiconductor material, such as polycrystalline silicon, containing a high level of doping with significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain a moderate level of doping, where the dopant atoms are well separated from each other in the semiconductor bulk lattice with negligible interactions.

[0065] In this example, the first source / drain region 321 and the second source / drain region 323 may contain highly doped n-type conductive impurities (e.g., highly doped (n+)) doped into the first source / drain region 321 and the second source / drain region 323. In some embodiments, the highly doped n-type conductive first drain region 321 and the second drain region 323 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the horizontally oriented access device 329 (e.g., a transistor) may have a p-type conductive configuration, in which case the conductivity type of the impurities (e.g., dopants) will be reversed.

[0066] like Figure 3A As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body of the horizontally oriented access device 329 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface within the body of the horizontally oriented access device 329, the bottom surface being vertically positioned above the bottom surface of the body of the horizontally oriented access device 329 in a third direction (D3) 311. Therefore, the horizontally oriented transistor 329 may have a body portion located below the first source / drain region 321 and electrically in contact with the body contacts. Furthermore, as... Figure 3A As shown in the example embodiments, similar to access lines 203-1, 203-2, ..., 203-Q in FIG2 and 107-1, 107-2, ..., 107-Q shown in FIG1, access lines (e.g., 307) may be disposed on a top surface opposite to and coupled to the channel region 325, the top surface being separated from the channel region by a gate dielectric 304. The gate dielectric material 304 may comprise, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The embodiments are not limited thereto. For example, in the high-k dielectric material example, the gate dielectric material 304 may comprise one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0067] like Figure 3A As shown in the example embodiments, similar to Figure 2A and 2B The number lines 207-1, 207-2, ..., 207-Q and Figure 1A and 1BIn the diagram, 103-1, 103-2, ..., 103-Q, digital lines (e.g., 303-1) can extend vertically along a third direction (D3) 311 adjacent to the sidewall of the first source / drain region 321 in the body to a horizontally oriented access device 329, such as a transistor horizontally conducting between the first source / drain region 321 and the second source / drain region 323 along a second direction (D2) 305. In this embodiment, the vertically oriented digital line 303-1 is asymmetrically topographically positioned adjacent to the electrical contact with the first source / drain region 321. The digital line 303-1 can be asymmetrically formed to reserve space for body contacts in the channel region 325.

[0068] Figure 3B A more detailed illustration of a vertically stacked memory cell array according to some embodiments of the present disclosure (e.g.) Figure 1A The unit cells (e.g., within the sub-cell array 101-2) in the sub-cell array 101-2 Figure 1A (Memory unit 110 in the middle). For example Figure 3B As shown, the first source / drain region 321 and the second source / drain region 323 can be impurity-doped regions of a horizontally oriented access device 329 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be similar to the first source / drain region 221 and the second source / drain region 223 shown in FIG2. Figure 3A The first source / drain region 321 and the second source / drain region 323 are shown. The first and second source / drain regions can be separated by a channel 325 formed in the body (e.g., the body region) of the semiconductor material of the horizontally oriented access device 329 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 can be formed by an n-type or p-type dopant doped in the body region. The embodiments are not limited thereto.

[0069] like Figure 3B As shown in the example embodiment, similar to digital lines 207-1, 207-2, ..., 207-Q in FIG. 2 and 103-1, 103-2, ..., 103-Q in FIG. 1, a digital line (e.g., 303-1) may extend vertically along a third direction (D3) 311 adjacent to the sidewall of the first source / drain region 321 in the body to a horizontally oriented access device 329, such as a transistor that conducts horizontally between the first source / drain region 321 and the second source / drain region 323, for example, along a second direction (D2) 305. In this embodiment, the vertically oriented digital line 303-1 is asymmetrically topographically aligned with and in electrical contact with the first source / drain region 321. The digital line 303-1 may be formed to contact an insulating material such that there is no body contact within the channel 325.

[0070] like Figure 3BAs shown in the example embodiment, digital line 303-1 may be symmetrically formed within first source / drain region 321, such that first source / drain region 321 surrounds digital line 303-1. First source / drain region 321 may occupy the upper portion of the body of horizontally oriented access device 329 (e.g., transistor). For example, first source / drain region 321 may have a bottom surface within the body of horizontally oriented access device 329, the bottom surface being vertically positioned above the bottom surface of the body of horizontally oriented access device 329 in a third direction (D3) 311. Therefore, horizontally oriented transistor 329 may have a body portion located below first source / drain region 321 and in contact with body contacts. Insulating material may fill the body contacts so that first source / drain region 321 may not be in electrical contact with channel 325. Furthermore, as... Figure 3B As shown in the example embodiment, similar to access lines 203-1, 203-2, ..., 203-Q in FIG2 and 107-1, 107-2, ..., 107-Q shown in FIG1, access lines (e.g., 307-1) may be disposed around and coupled to the channel region 325 and separated from it by the gate dielectric 304.

[0071] Figure 4 Example methods for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines, according to several embodiments of the present disclosure, are shown at a stage of a semiconductor manufacturing process. Figure 4 In the example embodiment shown in the example, the method includes depositing alternating layers of first dielectric material 430-1, 430-2, ..., 430-N (each or collectively referred to as first dielectric material 430), sacrificial material (e.g., semiconductor material) 432-1, 432-2, ..., 432-N (each or collectively referred to as sacrificial material 432), and second dielectric material 433-1, 433-2, ..., 433-N (each or collectively referred to as second dielectric material 433) in repeated iterations to form a vertical stack 402 on the working surface of the semiconductor substrate 400. In one embodiment, the dielectric material 430 may be deposited to have a thickness in the range of twenty (20) nanometers (nm) to sixty (60) nm, for example, a vertical height in a third direction (D3). In one embodiment, the sacrificial material 432 may be deposited to have a thickness in the range of twenty (20) nm to one hundred (100) nm, for example, a vertical height. In some embodiments, the height of the vertically stacked memory cell array may be at least four (4) layers. However, the embodiments are not limited to these examples.

[0072] In one example, the sacrificial materials 432-1, 432-2, ..., 432-N may comprise sacrificial semiconductor materials, such as polycrystalline silicon (Si), silicon nitride (SiN), or even oxide-based semiconductor compositions. Although the discussion herein refers to examples of sacrificial semiconductor materials, the embodiments are not limited to these examples. It is desirable that the sacrificial materials can be selectively etched relative to the layers of the first dielectric materials 430-1, 430-2, ..., 430-N and the second dielectric materials 433-1, 433-2, ..., 433-N.

[0073] like Figure 4 As shown, the vertical direction 411 is indicated as the third direction (D3), for example, the z-direction in the xyz coordinate system, similar to the third direction (D3) among the first, second, and third directions shown in Figures 1-3. Figure 4 In the example shown, four layers of repeated iterations of the vertical stack 402 are illustrated, numbered 1, 2, 3, and N. However, the embodiments are not limited to this example and may contain more or fewer repeated iterations. The photolithographic hard mask (HM) layer 435 may be deposited as the top layer on the repeated iterations of the vertical stack 402.

[0074] In some embodiments, the first dielectric material 430-1, 430-2, ..., 430-N and the second dielectric material 433-1, 433-2, ..., 432-N may be an interlayer dielectric (ILD). For example, but not as a limitation, the first dielectric material 430-1, 430-2, ..., 430-N and the second dielectric material 433-1, 433-2, ..., 433-N may comprise silicon dioxide (SiO2) material. In another example, the first dielectric material 430-1, 430-2, ..., 430-N and the second dielectric material 433-1, 433-2, ..., 432-N may comprise silicon nitride (Si3N4) material (also referred to herein as "SiN"). In another example, the first dielectric material 430-1, 430-2, ..., 430-N and the second dielectric material 433-1, 433-2, ..., 432-N may include silicon oxycarbide (SiO2). x C y The material (also referred to herein as "SiOC"). In another example, the first dielectric material 430-1, 430-2, ..., 430-N and the second dielectric material 433-1, 433-2, ..., 432-N may comprise silicon oxynitride (SiO2). x N yThe materials used are silicon (Si) materials (also referred to herein as "SiON") and / or combinations thereof. Embodiments are not limited to these examples. In some embodiments, the sacrificial semiconductor materials 432-1, 432-2, ..., 432-N may comprise silicon (Si) material in a polycrystalline and / or amorphous state. In another example, the sacrificial semiconductor materials 432-1, 432-2, ..., 432-N may comprise silicon nitride (SiN) material. However, embodiments are not limited to these examples.

[0075] Repeated iterations of the first dielectric material 430-1, 430-2, ..., 430-N, the sacrificial semiconductor material 432-1, 432-2, ..., 432-N, and the second dielectric material 433-1, 433-2, ..., 432-N layers can be deposited according to a semiconductor manufacturing process (e.g., chemical vapor deposition (CVD)) in a semiconductor manufacturing apparatus. However, the embodiments are not limited to this example, and other suitable semiconductor manufacturing techniques can be used to deposit the first dielectric material 430-1, 430-2, ..., 430-N, the sacrificial semiconductor material 432-1, 432-2, ..., 432-N, and the second dielectric material 433-1, 433-2, ..., 432-N layers in repeated iterations to form a vertical stack 402, such as... Figure 4 As shown in the image.

[0076] Figure 5A Examples of methods for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 5A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 5A In the example embodiment shown in the example, the method includes forming a plurality of first vertical openings 512 using an etchant process, the first vertical openings having a first horizontal direction (D1) 509 and a second horizontal direction (D2) 505, and extending through a vertical stack to a substrate. In one example, as Figure 5A As shown, the plurality of first vertical openings 512 extend primarily in the second horizontal direction (D2) 505 and can form an elongated column of vertical columns 513 having first vertical sidewalls 514 located in the vertical stack. The plurality of first vertical openings 512 can be formed by patterning a photolithographic mask 535 on the vertical stack using photolithography techniques, for example, to form a hard mask (HM), prior to etching the plurality of first vertical openings 512.

[0077] Figure 5B It is along Figure 5A The cross-sectional view obtained by cutting line A-A' in the figure shows another view of the semiconductor structure at a specific point in the semiconductor manufacturing process. Figure 5B The conductive materials 540-1, 540-2, ..., 540-4 are shown to be formed on the gate dielectric material 538 in the plurality of first vertical openings 512. For example, but not as a limitation, the gate dielectric material 538 may be conformally deposited in the plurality of first vertical openings 512 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings. The gate dielectric 538 may be deposited to a specific thickness (t1) suitable for a particular design rule, for example, a gate dielectric thickness of approximately 10 nanometers (nm). However, the embodiments are not limited to this example. For example, but not as a limitation, the gate dielectric 538 may include silicon dioxide (SiO2) material, aluminum oxide (Al2O3) material, high dielectric constant (k) (e.g., high k) dielectric material, and / or combinations thereof, as also described in FIG. 3.

[0078] In addition, such as Figure 5B As shown, a method for forming a vertically stacked memory cell array may include conformally depositing conductive materials 540-1, 540-2, ..., 540-4 on the gate dielectric material 538 in the plurality of first vertical openings 512. For example, but not as a limitation, the conductive materials 540-1, 540-2, ..., 540-4 may be conformally deposited on the surface of the gate dielectric material 538 in the plurality of first vertical openings 512 using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes to cover the bottom surface and vertical sidewalls of the plurality of first vertical openings on the gate dielectric 538. The conductive materials 540-1, 540-2, ..., 540-4 may be conformally deposited to a specific thickness (t2) to form vertically oriented access lines suitable for a specific design rule, for example as shown. Figure 1A and 1B The access lines 107-1, 107-2, ..., 107-Q (also referred to as word lines) are shown. For example, conductive materials 540-1, 540-2, ..., 540-4 can be conformally deposited to a thickness of approximately 20 nanometers (nm). However, the embodiments are not limited to this example. For example, but not as a limitation, conductive materials 540-1, 540-2, ..., 540-4 may include, for example, metals such as tungsten (W), metal compositions, titanium nitride (TiN), doped polycrystalline silicon, and / or some other combination thereof, as also described in Figure 3.

[0079] A method for forming a vertically stacked memory cell array may include removing portions of conductive material 540-1, 540-2, ..., 540-N from the plurality of first vertical openings 512, to extend along the first vertical sidewalls (e.g., Figure 5A The first vertical sidewall 514 forms multiple individual vertical conductive lines 540-1, 540-2, ..., 540-4. For example... Figure 5B As shown, conductive materials 540-1, 540-2, ..., 540-4 can be recessed to maintain their position only along the elongated vertical columnar columns (now...). Figure 5B The vertical sidewalls (shown as 542-1, 542-2, and 542-3) are shown in a cross-sectional view. Conductive materials 540-1, 540-2, ..., 540-4 can be obtained from the first vertical opening (e.g., ...) using a suitable selective anisotropic etching process. Figure 5A The conductive materials 540-1, 540-2, ..., 540-4 are removed from the bottom surface of 512 to create a recess, thereby exposing the gate dielectric 538 on the bottom surface to form individual conductive materials 540-1, 540-2, ..., 540-4.

[0080] like Figure 5B As shown, a method for forming a vertically stacked memory cell array may include depositing a third dielectric material 541 in the plurality of first vertical openings 512. For example, but not as a limitation, the third dielectric material 541 may be a material such as an oxide or other suitable spin dielectric (SOD), and may be deposited in the first vertical openings 512 using a process such as CVD to fill the first vertical openings 512. The dielectric may be planarized to the vertical semiconductor stack using chemical mechanical planarization (CMP) or other suitable semiconductor fabrication techniques (e.g., ...). Figure 4 The top surface of the hard mask 535 (shown as 402). Subsequent photolithography material 536 (e.g., the hard mask) can be deposited using CVD and planarized using CMP to cover and close the first vertical openings 512 on the conductive materials 540-1, 540-2, ..., 540-4. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing process described herein.

[0081] Figure 6A Examples of methods for forming a vertically stacked memory cell array having horizontally oriented access means and vertically oriented access lines, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 6A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 6A In one example embodiment, the method includes patterning a photomask 636 using a photolithography process. Figure 6AThe method further illustrates the use of a selective isotropic etchant process to remove exposed conductive materials 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z ( Figure 5B The portion 540 is used to separate and form the plurality of individual vertical access lines 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z, for example, Figure 1A and 1B Access lines 107-1, 107-2, ..., 107-Q, etc. are shown. Therefore, the plurality of individual vertical access lines 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are shown as being along the sidewalls of an elongated vertical column, for example, in... Figure 5B In the cross-sectional view, along the sidewalls of the slender vertical column rows 542-1, 542-2 and 542-3.

[0082] like Figure 6A As shown in the examples, the exposed conductive materials 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z can be removed back to the first vertical opening using a suitable selective isotropic etching process (e.g., Figure 5A The gate dielectric material 638 in (512) is used. For example... Figure 6A As shown, a subsequent dielectric material (such as an oxide or other suitable spin dielectric (SOD)) of, for example, a third dielectric material 641 can then be deposited to fill the remaining openings that have been removed from the exposed conductive materials 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z using processes such as CVD or other suitable techniques. The dielectric material 641 can then be planarized to a vertical semiconductor stack (e.g., using processes such as CMP or other suitable techniques). Figure 4 The top surface of the previous hard mask 635 (shown as 402). In some embodiments, subsequent photolithography material 635 (e.g., hard mask) may be deposited using CVD and planarized using CMP to cover and enclose the vertical semiconductor stack (e.g., Figure 4The plurality of individual vertical access lines 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z on the working surface of 402 are such that the plurality of individual vertical access lines 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1) and 640-Z are protected along the sidewalls of the elongated vertical column array. However, the embodiments are not limited to these process examples.

[0083] Figure 6B Show along Figure 6A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example embodiment of the present disclosure. Figure 6B The cross-sectional view shown is away from the plurality of individual vertical access lines 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1), and shows a vertical stack formed on the semiconductor substrate 600 (e.g., Figure 4 The alternating layers of the first dielectric material 630-1, 630-2, ..., 630-N, the sacrificial semiconductor material 632-1, 632-2, ..., 632-N, and the second dielectric material 633-1, 633-2, ..., 633-N are repeatedly iterated. For example... Figure 6B As shown, the vertical direction 611 is indicated as the third direction (D3), for example, the z-direction in the xyz coordinate system, similar to the third direction (D3) 111 among the first, second, and third directions shown in Figures 1-3. The plane extending left and right in the drawing is on the first direction (D1) 609. Figure 6B In an example embodiment, dielectric material 641 is shown as filling a vertical opening in the remaining gate dielectric 638 deposited on the sidewalls of elongated vertical columns 643-1, 642-2, and 642-3. The hard mask 636 described above covers the structure shown.

[0084] Figure 6C Show along Figure 6A The cross-sectional view obtained by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 6CThe cross-sectional view shown illustrates an axis extending in a second direction (D2) 605 along the repeating iterations of alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, sacrificial semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N. Horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed along said axis and within the layers of sacrificial semiconductor materials 632-1, 632-2, ..., 632-N. Figure 6C In the drawing, adjacent and opposite vertical access lines 640-3 are shown as dashed lines, indicating the position set from the plane and orientation of the drawing.

[0085] Figure 6D Show along Figure 6A The cross-sectional view obtained by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 6D The cross-sectional view shown illustrates the axis of repeated iterations along alternating layers of first dielectric material 630-1, 630-2, ..., 630-N, sacrificial semiconductor material 632-1, 632-2, ..., 632-N, and second dielectric material 633-1, 633-2, ..., 633-N, extending in a second direction (D2) 605 outside the regions where horizontally oriented access devices and horizontally oriented memory nodes (e.g., capacitor cells) will be formed within the layers of sacrificial semiconductor material 632-1, 632-2, ..., 632-N. Figure 6C In the drawing, dielectric material 641 is shown as filling the space between horizontally oriented access devices and horizontally oriented memory nodes spaced apart along a first direction (D1) in a three-dimensional array of vertically oriented memory cells, extending in and out of the drawing plane. At the left end of the drawing is shown a repeated iteration of alternating layers of first dielectric materials 630-1, 630-2, ..., 630-N, sacrificial semiconductor materials 632-1, 632-2, ..., 632-N, and second dielectric materials 633-1, 633-2, ..., 633-N, where horizontally oriented digital lines (e.g., digital lines 107-1, 107-2, ..., 107-P, etc. shown in FIG. 1) can be integrated to form electrical contacts with a second source / drain, as described in more detail below.

[0086] Figure 6E Show along Figure 6A The cross-sectional view obtained by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 6EThe cross-sectional view shown in the drawing plane, from right to left, extends along the first direction (D1) 609 along the axis of repeated iterations of the first dielectric materials 630-1, 630-2, ..., 630-N, the sacrificial semiconductor materials 632-1, 632-2, ..., 632-N, and the second dielectric materials 633-1, 633-2, ..., 633-N, across the plurality of individual vertical access lines 640-1, 640-2, ..., 640-( Intersecting with N-1), 640-N, 640-(N+1), ..., 640-(Z-1), and intersecting with the regions of the sacrificial semiconductor materials 632-1, 632-2, ..., 632-N that can form channel regions, said regions being separated from the plurality of individual vertical access lines 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1) by gate dielectric 638. Figure 6E In the diagram, a third dielectric material 641 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented memory nodes, which may be formed to extend in and out of the drawing plane, as described in more detail below, and may be spaced apart along a first direction (D1) 609 and vertically stacked in a three-dimensional (3D) memory as an array extending in a third direction (D3) 611.

[0087] Figure 7A Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 7A A cross-sectional view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 7A Show along Figure 7B The cross-sectional view obtained by cutting line A-A' in the image. Similar to the reference. Figure 5A The method for forming a vertically stacked memory cell array having horizontally oriented access devices and horizontally oriented memory nodes includes depositing layers of first dielectric material 730-1, 730-2, 730-3, ..., 730-N (respectively or collectively referred to as first dielectric material 730), semiconductor material 732-1, 732-2, 732-3, ..., 732-N (respectively or collectively referred to as sacrificial semiconductor material 732), and second dielectric material 733-1, 733-2, 733-3, ..., 733-N (respectively or collectively referred to as second dielectric material 733) in repeated iterations to form a vertical stack, for example, Figure 4The vertical stack 402 is formed in repeated iterations of a first dielectric material 730, a semiconductor material 732, and a second dielectric material 733 to form a vertical stack. This may include depositing an oxide material as the first dielectric material 730, depositing a polysilicon material as the semiconductor material 732, and depositing a nitride material as the second dielectric material 733. However, the embodiments are not limited to this example. Other suitable materials that can be selectively etched toward each other accordingly may be used.

[0088] like Figure 7A As shown, a photomask (e.g., mask material 735) may be deposited on a vertical stack. An etchant process may be used to remove portions of the mask material 735 to form openings 758 within the mask material 735. Adjacent and opposite vertical access lines 740 are shown as dashed lines, indicating their positions set from the plane and orientation of the drawing.

[0089] Figure 7B Show Figure 7A A top view of the semiconductor structure shown. Figure 7B As shown, portions of the mask material 735 have been patterned and etched to expose the plurality of vertically stacked structures (e.g., Figure 4 The elongated vertical column portion of the vertical stack 402) and the third dielectric material 741 (e.g., Figure 6E The third dielectric material 641). The top of the slender vertical column in the vertical stack is at Figure 7B The second dielectric layer 733-N, shown as the top layer, and the dashed lines representing each vertical stack, are illustrated. The third dielectric material 741 is shown in the exposed portions deposited between iterations of the vertical stacks. Figure 7B As shown, multiple portions of mask material 735 can be removed from the top portion of the vertically stacked mask material 735 to form patterned openings 758 in the mask material 735. The patterned openings 758 in the mask material may have a first horizontal direction (D1) 709 and a second horizontal direction (D2) 705, and extend primarily in the first horizontal direction (D1) 709. The multiple openings 758 in the mask material 735 may extend parallel to each other primarily in the first horizontal direction (D1) 709. At this stage of the semiconductor manufacturing process, the portion of the hard mask material 735 above the vertical conductive line 740 has not yet been removed.

[0090] Figure 7C Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 7C Show along Figure 7DThe cross-sectional view taken along the cutting line C-C' shows another view of the semiconductor structure at this specific point in the semiconductor manufacturing process of an embodiment of this disclosure. At this stage of the semiconductor manufacturing process, the method for forming a vertically stacked memory cell array includes forming a plurality of second vertical openings (e.g., in a third dielectric material) Figure 7D The second vertical opening 749 shown exposes the second vertical sidewall 745 in the vertical stack. In some embodiments, the second vertical opening may extend downward to the bottom first dielectric layer 730-1. In other embodiments, the second vertical opening may extend downward to the substrate 700. The second vertical opening may be formed between elongated vertical columns.

[0091] Figure 7D Show Figure 7A A top view of the semiconductor structure shown. Figure 7D As shown, a second vertical opening 749 may be formed in a portion of the vertically stacked memory cell array not covered by the mask material 735. In some embodiments, the second vertical opening 749 may be formed by selectively etching a third dielectric material (e.g., ...) via selective etching. Figure 7B The third dielectric material 741 is formed. Selective etching may be selective for the first dielectric material 730, the semiconductor material 732, and the second dielectric material 733, for example, not etching them. The second vertical opening 749 forms a non-solid space between each stack of the first dielectric material 730, the semiconductor material 732, and the second dielectric material 733 in each repeated iteration.

[0092] Figure 8A Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 8A Show along Figure 8B The cross-sectional view taken along line A-A' in Figure 7 shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. At this stage of the semiconductor manufacturing process, the method for forming a vertically stacked memory cell array includes forming a plurality of first horizontal openings 831-1, 831-2 (each or collectively referred to as first horizontal opening 831) in a layer of semiconductor material 832. Other components listed may be similar to those shown and discussed in conjunction with Figure 7.

[0093] The plurality of first horizontal openings 831 may include a first plurality of first horizontal openings 831-1 and a second plurality of first horizontal openings 831-2. For example... Figure 8AAs shown, the first plurality of first horizontal openings 831-1 are vertically aligned with each other, and the second plurality of first horizontal openings 831-2 are vertically aligned with each other. The first plurality of first horizontal openings 831-1 can extend parallel to the second plurality of first horizontal openings 831-2 into and out of the drawing plane. Furthermore, as... Figure 8A As shown, the first plurality of first horizontal openings 831-1 and the second plurality of first horizontal openings 831-2 contain the same number of horizontal openings.

[0094] In some embodiments, a method of forming vertically stacked memory cells may include laterally etching the plurality of first horizontal openings 831 through the plurality of second vertical openings formed by exposing a third dielectric material onto opposite sides of the semiconductor material 832. Figure 8A As shown, the first plurality of first horizontal openings 831-1 are formed below one opening in the mask material 835, and the second plurality of first horizontal openings 831-2 are formed below another opening in the mask material 835. In some embodiments, at least one layer of dielectric material (e.g., first dielectric material 830 and second dielectric material 833) may separate each horizontal opening in the first plurality of first horizontal openings 831-1 and each horizontal opening in the second plurality of first horizontal openings 831-2.

[0095] Furthermore, a portion of the semiconductor material 832 may separate the first plurality of first horizontal openings 831-1 and the second plurality of first horizontal openings 831-2. The portion of the semiconductor material 832 separating the first plurality of first horizontal openings 831-1 and the second plurality of first horizontal openings 831-2 may be below a portion of the mask material 835 and vertically aligned with said portion. In some embodiments, the first horizontal opening 831 may be formed in the portion of the semiconductor material 832 corresponding to the second vertical opening 849. In other words, the first horizontal opening 831 may be formed in the portion of the semiconductor material 832 adjacent to the second vertical opening 849.

[0096] Figure 8B Show Figure 8A The diagram shows a top view of the semiconductor structure. Figure 8B Each layer of the second dielectric material 833-N shown is a repeated iteration of the first dielectric material 830, the semiconductor material 832, and the second dielectric material 833 (e.g., Figure 4 The top layer of the vertically stacked 402). The lateral etching used to form the first horizontal opening 831 may be selective for the first dielectric material 830 and the second dielectric material 833, for example, without intending to remove them. See reference Figure 8AThe lateral etching can be performed on the semiconductor material 832 through a second vertical opening 849 of the semiconductor material 832 from opposite sides with exposed vertical sidewalls. The opposite sides of the semiconductor material can be the sidewalls of the semiconductor material 832 adjacent to each of the second vertical openings 849. In some embodiments, the lateral etching can be performed simultaneously on opposite sides of the semiconductor material 832. Figure 8B The diagram shows a lateral etching that forms the plurality of first horizontal openings 831 in each layer of semiconductor material 832 and extends completely through the vertically stacked elongated columnar columns of semiconductor material 832.

[0097] Figure 9A Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 9A Show along Figure 9B The cross-sectional view taken along cutting line A-A' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. At this stage of the semiconductor manufacturing process, the method for forming a vertically stacked memory cell array includes depositing fill materials 934-1, 934-2 (respectively or collectively referred to as fill material 934) to occupy the plurality of first horizontal openings (e.g., in the elongated vertical column array 542 in FIG. 5) in the elongated vertical column array (e.g., in the elongated vertical column array 542 in FIG. 5). Figure 8A The first horizontal opening 831 shown.

[0098] The filler material 934 may be composed of at least one of various materials. For example, in some embodiments, the filler material 934 may be silicon (Si). In some embodiments, the filler material 934 may be germanium (Ge). Furthermore, in some embodiments, the filler material 934 may be selective for the semiconductor material 932.

[0099] In some embodiments, a method of forming a vertically stacked memory cell array includes a doped filler material 934. The doped filler material 934 may dope a portion of a semiconductor material 932. For example, dopants deposited in the filler material 934 may migrate from the filler material 934 to the semiconductor material 932. For instance, the doped filler material may be annealed to migrate dopants (e.g., p-type dopants (boron atoms)) to the source / drain regions 978 of the semiconductor material 932. This dopant migration may allow the semiconductor material 932 to be doped after the filler material 934 has been deposited. Other components listed may be similar to those shown and discussed in conjunction with Figure 8.

[0100] Figure 9B Show Figure 9A A top view of the semiconductor structure shown. Figure 9BAs shown, the second vertical opening 949 separates the repeated iterations of the first dielectric material 930, the semiconductor material 932, and the second dielectric material 933. An opening 958 in the mask material may have a first horizontal direction (D1) 909 and a second horizontal direction (D2) 905, and extends primarily along the first horizontal direction (D1) 909. A second horizontal opening may have a first horizontal direction (D1) 909 and a second horizontal direction (D2) 905, and extends primarily along the second horizontal direction (D2) 905. The filler material 934 may be selectively etched to remove the filler material 934 from the second vertical opening 949, as... Figure 9C This is further illustrated in the text.

[0101] Figure 9C Show along Figure 9B The cross-sectional view obtained by cutting line B-B' shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example embodiment of this disclosure. Figure 9C As shown, multiple stacks of the first dielectric material 930, the filler material 934, and the second dielectric material 933, which are repeatedly iterated, can be separated by a second vertical opening 949. The second vertical opening 949 can be formed on the opposite sides of an elongated vertical column of each stack (e.g., a vertical stack) of the first dielectric material 930, the filler material 934, and the second dielectric material 933, which extends in and out of the drawing plane.

[0102] Figure 9D Show along Figure 9B The cross-sectional view obtained by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 9D This diagram illustrates multiple iterative stacks of a first dielectric material 930, a semiconductor material 932, and a second dielectric material 933, separated by a third dielectric material 941. It also shows portions of the mask material 935 deposited on the first dielectric material 930, the semiconductor material 932, the second dielectric material 933, and the third dielectric material 941. Figure 9D In the illustrated embodiment, a third dielectric material is deposited downwards to the bottom of the first dielectric material 930-1 because the second vertical opening extends downwards to the bottom of the first dielectric layer 930-1.

[0103] Figure 9E Examples of methods for forming a vertically stacked memory cell array with horizontal access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 9E Show along Figure 9FThe cross-sectional view taken by the cutting line D-D' shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. At this stage of the semiconductor manufacturing process, the mask material 935 can be removed from the first dielectric material 930, the semiconductor material 932, and the second dielectric material 933 through repeated iterations for further processing.

[0104] Figure 9F Show Figure 9E The diagram shows a top view of the semiconductor structure. Figure 9F In this process, the vertical conductive line 940 and the repeated iterative portions of the first dielectric material 930, semiconductor material 932, and second dielectric material 933 are no longer covered by the mask material 935. For example... Figure 9F As shown, a fourth dielectric material 947 has been deposited in the second vertical opening 949 to fill the second vertical opening 949. In some embodiments, such as Figure 9F As shown, the fourth dielectric material 947 can be the same dielectric material as the third dielectric material, and is therefore shown entirely as the fourth dielectric material 947 for clarity. Figure 9F The diagram further illustrates that any portion of the third dielectric material 941 retained after the formation of the second vertical opening 949 can be removed and replaced with a fourth dielectric material 947. In some embodiments, the fourth dielectric material 947 may be the same material as at least one of the first dielectric material 930, the second dielectric material 933, or the third dielectric material 941. In some embodiments, the fourth dielectric material 947 is a material different from the first dielectric material 930, the second dielectric material 933, and the third dielectric material 941. The fourth dielectric material 947 may be deposited to electrically isolate each stack of the first dielectric material 930, the semiconductor material 932, and the second dielectric material 933 in repeated iterations.

[0105] Figure 10A Examples of methods for forming a vertically stacked memory cell array having horizontally oriented access means and horizontally oriented memory nodes, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 10A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 10A In an example embodiment, the method includes patterning photomasks 1035, 1036 and / or 1037 using a photolithography process. Figure 10A The method further illustrates the use of one or more etchant processes in the memory node region 1050 (and Figure 10A and 10C In 1044), a vertical stack is formed (e.g., Figure 4Vertical openings 1051, 1051-1, 1051-N, 1051-(N+1), 1051-(Z-1), and 1051-Z are formed by vertical stacking (402) and extending primarily in the first horizontal direction (D1) 1009. The one or more etchant processes form the vertical openings 1051 to expose... Figure 10B-10E The vertically stacked layers shown depict alternating layers of first dielectric material 1030-1, 1030-2, ..., 1030-N, semiconductor material 1032-1, 1032-2, ..., 1032-N, and second dielectric material 1033-1, 1033-2, ..., 1033-N, with the third sidewall of the second region adjacent to the semiconductor material. Other components listed may be similar to those shown and discussed in conjunction with Figure 6.

[0106] In some embodiments, this process is combined Figure 7A-9F The semiconductor manufacturing process described is executed afterward. Figure 10B-10E The illustrated embodiment shows the sequence in which the memory node manufacturing process (e.g., performing digital line formation first) is performed "after" the formation of digital line 1077 and the first source / drain region. Here, digital line 1077 can be shown as along the plurality of individual vertical access lines 1040.

[0107] according to Figure 10B-10E The example embodiment shown includes a method comprising vertical stacking (e.g., Figure 4 In section 402), a third vertical opening 1051 is formed, and the second regions of semiconductor materials 1032-1, 1032-2, ..., 1032-N are selectively etched (e.g., ...). Figure 10C The second zone 1044) is formed with vertical stacking (e.g., Figure 4 A second horizontal opening 1079 is located behind the vertical opening 1051 in 402) and separated by a first horizontal distance (D1 opening). In some embodiments, the first horizontal distance (D1 opening) is in the range of two hundred (200) to three hundred (300) nanometers (nm). According to an embodiment, selectively etching the second region 1044 of the semiconductor materials 1032-1, 1032-2, ..., 1032-N may include using an atomic layer etching (ALE) process. As will be combined Figure 10C To further explain, a second source / drain region 1078 can be formed at the far end of the second horizontal opening 1079 relative to the vertical opening in semiconductor materials 1032-1, 1032-2, ..., 1032-N.

[0108] Figure 10B Show along Figure 10A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example embodiment of the present disclosure. Figure 10B The cross-sectional view shown is away from the plurality of individual vertical access lines 1040-1, 1040-2, ..., 1040-N, 1040-(N+1), ..., 1040-(Z-1), and shows the repeated iteration of alternating layers of vertically stacked dielectric materials 1030-1, 1030-2, ..., 1030-N, semiconductor materials 1032-1, 1032-2, ..., 1032-N, and second dielectric materials 1033-1, 1033-2, ..., 1033-N separated by a third dielectric 1041, formed on a semiconductor substrate 1000. Figure 10B As shown, the vertical direction 1011 is indicated as the third direction (D3), for example, the z-direction in the xyz coordinate system, similar to the third direction (D3) 111 among the first, second, and third directions shown in Figures 1-3. The plane extending left and right in the drawing is on the first direction (D1) 1009. Figure 10B In an example embodiment, the materials within the vertical stack—dielectric materials 1030-1, 1030-2, ..., 1030-N, semiconductor materials 1032-1, 1032-2, ..., 1032-N, and second dielectric materials 1033-1, 1033-2, ..., 1033-N—extend in the second direction (D2) and along the oriented axis of the horizontal access device and horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory to the plane of the drawing.

[0109] Figure 10C Show along Figure 10A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. At this stage of the semiconductor manufacturing process, the method of forming a vertically stacked memory array may include forming a third vertical opening 1051 to expose a third vertical sidewall of a memory node region (e.g., a second region) 1044 adjacent to the vertical stack. Furthermore, at this stage of the semiconductor manufacturing process, the method of forming a vertically stacked memory array may include selectively removing filler material (e.g., filler material 934 in FIG. 9) along a second horizontal direction (D2) 1005 to form a plurality of second horizontal openings 1079 in which horizontally oriented memory nodes are to be formed. In some embodiments, the method for forming a vertically stacked memory cell array may include selectively removing filler material (e.g., by selective etching) via selective etching. Figure 9A The filling material 934 shown is used to form the plurality of second horizontal openings 1079.

[0110] Furthermore, the method of forming a vertically stacked memory cell array may include removing the fill material by forming the second horizontal opening 1079 without using a timed-dig process. Using selective etching to remove the fill material instead of using a timed-dig etching process (e.g., timed etching) to remove the semiconductor material 1032 to form the second horizontal opening 1079 can be advantageous for vertically stacked memory cell arrays. Using timed etching to form the second horizontal opening 1079 can cause the second horizontal opening 1079 to unintentionally have different horizontal distances (D1 openings) in different layers of the semiconductor material 1032. For example, using timed etching to form the second horizontal opening 1079 can cause the horizontal distance (D1 opening) of the second horizontal opening 1079 in a higher (e.g., later formed) layer of the semiconductor material 1032 to be greater than the horizontal distance (D1 opening) of the second horizontal opening 1079 in a lower (e.g., earlier formed) layer of the semiconductor material 1079. This difference in the horizontal distance (D1 opening) of the second horizontal opening 1079 can degrade the performance of the vertically stacked memory cell array. For example, non-uniformity in the size and surface area of ​​the capacitors formed as storage nodes can lead to variations in the magnitude of charge storage capacity. Unexpected changes in charge storage can lead to inaccurate memory cell reads and / or device performance failures.

[0111] Forming the second horizontal opening 1079 by selectively etching the filler material can mitigate the performance degradation caused by forming the second horizontal opening 1079 using timed etching by forming the second horizontal opening 1097 with the same or substantially the same horizontal distance (D1 opening) in different layers of the semiconductor material 1032. The second horizontal opening 1079 can be formed with substantially the same horizontal distance (D1 opening) because the second horizontal opening 1079 is formed by removing the filler material via selective etching. This allows the semiconductor material 1032 to be used as an etch stop layer. As used herein, the term "etch stop layer" refers to material that has not been removed by etching. Selective etching removes the filler material, but stops material removal after all filler material has been removed and the semiconductor material 1032 remains. This allows for greater control when using selective etching instead of timed etching, because selective etching only removes the filler material and stops material removal after all filler material has been removed. Figure 10CThe cross-sectional view shown indicates that the axis of repeated iterations along the alternating layers of the first dielectric material 1030-1, 1030-2, ..., 1030-N, the semiconductor material 1032-1, 1032-2, ..., 1032-N, and the second dielectric material 1033-1, 1033-2, ..., 1033-N extends left and right along the drawing plane in the second direction (D2) 1005. Horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed along said axis and within the layers of semiconductor material 1032-1, 1032-2, ..., 1032-N.

[0112] exist Figure 10C In an example embodiment, the third vertical opening 1051 and the second horizontal opening 1079 are shown as being combined Figure 10A The mask patterning and etching processes described are formed. For example... Figure 10C As shown, semiconductor materials 1032-1, 1032-2, ..., 1032-N in the second region 1044 have been selectively removed to form a horizontal opening 1079. In one example, the semiconductor materials 1032-1, 1032-2, ..., 1032-N are selectively etched using an atomic layer etching (ALE) process, and a second distance (D2 opening) is removed from behind the third vertical opening 1051. Horizontally oriented memory nodes (e.g., capacitor cells) can be positioned relative to the second horizontal opening 1079. Figure 7A-9F The manufacturing process shown is either formed later or first.

[0113] exist Figure 10C The diagram also shows that the first source / drain region 1075 can be formed by vapor-doping a dopant into the top surface portion of the semiconductor material 1032. In some embodiments, the first source / drain region 1075 may be adjacent to the vertical access line 1040-3. According to one example embodiment, such as Figure 10C As shown, the second source / drain region 1078 can be formed by flowing a high-energy vapor dopant (e.g., phosphorus (P) for n-type transistors) into the second horizontal opening 1079 to dope the semiconductor material 1032-1, 1032-2, ..., 1032-N at the distal end of the second horizontal opening 1079 relative to the vertical opening 1051. In one example, vapor doping can be used to achieve highly isotropic (e.g., non-directional) doping to form the second source / drain region 1078 into a horizontally oriented access device in region 1042. In another example, thermal annealing with a dopant gas (e.g., phosphorus) combined with a high-energy plasma is used to help break the bond. However, the embodiments are not limited to these, and other suitable semiconductor manufacturing techniques can be utilized.

[0114] Conductive material 1077 may be deposited adjacent to the second dielectric material 1033. Conductive material 1077 may maintain direct electrical contact with and be located on the top surface of the first source / drain region 1075. Thus, conductive material 1077 maintains electrical contact with the source / drain region 1075. In some embodiments, a fifth dielectric material 1074 may be located below the first dielectric material 1030, while maintaining direct contact with the conductive material 1077, the first source / drain region 1075, and a first portion of the lightly doped semiconductor material 1032. The fifth dielectric material 1074 may form direct electrical contact with a heavily doped p-type (p+) silicon material 1095 (e.g., a horizontally oriented body region contact of an access device).

[0115] As later Figure 11C As shown, the first electrode (e.g., 1161) of the horizontally oriented memory node is coupled to the second source / drain region 1078 of the horizontal access device. As will be discussed later... Figure 11C As shown, such horizontally oriented storage nodes are illustrated as being formed in a second horizontal opening 1079, which extends laterally in the drawing plane in a second direction (D2), unlike those formed in vertical stacks (e.g., Figure 4 The vertical openings 1051 in the vertical stack 402 of the three-dimensional (3D) memory cell array are separated by a second distance (D2 opening) and are aligned along the axis of the orientation of the horizontal access devices and horizontal storage nodes of the vertical stack memory cell array. Figure 10C In the drawing, adjacent and opposite vertical access lines 1040-3 are shown as dashed lines, indicating the position set inward from the plane and direction of the drawing.

[0116] Figure 10D Show along Figure 10A The cross-sectional view obtained by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 10DThe cross-sectional view shown illustrates that the axis of repeated iterations along the alternating layers of the first dielectric material 1030-1, 1030-2, ..., 1030-N, semiconductor material 1032-1, 1032-2, ..., 1032-N, and fifth dielectric material 1074 extends laterally in the drawing plane in the second direction (D2) 1005 to the horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) formed within the layers of semiconductor material 1032-1, 1032-2, ..., 1032-N, outside the regions therein. The left end of the drawing shows a repeated iteration of alternating layers of first dielectric material 1030-1, 1030-2, ..., 1030-N, semiconductor material 1032-1, 1032-2, ..., 1032-N, and fifth dielectric material 1074. At this location, horizontally oriented digital lines (e.g., digital lines 107-1, 107-2, ..., 107-P, etc. shown in Figure 1) can be integrated to form electrical contacts with the first source / drain region or the digital line conductive contact material.

[0117] Similarly, although the references to first and second source / drain regions are used in this paper to refer to two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" have any particular meaning. It is only desired that one source / drain region is connected to a digital line (e.g., 107-2), and the other can be connected to a memory node.

[0118] In some embodiments, conductive material 1077 may be shown adjacent to fifth dielectric material 1074. Conductive material 1077 may be adjacent to third dielectric material 1041. Body contact region 1095 may be shown as a repeated iteration along alternating layers of first dielectric material 1030-1, 1030-2, ..., 1030-N, semiconductor material 1032-1, 1032-2, ..., 1032-N and fifth dielectric material 1074.

[0119] Figure 10E Show along Figure 10A The cross-sectional view obtained by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 10EThe cross-sectional view shown in the drawing plane, from right to left, extends in a first direction (D1) 1009 along the axis of repeated iterations of alternating layers of the first dielectric material 1030-1, 1030-2, ..., 1030-N, semiconductor material 1032-1, 1032-2, ..., 1032-N, and second dielectric material 1033-1, 1033-2, ..., 1033-N. This axis crosses the plurality of individual vertical access lines 1040-1, 1040-2, ..., 1040-4 and intersects with regions of the semiconductor material 1032-1, 1032-2, ..., 1032-N where channel regions can be formed. These regions are separated from the plurality of individual vertical access lines 1040-1, 1040-2, ..., 1040-4 by a gate dielectric 1038. Figure 10E In the diagram, a third dielectric material 1041 is shown as a space separating adjacent horizontally oriented access devices, which may be formed to extend into and out of the drawing plane and may be spaced apart along a first direction (D1) 1009 and vertically stacked in a three-dimensional (3D) memory as an array extending in a third direction (D3) 1011.

[0120] Figure 11A Examples of methods for forming a vertically stacked memory cell array with horizontally oriented access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 11A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 11A In an example embodiment, the method includes using a photolithography process to etch photomasks 1135 and 1137 (e.g., Figures 6A-6E Patterning of 635 and 637 in the model. Figure 11A The method further illustrates the use of one or more etchant processes in memory node region 1150 (and Figure 11A and 11C Vertical openings 1151, 1151-1, 1151-2, 1151-3, 1151-N, 1151-(N+1), 1151-(Z-1), and 1151-Z are formed in 1144, the vertical openings passing through the vertical stack and extending primarily in the first horizontal direction (D1) 1109. The one or more etchant processes form the vertical openings 1151 to expose... Figure 11B-11EThe vertically stacked layers shown depict alternating layers of first dielectric material 1130-1, 1130-2, ..., 1130-N, sacrificial semiconductor material 1132-1, 1132-2, ..., 1132-N, and second dielectric material 1133-1, 1133-2, ..., 1133-N, with the third sidewall of the second region adjacent to the sacrificial semiconductor material. Other components listed may be similar to those shown and discussed in conjunction with Figure 6.

[0121] According to an embodiment, the second region of the sacrificial semiconductor materials 1132-1, 1132-2, ..., 1132-N can be removed from alternating layers of the first dielectric materials 1130-1, 1130-2, ..., 1130-N, the sacrificial semiconductor materials 1132-1, 1132-2, ..., 1132-N, and the second dielectric materials 1133-1, 1133-2, ..., 1133-N, and self-aligned memory nodes can be formed in elongated vertical columns of a vertically stacked memory cell array. In some embodiments, the self-aligned memory node can be a capacitor and has horizontally oriented bottom electrodes of equal length. In some embodiments, this process is performed before selectively removing the access device regions (e.g., transistor regions) of the first source / drain region, channel region, and second source / drain region in the sacrificial semiconductor material to form horizontally oriented access devices. In other embodiments, this process is performed after selectively removing the access device regions—the first source / drain region, the channel region, and the second source / drain region—from the sacrificial semiconductor material to form the horizontally oriented access devices. According to Figure 11B-11E The example embodiment shown includes a method that selectively etches a second region of sacrificial semiconductor material 1132-1, 1132-2, ..., 1132-N to form a second horizontal opening, for example, Figures 10A-10E The second horizontal opening 1079 in the vertical stack is separated from the rear of the vertical opening 1151 in the vertical stack by a first horizontal distance. In some embodiments, such as Figure 11B-11E As shown, the method includes forming a capacitor cell as a storage node in a second horizontal opening. The method may include forming a horizontally oriented storage node comprising a capacitor cell having a first horizontally oriented electrode 1161 electrically coupled to a first source / drain region 1178 of a horizontally oriented access device and a second horizontally oriented electrode 1156 separated from the first horizontally oriented electrode 1178 by a cell dielectric 1163. For example, but not as a limitation, forming the capacitor includes sequentially depositing the first electrode 1161 and the second electrode 1156 separated by the cell dielectric 1163 in the second horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor fabrication techniques and / or storage node structures may be used.

[0122] Figure 11BShow along Figure 11A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example embodiment of the present disclosure. Figure 11B The cross-sectional view shown is away from the plurality of individual vertical access lines 1140-1, 1140-2, ..., 1140-N, 1140-(N+1), ..., 1140-(Z-1) and shows repeated iterations of alternating layers of first dielectric material 1130-1, 1130-2, ..., 1130-N and second dielectric material 1133-1, 1133-2, ..., 1133-N, separated by horizontally oriented capacitor cells, formed vertically stacked on a semiconductor substrate 1100. The horizontally oriented capacitor cells have a first electrode 1161 (e.g., a bottom cell contact electrode), a cell dielectric 1163, and a second electrode 1156 (e.g., a top common node electrode). Figure 11B As shown, the vertical direction 1111 is indicated as the third direction (D3), for example, the z-direction in the xyz coordinate system, similar to the third direction (D3) 111 among the first, second, and third directions shown in Figures 1-3. The plane extending left and right in the drawing is on the first direction (D1) 1109. Figure 11B In an example embodiment, the first electrode 1161 (e.g., the bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 1156 are shown separated by a cell dielectric material 1163 extending in a second direction (D2) and along the oriented axis of the vertically stacked memory cell array of the three-dimensional (3D) memory, both within and outside the drawing plane. In some embodiments, self-aligned memory nodes may be formed in a plurality of first horizontal openings formed by a selective etching process.

[0123] Figure 11C Show along Figure 11A The cross-sectional view obtained by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 11CThe cross-sectional view shown illustrates a repeating iterative axis along alternating layers of first dielectric material 1130-1, 1130-2, ..., 1130-N, sacrificial semiconductor material 1132-1, 1132-2, ..., 1132-N, and second dielectric material 1133-1, 1133-2, ..., 1133-N, extending laterally along the drawing plane in the second direction (D2) 1105. Horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) may be formed along said axis and within the layers of sacrificial semiconductor material 1132-1, 1132-2, ..., 1132-N. Figure 11C In an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is shown as having been formed during this semiconductor fabrication process, and a first electrode 1161 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and a second electrode 1156 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 1163 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 1161 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 1156 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by a cell dielectric 1163 may be formed after the first source / drain region, the channel region, and the second source / drain region are formed in regions of sacrificial semiconductor material 1132-1, 1132-2, ..., 1132-N, intended to position the horizontally oriented access device (e.g., to house its formation), which will be described subsequently.

[0124] exist Figure 11C In an example embodiment, a horizontally oriented memory node having a first electrode 1161 (e.g., a bottom electrode coupled to the source / drain region of a horizontal access device) and a second electrode 1156 (e.g., a top electrode coupled to a common electrode plane, such as a ground plane) is shown formed in a second horizontal opening that extends laterally in a second direction (D2) on the drawing plane, is separated from a vertical opening formed in a vertical stack by a second distance, and is along the orientation axis of the horizontal access device and the horizontal memory node of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 11C In the drawing, adjacent and opposite vertical access lines 1140-3 are shown as dashed lines, indicating the positions set inward from the plane and orientation of the drawing.

[0125] Figure 11D Show along Figure 11A The cross-sectional view obtained by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 11DThe cross-sectional view shown illustrates the recurring iterative axis along the second direction (D2) 1105 in the drawing plane, extending laterally to the horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) formed within the layers of sacrificial semiconductor materials 1130-1, 1130-2, ..., 1130-N, 1130-N, 1132-1, 1132-2, ..., 1132-N, and the fifth dielectric material 1174. Figure 11C In the diagram, a third dielectric material 1141 is shown filling the space between horizontally oriented access devices spaced apart along a first direction (D1) in a three-dimensional array of vertically oriented memory cells, extending both inside and outside the drawing plane. However, in Figure 11D In the cross-sectional view, a second electrode 1156 (e.g., the top common electrode of a capacitor cell structure) is also shown existing in the space between horizontally adjacent devices. At the left end of the drawing, a repetitive iteration of alternating layers of dielectric materials 1130-1, 1130-2, ..., 1130-N, sacrificial semiconductor materials 1132-1, 1132-2, ..., 1132-N, and a fifth dielectric material 1174 is shown, in which horizontally oriented digital lines (e.g., digital lines 107-1, 107-2, ..., 107-P, etc. shown in FIG. 1) can be integrated to form electrical contacts with the second source / drain region, which is described in more detail below.

[0126] Figure 11E Show along Figure 11A The cross-sectional view obtained by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 11E The cross-sectional view shown in the drawing plane, from right to left, extends in a first direction (D1) 1109 along the axis of repeated iterations of alternating layers of dielectric materials 1130-1, 1130-2, ..., 1130-N, sacrificial semiconductor materials 1132-1, 1132-2, ..., 1132-N, and third dielectric materials 1133-1, 1133-2, ..., 1133-N, intersecting the plurality of individual vertical access lines 1140-1, 1140-2, ..., 1140-4, and intersecting with regions of sacrificial semiconductor materials 1132-1, 1132-2, ..., 1132-N where channel regions can be formed, said regions being separated from the plurality of individual vertical access lines 1140-1, 1140-2, ..., 1140-4 by gate dielectric 1138. Figure 11EIn the diagram, a third dielectric filling material 1141 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented memory nodes, which may be formed to extend into and out of the drawing plane, as described in more detail below, and may be spaced apart along a first direction (D1) 1109 and vertically stacked in a three-dimensional (3D) memory as an array extending in a third direction (D3) 1111.

[0127] Figure 12A Examples of methods for forming a vertically stacked memory cell array with horizontally oriented access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 12A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 12A In an example embodiment, the method includes patterning photomasks 1235, 1236 and / or 1237, etc., using a photolithography process, as described in Figures 6 and 7. Figure 12A The method further illustrates the use of one or more etchant processes in the access device (e.g., transistor) region (e.g., Figure 7C Access device area 742 and Figure 12C Vertical openings 1271-1 and 1271-2 are formed in 1242) to replace the channel and source / drain transistor regions and extend through the vertical stack. Vertical openings 1271-1 and 1271-2 are shown extending primarily in the first horizontal direction (D1) 709. The one or more etchant processes form the vertical openings 1271-1 and 1271-2 to expose... Figure 12B-12E The third sidewall of the first region adjacent to the sacrificial semiconductor material is shown in the repeating iterations of alternating layers of the first dielectric material 1230-1, 1230-2, ..., 1230-N, the sacrificial semiconductor material 1232-1, 1232-2, ..., 1232-N, and the gate dielectric 1238 in the vertically stacked arrangement. Other components listed may be similar to those shown and discussed in conjunction with Figures 6 and 7.

[0128] According to an embodiment, the access device (e.g., transistor) region (e.g., ..., 1232-N) of the sacrificial semiconductor material 1232-1, 1232-2, ..., 1232-N Figure 12A and 12CThe access device region 1242 in the memory can be repeatedly and iteratively removed from alternating layers of dielectric materials 1230-1, 1230-2, ..., 1230-N, sacrificial semiconductor materials 1232-1, 1232-2, ..., 1232-N, and gate dielectric 1238 in a vertically stacked manner to form an access device, such as a transistor. In some embodiments, this process is performed before the memory node region in the sacrificial semiconductor material to be formed into a capacitor cell is selectively removed. In other embodiments, this process is performed after the memory node region in the sacrificial semiconductor material to be formed into a capacitor cell is selectively removed. Figure 12B-12E The illustrated example embodiment includes a method that selectively etches access device regions of sacrificial semiconductor materials 1232-1, 1232-2, ..., 1232-N to form a horizontal opening 1216, said horizontal opening being separated from the rear of vertical openings 1271-1 and 1271-2 in a vertical stack by a second horizontal distance (D2 opening). In some embodiments, such as Figure 12B-12E As shown, the method includes forming a transistor having a first source / drain region, a channel region, and a second source / drain region as an access device in a first horizontal opening. For example, but not as a limitation, forming the first source / drain region, the channel region, and the second source / drain region includes sequentially depositing the first source / drain region, the channel region, and the second source / drain region in the first horizontal opening using an atomic layer deposition (ALD) process. Other suitable semiconductor manufacturing techniques and / or memory node structures can be used.

[0129] Figure 12B Show along Figure 12A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example embodiment of the present disclosure. Figure 12B The cross-sectional view shown is away from the plurality of individual vertical access lines 1240-1, 1240-2, ..., 1240-N, 1240-(N+1), ..., 1240-(Z-1) and shows repeated iterations of alternating layers of first dielectric material 1230-1, 1230-2, ..., 1230-N and second dielectric material 1233-1, 1233-2, ..., 1233-N, separated by capacitor cells, formed vertically stacked on a semiconductor substrate 1200. The capacitor cells have a first electrode 1261 (e.g., a bottom cell contact electrode), a cell dielectric 1263, and a second electrode 1256 (e.g., a top common node electrode). Figure 12BAs shown, the vertical direction 1211 is indicated as the third direction (D3), for example, the z-direction in the xyz coordinate system, similar to the third direction (D3) 111 among the first, second, and third directions shown in Figures 1-3. The plane extending left and right in the drawing is on the first direction (D1) 1209. Figure 12B In an example embodiment, the first electrode 1261 (e.g., the bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 1256 are shown separated by a cell dielectric material 1263 that extends in a second direction (D2) and along the oriented axis of the horizontal access device and horizontal memory node of the vertically stacked memory cell array of the three-dimensional (3D) memory, both inside and outside the drawing plane.

[0130] Figure 12C Show along Figure 12A The cross-sectional view obtained by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 12C The cross-sectional view shown depicts an axis extending laterally along the drawing plane in a second direction (D2) 1205, representing the repeated iterations of alternating layers of first dielectric materials 1230-1, 1230-2, ..., 1230-N and second dielectric materials 1233-1, 1233-2, ..., 1233-N. However, it is now shown that sacrificial semiconductor material has been removed from the access device region 1242 of the vertically stacked alternating layers to form horizontal openings 1216-1, 1216-2, ..., 1216-N, wherein horizontally oriented access devices having first source / drain regions, channel regions, and second source / drain regions can be formed between the vertically alternating layers of first dielectric materials 1230-1, 1230-2, ..., 1230-N and second dielectric materials 1233-1, 1233-2, ..., 1233-N. Figure 12CIn an example embodiment, a horizontally oriented memory node (e.g., a capacitor cell) is shown formed in memory node region 1244 during the semiconductor fabrication process, and a first electrode 1261 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and a second electrode 1256 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by cell dielectric 1263 are shown. However, the embodiments are not limited to this example. In other embodiments, the first electrode 1261 (e.g., a bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 1256 (e.g., a top electrode to be coupled to a common electrode plane, such as a ground plane) separated by cell dielectric 1263 may be formed after the first source / drain region, the channel region, and the second source / drain region are formed in regions of sacrificial semiconductor material 1232-1, 1232-2, ..., 1232-N.

[0131] exist Figure 12C In an example embodiment, the horizontal openings 1216-1, 1216-2, ..., 1216-N, which form access devices having a first source / drain region, a channel region, and a second source / drain region, are shown extending laterally in the drawing plane along a second direction 1205 (D2), spaced a certain distance from the vertical openings 1271-1 and 1271-2 formed in the vertical stack, and along the axis of orientation of the horizontal access devices and horizontal memory nodes of the vertically stacked memory cell array of the three-dimensional (3D) memory. Figure 12C In the drawing, adjacent and opposite vertical access lines 1240-3 are shown as dashed lines, indicating the positions set inward from the plane and orientation of the drawing.

[0132] Figure 12D Show along Figure 12A The cross-sectional view obtained by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 12D The cross-sectional view shown is illustrated by an axis of repeated iterations along alternating layers of the first dielectric material 1230-1, 1230-2, ..., 1230-N, horizontal openings 1216-1, 1216-2, ..., 1216-N, and the second dielectric material 1233-1, 1233-2, ..., 1233-N, extending laterally in the drawing plane in the second direction (D2) 1205 outside the area where horizontally oriented access devices and horizontally oriented storage nodes (e.g., capacitor cells) will be formed. Figure 12D In the diagram, a third dielectric material 1241 is shown filling the space between horizontally oriented access devices spaced apart along a first direction (D1) in a three-dimensional array of vertically oriented memory cells, extending in and out of the drawing plane. However, in Figure 12D In the cross-sectional view, a second electrode 1256 (e.g., the top common electrode of a capacitor cell structure) is also shown existing in the space between horizontally adjacent devices. At the left end of the drawing, a repeated iteration of alternating layers of first dielectric materials 1230-1, 1230-2, ..., 1230-N, horizontal openings 1216-1, 1216-2, ..., 1216-N, and second dielectric materials 1233-1, 1233-2, ..., 1233-N is shown, in which horizontally oriented digital lines (e.g., digital lines 107-1, 107-2, ..., 107-P, etc. shown in FIG. 1) can be integrated to form electrical contacts with the second source / drain regions that form the horizontal access devices.

[0133] Figure 12E Show along Figure 12A The cross-sectional view obtained by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 12E The cross-sectional view shown in the drawing plane, from right to left, extends along the axis of repeated iterations of alternating layers of the first dielectric material 1230-1, 1230-2, ..., 1230-N, horizontal openings 1216-1, 1216-2, ..., 1216-N, and the second dielectric material 1233-1, 1233-2, ..., 1233-N, in a first direction (D1) 1209, wherein the channel region will be formed to be separated from the plurality of individual vertical access lines 1240-1, 1240-2, ..., 1240-4 by the gate dielectric 1238. Figure 12E In the diagram, a third dielectric material 1241 is shown as separating the space between adjacent horizontally oriented access devices and horizontally oriented memory nodes, which may be formed to extend in and out of the drawing plane, as described in more detail below, and may be spaced apart along a first direction (D1) 1209 and vertically stacked in a three-dimensional (3D) memory as an array extending in a third direction (D3) 1211.

[0134] Figure 13A Examples of methods for forming a vertically stacked memory cell array with horizontally oriented access means, according to several embodiments of the present disclosure, are shown at another stage of the semiconductor manufacturing process. Figure 13A A top view of a semiconductor structure at a specific point in time during the semiconductor manufacturing process, according to one or more embodiments. Figure 13A In the example embodiments, the vertical openings 1371-1 and 1371-2 are as follows: Figures 12A-12E As shown. However, in Figures 13A-13E In, it has in Figure 13CThe first source / drain region, channel region, and second source / drain region of the horizontal access devices 1398-1, 1398-2, ..., 1398-N, respectively, denoted as 1398-1A, 1398-1B, and 1398-1C, have been formed in [the image / image / concept]. Figure 12C and 12D The horizontal openings 1216-1, 1216-2, ..., 1216-N shown are included. Horizontal access devices 1398-1, 1398-2, and 1398-N are formed to extend in a second direction 1305 (D2) within a vertically stacked horizontal access device region 1342. Additionally, horizontal digital lines 1399-1, 1399-2, and 1399-N have been formed and integrated with the second source / drain region (e.g., ...). Figure 13C and 13D The 1398-1C contact is shown. Other components listed may be similar to those shown and discussed in conjunction with Figures 10, 11 and 12.

[0135] According to an embodiment, in the access device region 1342 (e.g., transistor region), Figures 12A-12E The sacrificial semiconductor materials 1232-1, 1232-2, ..., 1232-N in FIG. 12 have been removed from the vertical stack of FIG. 12. This process involves repeated iterations of alternating layers of first dielectric materials 1230-1, 1230-2, ..., 1230-N, horizontal openings 1216-1, 1216-2, ..., 1216-N, and second dielectric materials 1233-1, 1233-2, ..., 1233-N to form an access device, such as a transistor. In some embodiments, this process is performed before the selective removal of the sacrificial semiconductor material from the storage node region 1344 where capacitor cells are to be formed. In other embodiments, this process is performed after the selective removal of the sacrificial semiconductor material from the storage node region 1344 where capacitor cells are to be formed. Figure 13B-13E The example embodiments shown include methods using atomic layer deposition (ALD) processes or other suitable deposition techniques on... Figures 12A-12EIn each of the horizontal openings 1216-1, 1216-2, ..., 1216-N, a first source / drain region 1398-1A, a channel region 1398-1B, and a second source / drain region 1398-1C are selectively deposited. For example, but not as a limitation, forming the first source / drain region, channel region, and second source / drain region includes sequentially depositing the first source / drain region, channel region, and second source / drain region in the first horizontal opening using the process and techniques described in U.S. Patent Application No. 16943494, co-filed, co-pending, with at least one co-inventor, and entitled "Digit Line and Body Contact for Semiconductor Devices," using atomic layer deposition (ALD) technology. Other suitable semiconductor manufacturing techniques and / or memory node structures may be used.

[0136] Figure 13B Show along Figure 13A The cross-sectional view taken by the cutting line A-A' shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example embodiment of the present disclosure. Figure 13B The cross-sectional view shown is away from the plurality of individual vertical access lines 1340-1, 1340-2, ..., 1340-N, 1340-(N+1), ..., 1340-(Z-1), and shows a vertical stack formed on the semiconductor substrate 1300 (e.g., Figure 4 The vertically stacked capacitor (402) consists of alternating layers of first dielectric material 1330-1, 1330-2, ..., 1330-N and second dielectric material 1333-1, 1333-2, ..., 1333-N separated by capacitor cells. Each capacitor cell has a first electrode 1361 (e.g., a bottom cell contact electrode), a cell dielectric 1363, and a second electrode 1356 (e.g., a top common node electrode). Figure 13B As shown, the vertical direction 1311 is indicated as the third direction (D3), for example, the z-direction in the xyz coordinate system, similar to the third direction (D3) 111 among the first, second, and third directions shown in Figures 1-3. The plane extending left and right in the drawing is on the first direction (D1) 1309. Figure 13B In an example embodiment, the first electrode 1361 (e.g., the bottom electrode to be coupled to the source / drain region of the horizontal access device) and the second electrode 1356 are shown separated by a cell dielectric material 1363 that extends in a second direction (D2) and along the oriented axis of the horizontal access device and horizontal memory node of the vertically stacked memory cell array of the three-dimensional (3D) memory, both inside and outside the drawing plane.

[0137] Figure 13C Show along Figure 13A The cross-sectional view obtained by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 13C The cross-sectional view shown depicts the axis of repeated iterations along the second direction (D2) 1305 extending laterally along the drawing plane in the alternating layers of the first dielectric material 1330-1, 1330-2, ..., 1330-N and the second dielectric material 1333-1, 1333-2, ..., 1333-N. However, it is now shown that the first source / drain region material, the channel region material, and the second source / drain region materials 1398-1, 1398-2, ..., 1398-N have been deposited on... Figures 12A-12E The horizontal openings 1216-1, 1216-2, ..., 1216-N extend in the second direction 1305 (D2). As an example, the first source / drain region 1398-1, channel region 1398-1B, and 1398-1C are clearly shown. Furthermore, the horizontal digital lines 1399-1, 1399-2, ..., 1399-N are integrated into contact with the second source / drain region (e.g., 1398-1C) extending in the first direction (D1), for example, extending in and out of the drawing plane, and the layers of the second source / drain region are vertically alternating with the dielectric material 1330-1, 1330-2, ..., 1330-N in the direction (D3) 1311.

[0138] Therefore, three-node horizontal access devices 1338-1, 1338-2, ..., 1338-N have been formed and integrated into vertical access lines 1340-1, 1340-2, ..., 1340-(Z+1) and into digital lines 1399-1, 1399-2, ..., 1399-N without body contacts. Advantages of the structure and process described herein compared to silicon-based (Si-based) access devices may include lower turn-off current (Ioff) for the access devices. The channel region (e.g., 1338-1B) may have no minority carriers for the access device, thus eliminating the need to control the body potential of the access device's body region and / or reduce gate-induced / drain-induced leakage (GIDL). In some embodiments, channel and / or source / drain region replacement manufacturing steps can be performed after the capacitor cell formation process, thereby reducing the thermal budget. Since body contacts with the body region of the access device are not used, digital line integration can be more easily achieved during manufacturing. In addition, due to shorter channel lengths and lower source / drain semiconductor manufacturing process overhead, the embodiments described herein can achieve better lateral scaling paths than doped polysilicon-based channel regions.

[0139] Similarly, the integration of the first source / drain region, channel region, and second source / drain region of the horizontal access devices 1398-1, 1398-2, ..., 1398-N, and the horizontal digital lines 1399-1, 1399-2, ..., 1399-N, can be performed according to the processes and techniques described in U.S. Patent Applications Nos. 16986466 and 16986510, co-filed, co-pending, with at least one co-inventor, entitled “Channel Integration in a Three-Node Access Device for Vertical Three Dimensional (3D) Memory” and “Source / Drain Integration in a Three-Node Access Device for Vertical Three Dimensional (3D) Memory”, respectively. According to various embodiments, another advantage is that the formation of the source / drain regions avoids (e.g., does not use) gas phase doping (GPD). Other suitable semiconductor manufacturing technologies and / or memory node structures can be used.

[0140] exist Figure 13C In an example embodiment, horizontal access devices 1398-1, 1398-2, ..., 1389-N, having a first source / drain region, a channel region, and a second source / drain region, are shown extending laterally in the drawing plane along a second direction 1305 (D2), spaced a distance from the vertical openings 1371-1 and 1371-2 formed in the vertical stack, and along the orientation axis of the horizontal access devices and horizontal memory nodes of the vertically stacked memory cell array of the three-dimensional (3D) memory. In some embodiments, dielectric material may be deposited to fill the vertical openings 1371-1 and 1371-3. Figure 13C In the drawing, adjacent and opposite vertical access lines 1340-3 are shown as dashed lines, indicating the positions set inward from the plane and orientation of the drawing.

[0141] In some embodiments, execution is not performed in the storage node region. Figure 7A-9F The steps described herein can be performed in the access device area, not in the steps described herein. When Figure 7A-9FWhen the steps described herein are performed in the access device region, the method for forming a vertically stacked memory array may include performing etching to form a plurality of third vertical openings, thereby exposing third vertical sidewalls adjacent to the access device region 1342 in the vertical stack. The method may further include performing etching to selectively remove filler material along a second horizontal direction, thereby forming a plurality of second horizontal openings in which access devices are to be formed. In this embodiment, after the second horizontal openings are formed, the method may include forming horizontally oriented access devices within the second horizontal openings.

[0142] Figure 13D Show along Figure 13A The cross-sectional view obtained by the cutting line C-C' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 13D The cross-sectional view shown is illustrated by the axis of repeated iterations along the alternating layers of the first dielectric material 1330-1, 1330-2, ..., 1330-N, the horizontal digital lines 1399-1, 1399-2, ..., 1399-N, and the second dielectric material 1333-1, 1333-2, ..., 1333-N (extending in and out of the drawing plane in the first direction (D1)) and in the second direction (D2) 1305 extending left and right in the drawing plane outside the area in which the horizontally oriented access devices 1338-1, 1338-2, ..., 1338-N and the horizontally oriented storage nodes (e.g., capacitor cells) are formed in the access device area 1342 and the storage node area 1344. Figure 13D In the diagram, a third dielectric material 1341 is shown filling the space between horizontally oriented access devices spaced apart along a first direction (D1) in a three-dimensional array of vertically oriented memory cells, extending both inside and outside the drawing plane. However, in Figure 13D In the cross-sectional view, a second electrode 1356 (e.g., the top common electrode of a capacitor cell structure) is also shown existing in the space between horizontally adjacent devices. At the left end of the drawing, repeated iterations of alternating layers of first dielectric materials 1330-1, 1330-2, ..., 1330-N, horizontal digital lines 1399-1, 1399-2, ..., 1399-N (e.g., digital lines 107-1, 107-2, ..., 107-P, etc. shown in Figure 1) are shown, integrated to form electrical contacts with the second source / drain regions (e.g., 1338-1C) and second dielectric materials 1333-1, 1333-2, ..., 1333-N that form the horizontal access devices.

[0143] Figure 13E Show along Figure 13AThe cross-sectional view obtained by the cutting line D-D' in the figure shows another view of the semiconductor structure at this particular point in the semiconductor manufacturing process of an example of an embodiment of the present disclosure. Figure 13E The cross-sectional view shown in the drawing plane, from right to left, extends in a first direction (D1) 1309 along the axis of repeated iterations of the channel regions of the first dielectric material 1330-1, 1330-2, ..., 1330-N, the horizontal access devices 1398-1, 1398-2, ..., 1398-N, and the alternating layers of the second dielectric material 1333-1, 1333-2, ..., 1333-N. The channel regions are separated from the plurality of individual vertical access lines 1340-1, 1340-2, ..., 1340-4 by the gate dielectric 1338. Figure 13E In the diagram, a third dielectric filling material 1341 is shown to separate the space between adjacent horizontally oriented access devices and horizontally oriented storage nodes, which may be formed to extend into and out of the drawing plane, as described in more detail below, and may be spaced apart along a first direction (D1) 1309 and vertically stacked in a three-dimensional (3D) memory as an array extending in a third direction (D3) 1311.

[0144] Figure 14 A three-node horizontally oriented access device 1442 is shown, according to an embodiment of the present disclosure, coupled to a horizontally oriented storage node 1444 of a vertical three-dimensional (3D) memory. Figure 14 In the diagram, the three-node horizontally oriented access device 1442 is shown extending left and right in the drawing plane along a second direction (D2) 1405. The horizontally oriented access device 1442 is shown having a first source / drain region 1498-1A that is electrically contacting a first electrode 1461 (e.g., bottom electrode) of a horizontally oriented storage node 1444 (e.g., a capacitor cell). The storage node 1444 is further shown having a dielectric material 1463 separating the first electrode 1461 from a second electrode 1456 (e.g., the top common node electrode of a capacitor cell).

[0145] Channel region 1498-1B is shown as being electrically contacted with the first source / drain region 1498-1A. Vertically oriented access line 1440-3 is opposite to channel region 1498-1B and separated from it by a gate dielectric. Vertically oriented access line 1440-3 is shown as a dashed line, indicating a vertically oriented access line extending inwards and / or outwards from the drawing plane. According to specific design rules, vertically oriented access line 1440 may extend longer and / or shorter than the channel region in the second direction (D2) 1405, for example, with source / drain overlap and / or underlap.

[0146] The second source / drain region 1498-1C is shown as making electrical contact with the channel region 1498-1B, and also making electrical contact with and integrating with the horizontally oriented digital line 1499 extending in and out of the drawing plane. (As shown) Figure 14 As shown, the horizontally oriented access device 1442 and the horizontally oriented memory node 1444 are horizontally spaced from adjacent memory cells along the second direction (D2) 1405 via interlayer dielectric material 1480, and are vertically spaced from stacked adjacent cells in the three-dimensional (3D) memory via dielectric layers 1430-1 and 1430-2.

[0147] Figure 15 This is a block diagram of a device in the form of a computing system 1590 including a memory device 1593, according to several embodiments of the present disclosure. As used herein, the memory device 1593, memory array 1580, and / or host 1592 may also be considered, for example, as “devices” respectively.

[0148] In this example, system 1590 includes a host 1592 coupled to memory device 1593 via interface 1594. The computing system 1590 may be a personal laptop computer, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, as well as various other types of systems. Host 1592 may include several processing resources capable of accessing memory device 1593, such as one or more processors, microprocessors, or some other type of control circuitry. System 1590 may include a separate integrated circuit, or host 1592 and memory device 1593 may both be on the same integrated circuit. For example, host 1592 may be a system controller for a memory system including multiple memory devices 1593, wherein system controller 1591 provides access to the respective memory devices 1593 by another processing resource, such as a central processing unit (CPU).

[0149] exist Figure 15 In the example shown, host 1592 is responsible for executing an operating system (OS) and / or various applications, such as processes, that can be loaded onto memory device 1593, for example, via controller 1595. The OS and / or various applications can be loaded from memory device 1593 by providing access commands from host 1592 to memory device 1593 for accessing data including the OS and / or various applications. Host 1592 can also access the data used by the OS and / or various applications by providing access commands to memory device 1593 for retrieving the data used to execute the OS and / or various applications.

[0150] For clarity, system 1590 has been simplified to focus on features particularly relevant to this disclosure. Memory array 1580 may be a DRAM array comprising at least one memory cell having sensing lines and body contacts formed according to the techniques described herein. For example, memory array 1580 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Memory array 1580 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sensing lines (which may be referred to herein as digital lines or data lines). Although in Figure 15 A single array 1580 is shown, but embodiments are not limited thereto. For example, a memory device 1593 may include several arrays 1580, such as arrays of DRAM cells.

[0151] Memory device 1593 includes address circuitry 1596 to latch address signals provided via interface 1594. The interface may include a physical interface employing, for example, a suitable protocol (e.g., a data bus, address bus, and command bus, or a combination of data / address / command buses). Such protocols may be custom or proprietary, or interface 1594 may utilize standardized protocols such as PCIe, Gen-Z, CCIX, etc. Row decoder 1598 and column decoder 1582 receive and decode address signals to access memory array 1580. Data can be read from memory array 1580 by sensing voltage and / or current changes on sensing lines using sensing circuitry 1581. Sensing circuitry 1581 may include, for example, a sensing amplifier that can read and latch pages, such as rows, of data from memory array 1580. I / O circuitry 1597 can be used for bidirectional data communication with host 1592 via interface 1594. The read / write circuitry 1583 is used to write data to or read data from the memory array 1580. As an example, the circuitry 1583 may include various drivers, latching circuitry, etc.

[0152] The control circuitry 1584 includes register 1599 and decodes signals provided by host 1592. These signals may be commands provided by host 1592. These signals may include chip enable signals, write enable signals, and address latch signals, which control operations performed on memory array 1580, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry 1584 is responsible for executing instructions from host 1592. Control circuitry 1584 may include a state machine, sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination thereof. In some instances, host 1592 may be a controller external to memory device 1593. For example, host 1592 may be a memory controller coupled to the processing resources of a computing device.

[0153] For example, the term semiconductor can refer to a material, wafer, or substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when referenced to semiconductor in the foregoing description, prior processing steps may have been used to form regions / junctions in the substrate semiconductor structure, and the term semiconductor may include a base material containing these regions / junctions.

[0154] The figures in this document follow a numbering convention, wherein the first one or more digits correspond to the figure number, and the remaining digits identify elements or components in the figure. Similar (e.g., identical) elements or components between different figures may be identified by using similar digits. It should be understood that elements shown in various embodiments herein may be added, interchanged, and / or excluded to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scales and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be construed as limiting.

[0155] As used herein, “several” or “a certain number” of something can refer to one or more of such things. For example, “several” or “a certain number” of memory cells can refer to one or more memory cells. “A certain number” of something means two or more. As used herein, multiple actions performed simultaneously refer to actions that overlap at least partially within a specific time period. As used herein, the term “coupling” can include electrical coupling, direct coupling and / or direct connection (e.g., by direct physical contact) without intermediate elements, or indirect coupling and / or connection with intermediate elements, or wireless coupling. The term coupling can further include two or more elements that cooperate or interact with each other (e.g., as in a causal relationship). An element coupled between two elements can be between and coupled to each of the two elements.

[0156] It should be recognized that the term "vertical" refers to variations in verticality due to routine manufacturing, measurement, and / or assembly variations, and the meaning of the term "vertical" will be understood by those skilled in the art. For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, be above or laterally to the other element, and / or be in direct physical contact with the other element. For example, laterally to may refer to a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0157] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of various embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art after reviewing the above description. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of the equivalents granted by those claims.

Claims

1. A method for forming a vertically stacked memory cell array (101-1, 101-2, ..., 101-N, 201-1, 201-2, ..., 201-N) having horizontally oriented access devices (129, 229, 329, 1333-1, 1338-2, ..., 1338-N, 1442) and horizontally oriented memory nodes (1444), the method comprising: The first dielectric material (430-1, 430-2, ..., 430-N, 630-1, 630-2, ..., 630-N, 730-1, 730-2, ..., 730-N, 830-1, 830-2, ..., 830-N, 930-1, 930-2, ..., 930-N, 1030-1, 1030-2, ..., 1030-N, 113) is vertically deposited in repeated iterations. 0-1, 1130-2, ..., 1130-N, 1230-1, 1230-2, ..., 1230-N, 1330-1, 1330-2, ..., 1330-N), semiconductor materials (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ... ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N) and the second dielectric material (433-1, 433-2, ..., 433-N, 633-1, 633-2, ..., 633-N, 733-1, 733-2, ..., 733-N, 83 Layers of 3-1, 833-2, ..., 833-N, 933-1, 933-2, ..., 933-N, 1033-1, 1033-2, ..., 1033-N, 1133-1, 1133-2, ..., 1133-N, 1233-1, 1233-2, ..., 1233-N, 1333-1, 1333-2, ..., 1333-N) are stacked vertically (402); A plurality of first vertical openings (512) are formed, the first vertical openings having a first horizontal direction (509, 709, 909, 1009, 1109) and a second horizontal direction (505, 705, 905, 1005), passing through the vertical stack (402) and extending mainly in the second horizontal direction (505, 705, 905, 1005) to form an elongated vertical column (513, 542) with a first vertical sidewall (514) in the vertical stack (402); Conductive material (540-1, 540-2, ..., 540-4, 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1), 640-Z, 1077) is conformally deposited on the gate dielectric material (104, 304, 538, 638, 1038, 1138, 1238, 1338) in the plurality of first vertical openings (512); Remove portions of the conductive material (540-1, 540-2, ..., 540-4, 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1), 640-Z, 1077) from the plurality of first vertical openings (512) to form a plurality of individual vertical conductive lines (540-1, 540-2, ..., 540-4, 740, 940) along the first vertical sidewall (514); A third dielectric material (541, 641, 741, 941, 1041, 1141, 1241, 1341) is deposited in the plurality of first vertical openings (512); A plurality of second vertical openings (749, 849, 949) are formed in the third dielectric material (541, 641, 741, 941, 1041, 1141, 1241, 1341) to expose the second vertical sidewalls (745) in the vertical stack (402); A plurality of first horizontal openings (831-1, 831-2) are formed in the layer of the semiconductor material (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N). Deposited filling material (934-1, 934-2) to fill the plurality of first horizontal openings (831-1, 831-2) in the elongated vertical column array (513, 542); A third vertical opening (1051) is formed to expose the third vertical sidewalls of the adjacent storage node regions (1050, 1150, 1244, 1344) in the vertical stack (402); and The filler material (934-1, 934-2) is selectively removed along the second horizontal direction (505, 705, 905, 1005) to form a plurality of second horizontal openings (1079) in which the horizontally oriented storage node (1444) is to be formed.

2. The method according to claim 1, further comprising: A plurality of second horizontal openings (1079) are formed by selectively removing the filler material (934-1, 934-2) via selective etching; Remove the filler material (934-1, 934-2) without using a timed excavation etching process; as well as A horizontally oriented access device (129, 229, 329, 1333-1, 1338-2, ..., 1338-N, 1442) is formed in the second horizontal opening (1079).

3. The method according to claim 1, wherein the first dielectric material (430-1, 430-2, ..., 430-N, 630-1, 630-2, ..., 630-N, 730-1, 730-2, ..., 730-N, 830-1, 830-2, ..., 830-N, 930-1, 930-2, ..., 930-N, 1030-1, 1030-2, ...) is formed vertically in repeated iterations. 1030-N, 1130-1, 1130-2, ..., 1130-N, 1230-1, 1230-2, ..., 1230-N, 1330-1, 1330-2, ..., 1330-N), the semiconductor materials (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, ... 832-2, ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N) and the second dielectric material (433-1, 433-2, ..., 433-N, 633-1, 633-2, ..., 633-N, 733-1, 733-2, ..., 733-N, 8 The layers 33-1, 833-2, ..., 833-N, 933-1, 933-2, ..., 933-N, 1033-1, 1033-2, ..., 1033-N, 1133-1, 1133-2, ..., 1133-N, 1233-1, 1233-2, ..., 1233-N, 1333-1, 1333-2, ..., 1333-N) to form the vertical stack (402) include: The deposited oxide material serves as the first dielectric material (430-1, 430-2, ..., 430-N, 630-1, 630-2, ..., 630-N, 730-1, 730-2, ..., 730-N, 830-1, 830-2, ..., 830-N, 930-1, 930-2, ..., 930-N, 1030-1, 1030-2, ..., 1030-N, 1130-1, 1130-2, ..., 1130-N, 1230-1, 1230-2, ..., 1230-N, 1330-1, 1330-2, ..., 1330-N); Deposited polycrystalline silicon material as the semiconductor material (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N); and The deposited nitride material serves as the second dielectric material (433-1, 433-2, ..., 433-N, 633-1, 633-2, ..., 633-N, 733-1, 733-2, ..., 733-N, 833-1, 833-2, ..., 833-N, 933-1, 933-2, ..., 933-N, 1033-1, 1033-2, ..., 1033-N, 1133-1, 1133-2, ..., 1133-N, 1233-1, 1233-2, ..., 1233-N, 1333-1, 1333-2, ..., 1333-N).

4. The method according to claim 1, further comprising using lateral etching on opposite sides of the semiconductor material (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N) to form the plurality of first horizontal openings (831-1, 831-2).

5. The method according to claim 1, wherein: The filler material (934-1, 934-2) is silicon (Si) or germanium (Ge); and The filling material (934-1, 934-2) is selective for the semiconductor material (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N).

6. The method of claim 1, further comprising forming the horizontally oriented storage node (1444) to include a capacitor cell having a first horizontally oriented electrode (1161, 1261, 1361, 1461) of a first source / drain region (121, 221, 321, 1075, 1178, 1398-1A, 1498-1A) electrically coupled to the horizontally oriented access device (129, 221, 321, 1075, 1178, 1398-1A, 1498-1A) and a second horizontally oriented electrode (1156, 1256, 1356, 1456) separated from the first horizontally oriented electrode (1161, 1261, 1361, 1461) by a cell dielectric (1163, 1263, 1363).

7. A method for forming a vertically stacked memory cell array (101-1, 101-2, ..., 101-N, 201-1, 201-2, ..., 201-N) having horizontally oriented access devices (129, 229, 329, 1333-1, 1338-2, ..., 1338-N, 1442) and horizontally oriented memory nodes (1444), the method comprising: The first dielectric material (430-1, 430-2, ..., 430-N, 630-1, 630-2, ..., 630-N, 730-1, 730-2, ..., 730-N, 830-1, 830-2, ..., 830-N, 930-1, 930-2, ..., 930-N, 1030-1, 1030-2, ..., 1030-N, 113) is vertically deposited in repeated iterations. 0-1, 1130-2, ..., 1130-N, 1230-1, 1230-2, ..., 1230-N, 1330-1, 1330-2, ..., 1330-N), semiconductor materials (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ... ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N) and the second dielectric material (433-1, 433-2, ..., 433-N, 633-1, 633-2, ..., 633-N, 733-1, 733-2, ..., 733-N, 83 Layers of 3-1, 833-2, ..., 833-N, 933-1, 933-2, ..., 933-N, 1033-1, 1033-2, ..., 1033-N, 1133-1, 1133-2, ..., 1133-N, 1233-1, 1233-2, ..., 1233-N, 1333-1, 1333-2, ..., 1333-N) are stacked vertically (402); Etching is performed to form a plurality of first vertical openings (512) having a first horizontal direction (509, 709, 909, 1009, 1109) and a second horizontal direction (505, 705, 905, 1005), passing through the vertical stack (402) and extending primarily in the second horizontal direction (505, 705, 905, 1005) to form an elongated column of vertical columns (513, 542) having first vertical sidewalls (514) in the vertical stack (402); Conductive material (540-1, 540-2, ..., 540-4, 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1), 640-Z, 1077) is conformally deposited on the gate dielectric material (104, 304, 538, 638, 1038, 1138, 1238, 1338) in the plurality of first vertical openings (512); Etching is performed to remove portions of the conductive material (540-1, 540-2, ..., 540-4, 640-1, 640-2, ..., 640-(N-1), 640-N, 640-(N+1), ..., 640-(Z-1), 640-Z, 1077) from the plurality of first vertical openings (512), thereby forming a plurality of individual vertical conductive lines (540-1, 540-2, ..., 540-4, 740, 940) along the first vertical sidewall (514); A third dielectric material (541, 641, 741, 941, 1041, 1141, 1241, 1341) is deposited in the plurality of first vertical openings (512); Etching is performed to form a plurality of second vertical openings (749, 849, 949) in the third dielectric material (541, 641, 741, 941, 1041, 1141, 1241, 1341), thereby exposing the second vertical sidewalls (745) in the vertical stack (402); Lateral etching is performed to form a plurality of first horizontal openings (831-1, 831-2) in the layer of the semiconductor material (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N); Depositing selective filler materials (934-1, 934-2) selectively targeting the semiconductor materials (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N) to fill the plurality of first horizontal openings (831-1, 831-2) in the elongated vertical column array (513, 542); Etching is performed to form a plurality of third vertical openings (1051), thereby exposing the third vertical sidewalls of the vertical stack (402) adjacent to the access device area (742, 1242, 1342); as well as Etching is performed to selectively remove the filler material (934-1, 934-2) along the second horizontal direction (505, 705, 905, 1005), thereby forming a plurality of second horizontal openings (1079) in which access devices (129, 229, 329, 1333-1, 1338-2, ..., 1338-N, 1442) are to be formed.

8. The method of claim 7, further comprising doping the filler material (934-1, 934-2) to dope a portion of the semiconductor material (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N).

9. The method according to any one of claims 7 to 8, further comprising forming the first horizontal opening (831-1, 831-2) in the portion of the semiconductor material (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N) corresponding to the second vertical opening (749, 849, 949).

10. The method according to any one of claims 7 to 8, wherein the lateral etching is directed against the first dielectric material (430-1, 430-2, ..., 430-N, 630-1, 630-2, ..., 630-N, 730-1, 730-2, ..., 730-N, 830-1, 830-2, ..., 830-N, 930-1, 930-2, ..., 930-N, 1030-1, 1030-2, ..., 1030-N, 1130-1, 1130-2, ..., 1130-N, 1230-1, 1230-2, ..., 1230-N, 1330-1, 133...). The first dielectric material (0-2, ..., 1330-N) and the second dielectric material (433-1, 433-2, ..., 433-N, 633-1, 633-2, ..., 633-N, 733-1, 733-2, ..., 733-N, 833-1, 833-2, ..., 833-N, 933-1, 933-2, ..., 933-N, 1033-1, 1033-2, ..., 1033-N, 1133-1, 1133-2, ..., 1133-N, 1233-1, 1233-2, ..., 1233-N, 1333-1, 1333-2, ..., 1333-N) are selective.

11. A memory device comprising: A vertically stacked memory cell array (101-1, 101-2, ..., 101-N, 201-1, 201-2, ..., 201-N) having horizontally oriented access devices (129, 229, 329, 1333-1, 1338-2, ..., 1338-N, 1442) and horizontally oriented memory nodes (1444), wherein the vertically stacked memory cell array (101-1, 101-2, ..., 101-N, 201-1, 201-2, ..., 201-N) comprises: The horizontally oriented access device (129, 229, 329, 1333-1, 1338-2, ..., 1338-N, 1442) has a first source / drain region (121, 221, 321, 1075, 1178, 1398-1A, 1498-1A) and a second source / drain region (121) separated by channels (125, 225, 325, 1338-1, 1498-1A). , 123, 221, 223, 321, 323, 1078, 1398-1, 1398-2, ..., 1398-N, 1498-1), and having a gate opposite to the channel (125, 225, 325, 1338-1, 1498-1) and separated from it by a gate dielectric (104, 304, 538, 638, 1038, 1138, 1238, 1338); and Self-aligned memory nodes are formed in the vertically stacked memory cell array (101-1, 101-2, ..., 101-N, 201-1, 201-2, ..., 201-N), wherein the self-aligned memory nodes are formed in the memory node region of the vertically stacked memory cell array (101-1, 101-2, ..., 101-N, 201-1, 201-2, ..., 201-N), and the memory node region is formed by the following steps: Lateral etching is performed on the opposite sides of the semiconductor material (432-1, 432-2, ..., 432-N, 632-1, 632-2, ..., 632-N, 732-1, 732-2, ..., 732-N, 832-1, 832-2, ..., 832-N, 932-1, 932-2, ..., 932-N, 1032-1, 1032-2, ..., 1032-N, 1132-1, 1132-2, ..., 1132-N) of the vertically stacked memory cell array (101-1, 101-2, ..., 101-N, 201-1, 201-2, ..., 201-N) to form horizontal openings (831-1, 831-2); The horizontal openings (831-1, 831-2) are filled with filler materials (934-1, 934-2); The filler materials (934-1, 934-2) are doped to cause the dopant to migrate from the filler materials (934-1, 934-2) to the semiconductor materials (432-1, 432-2, ..., 432-N; 632-1, 632-2, ..., 632-N; 732-1, 732-2, ..., 732-N; 832-1, 832-2, ..., 832-N; 932-1, 932-2, ..., 932-N; 1032-1, 1032-2, ..., 1032-N; 1132-1, 1132-2, ..., 1132-N). A vertical opening (1051) is formed to expose the vertical sidewalls in the vertical stack adjacent to the storage node area; and Selectively remove the filling material (934-1, 934-2) in the horizontal direction to extend the storage node area by a horizontal distance.

12. The memory device of claim 11, wherein the height of the vertically stacked memory cell array (101-1, 101-2, ..., 101-N, 201-1, 201-2, ..., 201-N) is at least four layers.

13. The memory device according to any one of claims 11 to 12, wherein: The self-aligned storage node is a capacitor and has horizontally oriented bottom electrodes of equal length (1156, 1256, 1356, 1456); and The self-aligned memory node is formed in a plurality of first horizontal openings (831-1, 831-2) formed by a selective etching process.

14. The memory device of any claim 13, wherein the first plurality of first horizontal openings and the second plurality of first horizontal openings comprise the same number of horizontal openings.

15. The memory device according to any one of claims 11 to 12, wherein the horizontal distance is in the range of two hundred (200) to three hundred (300) nanometers (nm).

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