A method of forming a capacitor

Abstract

The application provides a capacitor forming method, which comprises the following steps: providing a semiconductor substrate, forming a plurality of grooves in the semiconductor substrate, sequentially forming a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer in the plurality of grooves and on the surface of the semiconductor substrate, and forming a plurality of first openings in the third electrode layer and the fourth electrode layer between adjacent grooves, the first openings exposing the second electrode layer; forming a second opening in the second electrode layer exposed by the first opening, the second opening exposing the first electrode layer, and forming a third opening in the fourth electrode layer, the third opening exposing the third electrode layer. The application provides a capacitor forming method, which combines the mode of etching two or more electrode layers by one-time photolithography and the mode of etching a single electrode layer by one-time photolithography, so that the number of photolithography processes can be reduced, all electrode layers can be connected, the process is simplified, and the cost is saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a forming method of a capacitor. BACKGROUND

[0002] With the continuous reduction of the size of semiconductor devices and the continuous improvement of the integration, the performance of the capacitor also needs to be improved, that is, the charge storage capacity of the capacitor is increased under the premise of reducing the capacitor area. It is known that the deep trench capacitor device greatly reduces the area occupied by the capacitor. However, to further improve the capacitance of the capacitor, more layers of electrode layers need to be made to increase the total area of the electrode layers.

[0003] However, with the increase of the number of electrode layers, more times of photolithography process are needed to form the contact structures respectively electrically connecting different electrode layers in the subsequent process, which makes the process more complex and the cost is also higher. Therefore, it is necessary to provide a more effective and reliable technical solution. SUMMARY

[0004] The present application provides a forming method of a capacitor, which can reduce the number of photolithography processes, simplify the process and save the cost.

[0005] One aspect of the present application provides a forming method of a capacitor, comprising: providing a semiconductor substrate, a plurality of trenches are formed in the semiconductor substrate, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer filling the plurality of trenches are sequentially formed in the plurality of trenches and the surface of the semiconductor substrate, wherein a plurality of first openings exposing the second electrode layer are formed in the third electrode layer and the fourth electrode layer between adjacent trenches; forming a second opening exposing the first electrode layer in the second electrode layer exposed by the first opening, and forming a third opening exposing the third electrode layer in the fourth electrode layer; forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer on the semiconductor substrate; and forming a contact structure penetrating through the dielectric layer and respectively electrically connecting the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer in the dielectric layer.

[0006] In some embodiments of the present application, the method for forming a plurality of first openings exposing the second electrode layer in the third electrode layer and the fourth electrode layer between adjacent trenches comprises: providing a semiconductor substrate having a plurality of trenches formed therein, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer formed in the plurality of trenches and on the surface of the semiconductor substrate in sequence; forming a patterned first photoresist layer on the surface of the fourth electrode layer, the patterned first photoresist layer defining the positions of the first openings; etching the fourth electrode layer and the third electrode layer to form the first openings using the patterned first photoresist layer as a mask; and removing the patterned first photoresist layer.

[0007] In some embodiments of the present application, the method for forming a second opening exposing the first electrode layer in the second electrode layer exposed by the first opening, and a third opening exposing the third electrode layer in the fourth electrode layer comprises: forming a patterned second photoresist layer on the surface of the second electrode layer exposed by the first opening and on the surface of the fourth electrode layer, the patterned second photoresist layer defining the positions of the second opening and the third opening; etching the second electrode layer exposed by the first opening and the fourth electrode layer to form the second opening and the third opening using the patterned second photoresist layer as a mask; and removing the patterned second photoresist layer.

[0008] In some embodiments of the present application, the patterned second photoresist layer comprises a fourth opening and a fifth opening, wherein the fourth opening defines the position of the second opening, and the fifth opening defines the position of the third opening.

[0009] In some embodiments of the present application, the patterned second photoresist layer comprises a sixth opening, the sixth opening being located at the boundary of the first opening and defining the positions of the second opening and the third opening.

[0010] In some embodiments of the present application, a first insulating layer is further formed between the first electrode layer and the second electrode layer; a second insulating layer is further formed between the second electrode layer and the third electrode layer; and a third insulating layer is further formed between the third electrode layer and the fourth electrode layer.

[0011] Another aspect of the present application provides a method for forming a capacitor, comprising: providing a semiconductor substrate having a plurality of trenches formed therein, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer sequentially formed in the plurality of trenches and on the surface of the semiconductor substrate, wherein a plurality of first openings exposing the third electrode layer are formed in the fourth electrode layer between adjacent trenches; forming a second opening exposing the first electrode layer in the third electrode layer and the second electrode layer at the bottom of the first opening, and simultaneously forming a third opening exposing the second electrode layer in the fourth electrode layer and the third electrode layer; forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer on the semiconductor substrate; and forming a contact structure penetrating the dielectric layer and electrically connecting the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer respectively.

[0012] In some embodiments of the present application, the method for forming a plurality of first openings exposing the third electrode layer in the fourth electrode layer between adjacent trenches comprises: providing a semiconductor substrate having a plurality of trenches formed therein, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer sequentially formed in the plurality of trenches and on the surface of the semiconductor substrate; forming a patterned first photoresist layer on the surface of the fourth electrode layer, the patterned first photoresist layer defining the positions of the first openings; etching the fourth electrode layer to form the first openings using the patterned first photoresist layer as a mask; and removing the patterned first photoresist layer.

[0013] In some embodiments of the present application, the method for forming a second opening exposing the first electrode layer in the third electrode layer and the second electrode layer at the bottom of the first opening, and simultaneously forming a third opening exposing the second electrode layer in the fourth electrode layer and the third electrode layer comprises: forming a patterned second photoresist layer on the surface of the third electrode layer exposed by the first opening and on the surface of the fourth electrode layer, the patterned second photoresist layer defining the positions of the second openings and the third openings; etching the third electrode layer and the second electrode layer at the bottom of the first opening and the fourth electrode layer and the third electrode layer to form the second openings and the third openings simultaneously using the patterned second photoresist layer as a mask; and removing the patterned second photoresist layer.

[0014] In some embodiments of the present application, the patterned second photoresist layer comprises a fourth opening and a fifth opening, wherein the fourth opening defines the position of the second opening, and the fifth opening defines the position of the third opening.

[0015] In some embodiments of the present application, the patterned second photoresist layer comprises a sixth opening, the sixth opening is located at the boundary of the first opening and defines the positions of the second opening and the third opening.

[0016] In some embodiments of the present application, a first insulating layer is further formed between the first electrode layer and the second electrode layer; a second insulating layer is further formed between the second electrode layer and the third electrode layer; and a third insulating layer is further formed between the third electrode layer and the fourth electrode layer.

[0017] The present application provides a method for forming a capacitor, by adjusting the combination of lithography processes when etching different electrode layers, the number of lithography processes can be reduced, the process is simplified, and the cost is saved. BRIEF DESCRIPTION OF DRAWINGS

[0018] The following drawings set forth in detail the exemplary embodiments disclosed in the present application. The same reference numbers in the several views of the drawings represent similar structures. A person of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, other ways of embodiments can also achieve the same intention of the invention in the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0019] Figures 1 to 6 Structure diagrams of some steps in the method for forming a capacitor;

[0020] Figure 7 Flowchart of the method for forming a capacitor according to some embodiments of the present application;

[0021] Figures 8 to 19 Structure diagrams of some steps in the method for forming a capacitor according to some embodiments of the present application;

[0022] Figure 20 Flowchart of the method for forming a capacitor according to some embodiments of the present application;

[0023] Figures 21 to 32 Structure diagrams of some steps in the method for forming a capacitor according to some embodiments of the present application. DETAILED DESCRIPTION

[0024] The following description provides specific application scenarios and requirements of the present application, which is to enable a person skilled in the art to manufacture and use the content in the present application. Various local modifications of the disclosed embodiments are obvious to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the shown embodiments, but is consistent with the widest scope of the claims.

[0025] The technical solutions of the present application will be described in detail below with reference to the embodiments and drawings.

[0026] Figures 1 to 6 Structure diagrams of some steps in the forming method of the capacitor.

[0027] Reference Figure 1 As shown in FIG. 1, a semiconductor substrate 100 is provided, in which a plurality of trenches 101 are formed, and in which the first electrode layer 110, the second electrode layer 120, the third electrode layer 130 and the fourth electrode layer 140 are sequentially formed in the plurality of trenches 101 and on the surface of the semiconductor substrate 100.

[0028] A first insulating layer (not shown in the figure) is further formed between the first electrode layer 110 and the second electrode layer 120; a second insulating layer (not shown in the figure) is further formed between the second electrode layer 120 and the third electrode layer 130; and a third insulating layer (not shown in the figure) is further formed between the third electrode layer 130 and the fourth electrode layer 140.

[0029] Reference Figure 2 As shown in FIG. 2, a first opening 151 exposing the third electrode layer 130 is formed in the fourth electrode layer 140 between the adjacent trenches 101 using a photolithography process.

[0030] Reference Figure 3 As shown in FIG. 3, a second opening 152 exposing the second electrode layer 120 is formed in the third electrode layer 130 exposed by the first opening 151 using a photolithography process.

[0031] Reference Figure 4 As shown in FIG. 4, a third opening 153 exposing the first electrode layer 110 is formed in the second electrode layer 120 exposed by the second opening 152 using a photolithography process.

[0032] Reference Figure 5 As shown in FIG. 5, a dielectric layer 160 covering the first electrode layer 110, the second electrode layer 120, the third electrode layer 130 and the fourth electrode layer 140 is formed on the semiconductor substrate 100.

[0033] Reference Figure 6 As shown in FIG. 6, a contact structure 170 penetrating the dielectric layer 160 and electrically connecting the first electrode layer 110, the second electrode layer 120, the third electrode layer 130 and the fourth electrode layer 140 respectively is formed in the dielectric layer 160.

[0034] In Figures 1 to 6In the shown process, the first opening 151, the second opening 152, and the third opening 153 are formed one by one in sequence, and thus three photolithography processes are required. However, this way requires a large number of photolithography processes, leading to a complex process. In semiconductor processes, the photolithography process itself is a process with high cost and high difficulty. A large number of photolithography processes lead to higher cost. As the number of electrode layers increases, the complexity of the process will continue to increase, and the cost will also continue to increase.

[0035] To solve the above problems, the application provides a capacitor forming method. By adjusting the photolithography process combination when etching different electrode layers, the number of photolithography processes can be reduced, the process can be simplified, and the cost can be saved.

[0036] Figure 7 The flowchart of the capacitor forming method described in some embodiments of the application.

[0037] Some embodiments of the application provide a capacitor forming method, which is described with reference to Figure 7 as shown, comprising:

[0038] Step S1: providing a semiconductor substrate, a plurality of trenches are formed in the semiconductor substrate, and a first electrode layer, a second electrode layer, a third electrode layer, and a fourth electrode layer that fill the plurality of trenches are formed in the plurality of trenches and on the surface of the semiconductor substrate in sequence, wherein a plurality of first openings exposing the second electrode layer are formed in the third electrode layer and the fourth electrode layer between adjacent trenches;

[0039] Step S2: forming a second opening exposing the first electrode layer in the second electrode layer exposed by the first opening, and forming a third opening exposing the third electrode layer in the fourth electrode layer;

[0040] Step S3: forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer, and the fourth electrode layer on the semiconductor substrate;

[0041] Step S4: forming a contact structure in the dielectric layer, the contact structure penetrating the dielectric layer and electrically connecting the first electrode layer, the second electrode layer, the third electrode layer, and the fourth electrode layer, respectively.

[0042] Figures 8 to 16 The structure diagram of each step in the capacitor forming method described in some embodiments of the application is shown. The capacitor forming method described in some embodiments of the application will be described in detail below with reference to the accompanying drawings.

[0043] Reference is made to Figure 7 and Figures 8 to 11As shown, a semiconductor substrate 200 is provided, in which a plurality of trenches 201 are formed, and a first electrode layer 210, a second electrode layer 220, a third electrode layer 230 and a fourth electrode layer 240 are sequentially formed in the plurality of trenches 201 and on the surface of the semiconductor substrate 200, wherein a plurality of first openings 261 exposing the second electrode layer 220 are formed in the third electrode layer 230 and the fourth electrode layer 240 between adjacent trenches 201.

[0044] Reference Figure 8 As shown, a semiconductor substrate 200 is provided, in which a plurality of trenches 201 are formed, and a first electrode layer 210, a second electrode layer 220, a third electrode layer 230 and a fourth electrode layer 240 are sequentially formed in the plurality of trenches 201 and on the surface of the semiconductor substrate 200.

[0045] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or indium gallium phosphide, etc.; or (iv) a combination thereof. In addition, the semiconductor substrate 200 can be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 200 can be doped with a P-type dopant (e.g., boron, indium, aluminum or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0046] In some embodiments of the present application, the material of the first electrode layer 210, the second electrode layer 220, the third electrode layer 230 and the fourth electrode layer 240 includes a metal or a metal compound, such as aluminum, tungsten, etc.

[0047] In some embodiments of the present application, a first insulating layer (not shown in the figure) is further formed between the first electrode layer 210 and the second electrode layer 220; a second insulating layer (not shown in the figure) is further formed between the second electrode layer 220 and the third electrode layer 230; and a third insulating layer (not shown in the figure) is further formed between the third electrode layer 230 and the fourth electrode layer 240. The thicknesses of the first insulating layer, the second insulating layer and the third insulating layer are thinner than the thicknesses of the first electrode layer 210, the second electrode layer 220, the third electrode layer 230 and the fourth electrode layer 240, and therefore the first insulating layer, the second insulating layer and the third insulating layer are not shown in the figures for the purpose of simplicity. However, it should be understood by those skilled in the art that the first insulating layer, the second insulating layer and the third insulating layer are objectively existent as the basic constituent structures of the deep trench capacitor.

[0048] In some embodiments of the application, the material of the first, second and third insulating layers is an insulating dielectric material, such as silicon oxide or silicon nitride.

[0049] Referring to Figure 9 As shown, a patterned first photoresist layer 251 is formed on the surface of the fourth electrode layer 240, which defines the position of the first opening 261.

[0050] Referring to Figure 10 As shown, the fourth electrode layer 240 and the third electrode layer 230 are etched to form the first opening 261, with the patterned first photoresist layer 251 as a mask.

[0051] Referring to Figure 11 As shown, the patterned first photoresist layer 251 is removed.

[0052] In some embodiments of the application, the position of the first opening 261 is not in the middle of the adjacent trench 201, but close to one of the adjacent trenches 201. This is to leave enough space for the third opening to be formed later. The width of the first opening 261 cannot be too small, otherwise the space for the second opening to be formed later is too small; the width of the first opening 261 also cannot be too large, otherwise the space for the third opening to be formed later is too small.

[0053] Referring to Figure 7 And Figures 12 to 17 As shown, in step S2, a second opening 262 is formed in the second electrode layer 220 exposed by the first opening 261, which exposes the first electrode layer 210, and a third opening 263 is formed in the fourth electrode layer 240, which exposes the third electrode layer 230.

[0054] Referring to Figure 12 As shown, a patterned second photoresist layer 252 is formed on the surface of the second electrode layer 220 exposed by the first opening 261 and the surface of the fourth electrode layer 240, which defines the position of the second opening 262 and the third opening 263.

[0055] In some embodiments of the application, the patterned second photoresist layer 252 includes a fourth opening 264 and a fifth opening 265, wherein the fourth opening 264 defines the position of the second opening 262, and the fifth opening 265 defines the position of the third opening 263.

[0056] Referring to Figure 13As shown, the second electrode layer 220 and the fourth electrode layer 240 exposed by the first opening are etched simultaneously to form the second opening 262 and the third opening 263.

[0057] Referring to Figure 14 As shown, the patterned second photoresist layer 252 is removed.

[0058] Referring to Figure 15 As shown Figure 15 In some other embodiments Figure 11 In some other embodiments of the present application, as shown in the subsequent figure, the patterned second photoresist layer 252 includes a sixth opening 266, which is located at the boundary of the first opening and defines the positions of the second opening 262 and the third opening 263.

[0059] Referring to Figure 16 As shown, the second electrode layer 220 and the fourth electrode layer 240 exposed by the first opening are etched simultaneously to form the second opening 262 and the third opening 263.

[0060] Referring to Figure 17 As shown, the patterned second photoresist layer 252 is removed.

[0061] In Figures 15 to 17 In the technical solution shown, the first opening and the sixth opening 266 are used to etch the second opening 262 and the third opening 263 simultaneously, which can simplify the process difficulty and save the etching dose.

[0062] Compared with Figures 1 to 6 In the technical solution of the present application, only two masks (the patterned first photoresist layer 251 and the patterned second photoresist layer 252) are used to perform two photolithography processes to form the first opening 261, the second opening 262 and the third opening 263. The process is simplified, the photolithography steps are saved, and the cost is saved. Moreover, the technical solution of the present application can also be applied to capacitors containing more electrode layers, such as five electrode layers, or the semiconductor substrate also serving as an electrode layer. Moreover, the semiconductor substrate also serving as an electrode layer and the total electrode layer being five or six layers can also be completed by the lowest three photolithography and etching to form all the electrode layer openings.

[0063] Specifically, Figures 1 to 6In the illustrated technical solution, the electrode layers are etched layer by layer, with each photolithography step etching only one electrode layer and exposing that layer. Therefore, when there are n electrode layers, n-1 etching steps are required to expose each electrode layer. For example, with four electrode layers, three etching steps are needed; with five electrode layers, four etching steps are needed; with six electrode layers, five etching steps are needed; with seven electrode layers, six etching steps are needed; with eight electrode layers, seven etching steps are needed; and with nine electrode layers, eight etching steps are needed.

[0064] In the technical solution of this application, the electrode layers are not etched layer by layer. By changing the photolithography pattern and the number of etching layers, two or more electrode layers can be etched at once, thus reducing the number of etching steps required to expose all electrode layers. Specifically, the applicant has discovered that the relationship between the number of etching steps and the number of electrode layers in the technical solution of this application is 2. m The number of lithography (or etching) steps for each electrode layer is greater than (n-1), where n is the total number of electrode layers. This means that each electrode layer can be connected to the contact hole in one step. The number of lithography (or etching) steps required for each electrode layer is the smallest positive integer m that satisfies the above inequality. For example, when there are four electrode layers, two to three etching steps are required (minimum two etching steps); when there are five electrode layers, three to four etching steps are required (minimum three etching steps); when there are six electrode layers, three to five etching steps are required (minimum three etching steps); when there are seven electrode layers, three to six etching steps are required (minimum three etching steps); when there are eight electrode layers, three to seven etching steps are required (minimum three etching steps); and when there are nine electrode layers, four to eight etching steps are required (minimum four etching steps).

[0065] refer to Figure 18 As shown ( Figure 18 yes Figure 17 (See subsequent figures), step S3, forming a dielectric layer 270 on the semiconductor substrate 200 covering the first electrode layer 210, the second electrode layer 220, the third electrode layer 230 and the fourth electrode layer 240.

[0066] In some embodiments of this application, the material of the dielectric layer 270 includes silicon oxide. Methods for forming the dielectric layer 270 include chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0067] refer to Figure 19 As shown, in step S4, a contact structure 280 is formed in the dielectric layer 270, which penetrates the dielectric layer 270 and electrically connects the first electrode layer 210, the second electrode layer 220, the third electrode layer 230 and the fourth electrode layer 240 respectively.

[0068] In some embodiments of the present application, the material of the contact structure 280 is a metal material or a metal compound, such as tungsten, aluminum, cobalt, etc. The method for forming the contact structure 280 includes a chemical vapor deposition process or a physical vapor deposition process, etc.

[0069] The present application provides a method for forming a capacitor, by adjusting the combination of lithography processes when etching different electrode layers, the number of lithography processes can be reduced, the process is simplified, and the cost is saved.

[0070] Figure 20 The flow chart of the method for forming a capacitor according to some embodiments of the present application.

[0071] Some embodiments of the present application also provide a method for forming a capacitor, as shown in Figure 20 , which comprises:

[0072] Step S10: providing a semiconductor substrate, a plurality of trenches are formed in the semiconductor substrate, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer are sequentially formed in the plurality of trenches and on the surface of the semiconductor substrate, wherein a plurality of first openings exposing the third electrode layer are formed in the fourth electrode layer between adjacent trenches;

[0073] Step S20: forming a second opening exposing the first electrode layer in the third electrode layer and the second electrode layer at the bottom of the first opening, and forming a third opening exposing the second electrode layer in the fourth electrode layer and the third electrode layer;

[0074] Step S30: forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer on the semiconductor substrate;

[0075] Step S40: forming a contact structure in the dielectric layer, the contact structure penetrating the dielectric layer and electrically connecting the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer respectively.

[0076] Figures 21 to 32 The structural schematic diagram of each step in the method for forming a capacitor according to some other embodiments of the present application.

[0077] Referring to Figure 20 and Figures 21 to 24As shown, a semiconductor substrate 300 is provided, in which a plurality of trenches 301 are formed, and a first electrode layer 310, a second electrode layer 320, a third electrode layer 330 and a fourth electrode layer 340 are sequentially formed in the plurality of trenches 301 and on the surface of the semiconductor substrate 300, wherein a plurality of first openings 361 exposing the third electrode layer 330 are formed in the fourth electrode layer 340 between adjacent trenches 301.

[0078] Reference is made to Figure 21 As shown, a semiconductor substrate 300 is provided, in which a plurality of trenches 301 are formed, and a first electrode layer 310, a second electrode layer 320, a third electrode layer 330 and a fourth electrode layer 340 are sequentially formed in the plurality of trenches 301 and on the surface of the semiconductor substrate 300.

[0079] In some embodiments of the present application, the material of the semiconductor substrate 300 includes (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or indium gallium phosphide, etc.; or (iv) a combination thereof. In addition, the semiconductor substrate 300 can be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 300 can be doped with a P-type dopant (e.g., boron, indium, aluminum or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0080] In some embodiments of the present application, the material of the first electrode layer 310, the second electrode layer 320, the third electrode layer 330 and the fourth electrode layer 340 includes a metal or a metal compound, such as aluminum, tungsten, etc.

[0081] In some embodiments of the present application, a first insulating layer (not shown in the figure) is further formed between the first electrode layer 310 and the second electrode layer 320; a second insulating layer (not shown in the figure) is further formed between the second electrode layer 320 and the third electrode layer 330; and a third insulating layer (not shown in the figure) is further formed between the third electrode layer 330 and the fourth electrode layer 340. The thicknesses of the first insulating layer, the second insulating layer and the third insulating layer are thinner than the thicknesses of the first electrode layer 310, the second electrode layer 320, the third electrode layer 330 and the fourth electrode layer 340, and therefore the first insulating layer, the second insulating layer and the third insulating layer are not shown in the figures for the purpose of simplicity. However, it should be understood by those skilled in the art that the first insulating layer, the second insulating layer and the third insulating layer are objectively existent as the basic constituent structures of the deep trench capacitor.

[0082] In some embodiments of the application, the first, second and third insulating layers are made of insulating dielectric material, such as silicon oxide or silicon nitride.

[0083] Referring to Figure 22 As shown in FIG. 3C, a patterned first photoresist layer 351 is formed on the surface of the fourth electrode layer 340, which defines the position of the first opening 361.

[0084] Referring to Figure 23 As shown in FIG. 3D, the fourth electrode layer 340 is etched to form the first opening 361 using the patterned first photoresist layer 351 as a mask.

[0085] Referring to Figure 24 As shown in FIG. 3E, the patterned first photoresist layer 351 is removed.

[0086] In some embodiments of the application, the first opening 361 is not located in the middle of the adjacent trench 301, but is close to one of the adjacent trenches 301. This is to leave enough space for the third opening to be formed later. The width of the first opening 361 cannot be too small, otherwise the space for the second opening to be formed later is too small; the width of the first opening 361 also cannot be too large, otherwise the space for the third opening to be formed later is too small.

[0087] Referring to Figure 20 and Figures 25 to 30 As shown in FIG. 3F, in step S20, a second opening 362 is formed in the third electrode layer 330 and the second electrode layer 320 at the bottom of the first opening 361 to expose the first electrode layer 310, and a third opening 363 is formed in the fourth electrode layer 340 and the third electrode layer 330 to expose the second electrode layer 320.

[0088] Referring to Figure 25 As shown in FIG. 3G, a patterned second photoresist layer 352 is formed on the surface of the third electrode layer 330 exposed by the first opening and on the surface of the fourth electrode layer 340, which defines the position of the second opening 362 and the third opening 363.

[0089] In some embodiments of the application, the patterned second photoresist layer 352 includes a fourth opening 364 and a fifth opening 365, wherein the fourth opening 364 defines the position of the second opening 362, and the fifth opening 365 defines the position of the third opening 363.

[0090] Referring to Figure 26As shown, the third electrode layer 330 and the second electrode layer 320 at the bottom of the first opening are etched simultaneously to form the second opening 362 and the third opening 363.

[0091] Referring to Figure 27 As shown, the patterned second photoresist layer 352 is removed.

[0092] Referring to Figure 28 As shown Figure 28 In other embodiments Figure 24 of the subsequent figures), in other embodiments of the present application, the patterned second photoresist layer 352 includes a sixth opening 366, which is located at the boundary of the first opening and defines the positions of the second opening 362 and the third opening 363.

[0093] Referring to Figure 29 As shown, the third electrode layer 330 and the second electrode layer 320 at the bottom of the first opening are etched simultaneously to form the second opening 362 and the third opening 363.

[0094] Referring to Figure 30 As shown, the patterned second photoresist layer 352 is removed.

[0095] In Figures 28 to 30 The technical solution shown in the technical solution, only the first opening sixth opening 366 to etch to form the second opening 362 and the third opening 363, can simplify the process difficulty, save etching dose.

[0096] Compared with Figures 1 to 6 The technical solution of the present application only needs to use two masks (patterned first photoresist layer 351 and patterned second photoresist layer 352) to perform two photoetching processes to form the first opening 361, the second opening 362 and the third opening 363. Simplify the process, save the photoetching step, save the cost. And the technical solution of the present application can also be applied to capacitors containing more electrode layers, such as five electrode layers, or the semiconductor substrate also as the electrode layer. And the semiconductor substrate also as the electrode layer and the total electrode layer is five or six layers can also be in the form of the lowest three times of photoetching to complete the opening manufacturing of all electrode layers.

[0097] Specifically, Figures 1 to 6In the illustrated technical solution, the electrode layers are etched layer by layer, with each photolithography step etching only one electrode layer and exposing that layer. Therefore, when there are n electrode layers, n-1 etching steps are required to expose each electrode layer. For example, with four electrode layers, three etching steps are needed; with five electrode layers, four etching steps are needed; with six electrode layers, five etching steps are needed; with seven electrode layers, six etching steps are needed; with eight electrode layers, seven etching steps are needed; and with nine electrode layers, eight etching steps are needed.

[0098] In the technical solution of this application, the electrode layers are not etched layer by layer. By changing the photolithography pattern and the number of etching layers, two or more electrode layers can be etched at once, thus reducing the number of etching steps required to expose all electrode layers. Specifically, the applicant has discovered that the relationship between the number of etching steps and the number of electrode layers in the technical solution of this application is 2. m The number of lithography (or etching) steps for each electrode layer is greater than (n-1), where n is the total number of electrode layers. This means that each electrode layer can be connected to the contact hole in one step. The number of lithography (or etching) steps required for each electrode layer is the smallest positive integer m that satisfies the above inequality. For example, when there are four electrode layers, two to three etching steps are required (minimum two etching steps); when there are five electrode layers, three to four etching steps are required (minimum three etching steps); when there are six electrode layers, three to five etching steps are required (minimum three etching steps); when there are seven electrode layers, three to six etching steps are required (minimum three etching steps); when there are eight electrode layers, three to seven etching steps are required (minimum three etching steps); and when there are nine electrode layers, four to eight etching steps are required (minimum four etching steps).

[0099] refer to Figure 31 As shown ( Figure 31 yes Figure 30 (See subsequent figures), in step S30, a dielectric layer 370 is formed on the semiconductor substrate 300, covering the first electrode layer 310, the second electrode layer 320, the third electrode layer 330 and the fourth electrode layer 340.

[0100] In some embodiments of this application, the dielectric layer 370 is made of silicon oxide. Methods for forming the dielectric layer 370 include chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0101] refer to Figure 32 As shown, in step S40, a contact structure 380 is formed in the dielectric layer 370, which penetrates the dielectric layer 370 and electrically connects the first electrode layer 310, the second electrode layer 320, the third electrode layer 330 and the fourth electrode layer 340 respectively.

[0102] In some embodiments of the present application, the material of the contact structure 380 is a metal material or a metal compound, such as tungsten, aluminum, cobalt, etc. The method of forming the contact structure 380 includes a chemical vapor deposition process or a physical vapor deposition process, etc.

[0103] The technical solution of the present application can reduce the number of photolithography processes, simplify the process, and save costs by adjusting the photolithography process combination when etching different electrode layers. The main technical principle is that, instead of etching one electrode layer after another as in the conventional process, part of the electrode layers can be exposed at the same time after etching through process adjustment, thereby saving the number of etching processes. In addition, the present application only takes a capacitor with four electrode layers as an example. In fact, capacitors with more electrode layers can also apply the technical principle of the present application, such as five electrode layers, six electrode layers, etc. Moreover, in some capacitors, the semiconductor substrate is also regarded as an electrode layer. In this structure, the technical principle of the present application is also applicable.

[0104] The present application provides a method for forming a capacitor, which can reduce the number of photolithography processes, simplify the process, and save costs by adjusting the photolithography process combination when etching different electrode layers.

[0105] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only in an exemplary manner and can not be limiting. Although not explicitly stated here, those skilled in the art can understand that the present application intends to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0106] It should be understood that the term "and / or" used in the embodiments of the present application includes any or all combinations of one or more associated listed items. It should be understood that when one element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be an intermediate element.

[0107] Similarly, it should be understood that when an element such as a layer, a region or a substrate is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediate element. In contrast, the term "directly" means that there is no intermediate element. It should also be understood that the terms "comprise", "comprising", "include", or "including", as used in the present application, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0108] It will also be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments could be called a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or same reference designators denote the same elements throughout the specification.

[0109] Furthermore, the present application description describes exemplary embodiments by reference to idealized illustrative cross-sectional and / or plan and / or elevation views. Consequently, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, exemplary embodiments should not be construed as limited to the precise shapes and regions shown herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Consequently, the regions illustrated in the figures are schematic and not drawn to scale. The same reference numerals or same reference designators denote the same elements throughout the specification.

Claims

1. A method of forming a capacitor, characterized by, The method comprises the following steps: providing a semiconductor substrate, a plurality of trenches are formed in the semiconductor substrate, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer are sequentially formed in the plurality of trenches and on the surface of the semiconductor substrate; forming a patterned first photoresist layer on the surface of the fourth electrode layer, the patterned first photoresist layer defines the position of a first opening, and the fourth electrode layer and the third electrode layer are etched to form the first opening by taking the patterned first photoresist layer as a mask, wherein the first opening penetrates the third electrode layer and the fourth electrode layer between adjacent trenches and exposes the surface of the second electrode layer, and the position of the first opening is close to one of the adjacent trenches; removing the patterned first photoresist layer; forming a patterned second photoresist layer on the surface of the second electrode layer exposed by the first opening and the surface of the fourth electrode layer, the patterned second photoresist layer defines the positions of a second opening and a third opening, and the second electrode layer and the fourth electrode layer are etched to form the second opening and the third opening by taking the patterned second photoresist layer as a mask, wherein the second opening penetrates the part of the second electrode layer exposed by the first opening and exposes the first electrode layer, and the third opening penetrates part of the fourth electrode layer and exposes the third electrode layer; removing the patterned second photoresist layer; forming a dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer on the semiconductor substrate; forming a contact structure in the dielectric layer, the contact structure penetrates the dielectric layer and is electrically connected to the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer respectively.

2. The method of forming a capacitor of claim 1 wherein, The patterned second photoresist layer comprises a fourth opening and a fifth opening, wherein the fourth opening defines the position of the second opening, and the fifth opening defines the position of the third opening.

3. The method of forming a capacitor of claim 1 wherein, The patterned second photoresist layer comprises a sixth opening, the sixth opening is located at the boundary of the first opening and simultaneously defines the positions of the second opening and the third opening.

4. The method of forming a capacitor of claim 1 wherein, A first insulating layer is further formed between the first electrode layer and the second electrode layer; a second insulating layer is further formed between the second electrode layer and the third electrode layer; and a third insulating layer is further formed between the third electrode layer and the fourth electrode layer.

5. A method of forming a capacitor, characterized by, The method comprises the following steps: providing a semiconductor substrate, a plurality of trenches are formed in the semiconductor substrate, and a first electrode layer, a second electrode layer, a third electrode layer and a fourth electrode layer are sequentially formed in the plurality of trenches and on the surface of the semiconductor substrate; forming a patterned first photoresist layer on the surface of the fourth electrode layer, the patterned first photoresist layer defines the position of a first opening, and the fourth electrode layer and the third electrode layer are etched to form the first opening by taking the patterned first photoresist layer as a mask, wherein the first opening penetrates the third electrode layer and the fourth electrode layer between adjacent trenches and exposes the surface of the second electrode layer, and the position of the first opening is close to one of the adjacent trenches; removing the patterned first photoresist layer; forming a patterned second photoresist layer on the third electrode layer surface exposed by the first opening and the fourth electrode layer surface, the patterned second photoresist layer defining positions of the second opening and the third opening, and etching the third electrode layer and the second electrode layer at the bottom of the first opening and the fourth electrode layer and the third electrode layer to form the second opening and the third opening simultaneously using the patterned second photoresist layer as a mask, wherein the second opening penetrates the third electrode layer and the second electrode layer exposed by the first opening and exposes the first electrode layer, and the third opening penetrates the fourth electrode layer and the third electrode layer and exposes the second electrode layer; and removing the patterned second photoresist layer; forming a dielectric layer on the semiconductor substrate, the dielectric layer covering the first electrode layer, the second electrode layer, the third electrode layer, and the fourth electrode layer; forming a contact structure in the dielectric layer, the contact structure penetrating the dielectric layer and electrically connecting the first electrode layer, the second electrode layer, the third electrode layer, and the fourth electrode layer, respectively.

6. The method of forming a capacitor of claim 5, wherein, The patterned second photoresist layer includes a fourth opening and a fifth opening, wherein the fourth opening defines the position of the second opening, and the fifth opening defines the position of the third opening.

7. The method of forming a capacitor of claim 5, wherein, The patterned second photoresist layer includes a sixth opening, the sixth opening being located at the boundary of the first opening and defining the positions of the second opening and the third opening simultaneously.

8. The method of forming a capacitor of claim 5, wherein, The first electrode layer and the second electrode layer further have a first insulating layer therebetween; the second electrode layer and the third electrode layer further have a second insulating layer therebetween; and the third electrode layer and the fourth electrode layer further have a third insulating layer therebetween.

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