Vertical dram structure and method

Abstract

The present disclosure relates to vertical DRAM structures and methods. Embodiments of the present disclosure provide a lateral channel dynamic random access memory (DRAM) cell and cell array utilizing a vertical design with lateral channel transistors. A dielectric layer is disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer surrounds the gate electrode, and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure further includes a dielectric structure disposed over the conductive structure and the gate electrode, with the channel layer extending upward through the dielectric structure.

Description

Technical Field

[0001] This disclosure relates to vertical DRAM structures and methods. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed.

[0004] Semiconductor memory devices include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). A DRAM memory cell has only one transistor and one capacitor, thus offering a high degree of integration. Vertical DRAM provides DRAM technology in a smaller size, which creates potential additional problems that need to be addressed. Summary of the Invention

[0005] According to one embodiment of the present disclosure, a semiconductor structure is provided, comprising: a dielectric layer disposed on a substrate; a gate electrode embedded in the dielectric layer; a channel layer surrounding the gate electrode; a conductive structure adjacent to the channel layer, the channel layer being disposed between the gate electrode and the conductive structure; and a dielectric structure disposed on the conductive structure and the gate electrode, the channel layer extending upward through the dielectric structure.

[0006] According to another embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a conductive line in a substrate; depositing an insulating layer on the substrate; patterning a first opening in the insulating layer, the first opening extending perpendicular to the conductive line; forming a conductive structure in the first opening; patterning a second opening in the insulating layer, the second opening exposing sidewalls of the conductive structure and the conductive line; depositing a channel layer in the second opening; depositing a gate dielectric layer on the channel layer; depositing a gate electrode on the gate dielectric layer; recessing the gate dielectric layer, the gate electrode, and the conductive structure, the channel layer extending above the gate electrode; and depositing an isolation structure around the channel layer, the isolation structure having an upper surface flush with the upper surface of the channel layer.

[0007] According to another embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising: depositing a channel structure in a first opening disposed between two conductive structures, the channel structure being lined within the first opening, the bottom of the channel structure extending along a conductive element embedded in a substrate, wherein a first isolation structure is interposed between the two conductive structures and the substrate, and the first opening exposing a portion of the first isolation structure; depositing a gate dielectric layer in the first opening, the gate dielectric layer being lined within the first opening on the channel structure; depositing a gate electrode in the first opening, the gate electrode filling the first opening; recessing the upper surfaces of the two conductive structures and the upper surface of the gate electrode, the first portion of the channel structure being exposed from the two conductive structures and the gate electrode; and depositing a second isolation structure over the upper surfaces of the two conductive structures and the upper surface of the gate electrode, the second isolation structure laterally surrounding the first portion of the channel structure. Attached Figure Description

[0008] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1A , Figure 1B and Figures 1C to 10A , Figure 10B and Figure 10C Intermediate steps for forming a portion of a DRAM array according to some embodiments are shown.

[0010] Figure 11A , Figure 11B , Figure 11C and Figure 11D Based on other embodiments Figure 8B The process of continuing the structure shown.

[0011] Figure 12A , Figure 12B and Figure 12C Based on other embodiments Figure 8B The process of continuing the structure shown.

[0012] Figure 13A , Figure 13B , Figure 13C and Figure 13D Based on other embodiments Figure 8B The process of continuing the structure shown.

[0013] Figure 14A and Figure 14BA cross-sectional view of the formation of a ground gate according to some embodiments is shown. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "lower than," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0016] Embodiments of this disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array utilizing a vertical design with side-channel transistors. Vertically designed DRAM enables the completion of memory cells and arrays using less surface area. However, as the layout becomes more compact, write line coupling can occur, leading to undesirable electrical performance. Furthermore, body effects can also be a problem, where the voltage threshold of a transistor cell is affected by the voltage bias of the body material between adjacent transistors. Embodiments include vertical DRAM designs that advantageously eliminate or reduce body effects and word line (WL) coupling. Since there are no inherent size limitations on the channel and gate, the embodiments also advantageously provide good dimensional scalability. Therefore, the capacitor recovery time can be unaffected by scaling.

[0017] A DRAM memory cell includes transistors, such as field-effect transistors, where the gate input is connected to the word line (WL), the first leg is connected to the bit line (BL), and the second leg is connected to a charging capacitor. The other end of the capacitor is connected to a first reference voltage, such as ground. The DRAM operates in write mode as follows: a charging voltage or the first reference voltage (e.g., ground) is applied to the BL, and then the WL charges or discharges the capacitor, thereby writing a 1 or 0 to the capacitor, respectively. The DRAM operates in read mode as follows: a second reference voltage, between the charging voltage and the first reference voltage, is applied to the BL. The WL is then enabled. If the BL voltage increases as the capacitor begins to discharge to the BL, it is determined to be 1. If the BL voltage decreases as it begins to charge the capacitor, it is determined to be 0.

[0018] Figure 1A , Figure 1B and Figures 1C to 10A , Figure 10B and Figure 10C The intermediate steps for forming a portion of a DRAM array comprising several DRAM cells are shown. Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A A plan view is shown, and several features from several horizontal cross-sections can be included in a single view. These will be identified in the following discussion. Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B The following are shown respectively along Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A A cross-sectional view of the BB reference line (through BL, along the length of BL). Figure 1C , Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C and Figure 10C The following are shown respectively along Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A A cross-sectional view of the CC reference line. Figure 2D and Figure 3D The following are shown respectively along Figure 2A and Figure 3A The cross-sectional view of the DD reference line is shown. It should be understood that the processes described and illustrated herein can be replicated on any number of DRAM cells and DRAM arrays on a single substrate or device. It should also be understood that DRAM cells and / or DRAM arrays require additional circuitry for operation, such as voltage sensing devices, multiplexing devices, and control devices known to those skilled in the art.

[0019] Figure 1A , Figure 1B and Figure 1C A substrate 100 and a dielectric layer 110 are shown, with any number of layers and device features inserted between them. Figure 1A It's a floor plan. Figure 1B It is along Figure 1A The cross-sectional view of line BB, and Figure 1C It is along Figure 1A A cross-sectional view of line CC. Substrate 100 may be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed of other semiconductor materials. Substrate 100 may be doped with p-type or n-type impurities. In other embodiments, substrate 100 may be a carrier substrate, such as a glass carrier, a ceramic carrier, etc. Dielectric layer 110 may be any suitable dielectric layer type. In some embodiments, dielectric layer 110 may be an interlayer dielectric (ILD) or an intermetallic dielectric (IMD), etc., and may be a layer in a redistribution structure or interconnect. Dielectric layer 110 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition process. Dielectric layer 110 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based dielectric material, such as silicon oxide (e.g., formed using tetraethyl orthosilicate (TEOS) as a process gas), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.

[0020] Next, trenches are formed in the dielectric layer 110. The trenches can be formed using a suitable photolithography process. For example, a resist layer (not shown) can be formed over the dielectric layer 110 and exposed to a light source using a photomask, which is then patterned onto the resist layer. Next, the resist layer is developed and cured, forming openings in the resist layer according to the pattern of the photomask. The resist layer is used as a mask to perform an etching process. The etching process can include wet and / or dry etching processes to transfer the openings in the resist layer to the underlying layer. In some embodiments, an additional etching mask can be used between the resist layer and the target layer (in this case, the dielectric layer 110). In some embodiments, the etching process uses isotropic etching to pattern the trenches into the dielectric layer 110.

[0021] After the trench is formed, BL 115 is formed by depositing a conductive material in the trench, for example by depositing a seed layer, and then performing an electroplating process to deposit the conductive material. The conductive material of BL 115 may include any suitable material, such as copper, tin, tungsten, cobalt, aluminum, gold, titanium, titanium nitride, tantalum, tantalum nitride, alloys thereof, combinations thereof, etc. In some embodiments, a barrier layer may be deposited first to inhibit the diffusion of the conductive material into the surrounding dielectric layer 110. The barrier layer may be formed of any suitable material such as titanium nitride and may be deposited by CVD, PVD, ALD, or another suitable process. A planarization process (e.g., CMP) may then be used to make the upper surface of BL 115 flush with the upper surface of dielectric layer 110.

[0022] Other processes can be used to form BL 115 in dielectric layer 110, including, for example, first forming BL 115, then forming dielectric layer 110 around BL 115, and then performing a planarization process to make the upper surface of BL 115 flush with the upper surface of dielectric layer 110.

[0023] exist Figure 2A , Figure 2B , Figure 2C and Figure 2D In the process, a dielectric layer 120 is formed and trenches are formed therein. The trenches 125 are formed such that they do not completely penetrate the thickness of the dielectric layer 120. Figure 2A It's a floor plan. Figure 2B It is along Figure 2A A cross-sectional view of line BB. Figure 2C It is along Figure 2A The cross-sectional view of line CC, and Figure 2D It is along Figure 2A A cross-sectional view of line DD.

[0024] First, a dielectric layer 120 is formed on top of BL 115 and dielectric layer 110. Dielectric layer 120 may comprise a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition process. Dielectric layer 120 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based dielectric material, such as silicon oxide (e.g., formed using tetraethyl orthosilicate (TEOS) as a process gas), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. The thickness t1 of dielectric layer 120 may be between approximately 50 nm and 5000 nm.

[0025] Next, the dielectric layer 120 is patterned to form trenches 125. The trenches 125 extend perpendicular to the longitudinal direction of BL 115. Figure 2A The view in the image combines a view of trench 125 and a view of dielectric layer 120 (the bottom of dielectric layer 120 is omitted). For example... Figure 2B As shown, BL 115 extends continuously beneath trench 125. Trench 125 can be formed using any suitable photolithography and etching process, such as the process described above regarding patterning of dielectric layer 110. The etching process can use timed etching such that the bottom of trench 125 is positioned between the bottom and top of dielectric layer 120. A ground gate will be formed in trench 125, and the thickness t2 of dielectric layer 120 remaining between the bottom of trench 125 and BL 115 isolates BL 115 from the ground gate. In some embodiments, thickness t2 can be between about 1 nm and 50 nm. A smaller thickness t2 is desirable to reduce bulk effects and reduce the area required per DRAM cell. However, if the thickness t2 is too small, breakdown or leakage of the ground gate (which is subsequently formed in trench 125) to BL 115 may occur. In some embodiments, the target thickness t2 is determined by the thickness of the subsequently formed gate channel and gate insulating layer, which will be discussed further below.

[0026] exist Figure 3A , Figure 3B , Figure 3C and Figure 3D In the trench 125, a ground gate 140 including an adhesive layer 130 and a ground gate electrode 135 is formed. Figure 3A It's a floor plan. Figure 3B It is along Figure 3A A cross-sectional view of line BB. Figure 3C It is along Figure 3A The cross-sectional view of line CC, and Figure 3D It is along Figure 3A A cross-sectional view of line DD. (See diagram below.) Figure 3BAs shown, BL 115 continues to pass beneath dielectric layer 120. Ground gate 140 provides a ground plane between each side channel and prevents or reduces coupling effects between adjacent WLs. Preventing or reducing coupling effects improves the controllability of the resulting memory cell or array because it prevents adjacent WLs from affecting neighboring WLs. Ground gate 140 also reduces body effects by eliminating voltage potentials that might otherwise exist in the dielectric or bulk material between the gates of the memory transistors. It should be understood that although the term "ground gate" is used, the potential provided at ground gate 140 can be any suitable reference voltage.

[0027] The ground gate 140 is formed by first depositing a resist layer 130 in each trench 125 and over the upper surface of the dielectric layer 120. The resist layer 130 can be deposited by any suitable process, such as CVD, PVD, ALD, or combinations thereof. The resist layer 130 is conformally deposited and provides stability between the subsequently formed trench and the ground gate electrode 135. The resist layer 130 can be made of any suitable material, such as titanium nitride, and can be doped or undoped of silicon. Next, the ground gate electrode 135 is deposited in the remaining trenches 125. The ground gate electrode 135 can be a metallic material, such as tungsten or cobalt, and can be deposited by any suitable process, such as electroplating, electroless plating, CVD, or combinations thereof. Subsequently, a planarization process, such as CMP or mechanical polishing, is performed such that the resist layer 130, the ground gate electrode 135, and possibly portions of the dielectric layer 120 are removed and their upper surfaces are flush with each other. As a result, a gel layer 130 and a ground gate electrode 135 are formed, which are collectively referred to as ground gate 140.

[0028] exist Figure 4A , Figure 4B and Figure 4C In the dielectric layer 120, trenches 145 are formed. Figure 4A It's a floor plan. Figure 4B It is along Figure 4A The cross-sectional view of line BB, and Figure 4C It is along Figure 4A A cross-sectional view of line CC. Figure 4A The view in the image combines views of trench 145, ground gate 140, and BL 115. Figure 4A The view in the diagram omits the view of the photoresist 143. The trench 145 can be formed using any suitable photolithography and etching process. For example, the photoresist 143 can be deposited on the ground gate 140 and patterned to expose portions of the dielectric layer 120 between the ground gates 140. In some embodiments, etching the trench 145 can use the ground gate 140 as part of an etching mask to perform self-aligned etching of the trench 145, such as... Figure 4BAs shown, the patterned photoresist 143 exposes a portion of the ground gate 140. In other embodiments, etching of the trench 145 may be performed using wet etching, or a combination of wet and dry etching, to etch the dielectric layer 120 between the ground gates 140, such that the dielectric layer 120 across the entire width of the ground gates 140 is removed. In this case, the patterned photoresist 143 may be slightly overhanging the width of the ground gate 140, such as... Figure 4B The photoresist 143 on the right is shown. Etching can be performed using BL 115 and dielectric layer 110 as an etch stop, so that trench 145 completely penetrates dielectric layer 120 and exposes the bottom BL 115 and the side ground gate 140 (adhesive layer 130).

[0029] exist Figure 5A , Figure 5B and Figure 5C In the middle, material for channel 150 is deposited in trench 145. Figure 5A It's a floor plan. Figure 5B It is along Figure 5A The cross-sectional view of line BB, and Figure 5C It is along Figure 5A A cross-sectional view of line CC. Figure 5A The view in the image combines views of the material used for channel 150, ground gate 140, and BL 115. (BL 115 will be invisible from top to bottom, and channel 150 will appear as a vertical line between ground gate 140). The material used for channel 150 can be deposited using any suitable process, such as ALD, PVD, CVD, molecular beam epitaxy (MBE), or combinations thereof. The resulting channel 150 can be conformally deposited (with a thickness variation of no more than about 25% on the bottom and side surfaces) in trench 145 and above ground gate 140. The material of channel 150 can be an oxide of silicon or a semiconductor material, such as IGZO (indium gallium zinc oxide), IWO (indium tungsten oxide), IZO (indium zinc oxide), ITO (indium tin oxide), or combinations thereof. The thickness of the channel is adjustable. If the channel is too thin, it will not be able to maintain a sufficiently large current throughput. If the channel is too thick, large current leakage is more likely to occur. In some embodiments, the channel 150 may be deposited to a thickness between about 1 nm and about 30 nm. After deposition, a planarization process such as CMP can be used to remove the upper portion of the channel 150 above the ground gate 140.

[0030] exist Figure 6A , Figure 6B and Figure 6C In the middle, the channel 150 is cut for each storage cell. Figure 6A It's a floor plan. Figure 6B It is along Figure 6AThe cross-sectional view of line BB, and Figure 6C It is along Figure 6A A cross-sectional view of line CC. Figure 6A The view in the diagram combines the material used for the channel 150 (showing the vertical leg 150v separated from the horizontal portion 150h) and the view of the ground gate 140. The channel 150 can be cut using any suitable process. In one embodiment, the channel 150 can be cut using a suitable photolithography and etching process, including depositing a photomask (not shown), patterning a photomask, and etching the exposed portions of the channel 150. The channel 150 is cut such that the remaining portion of the channel 150 extends perpendicular to the longitudinal direction of the ground gate 140. After the channel 150 is cut, the remaining channel 150 is a U-shaped channel 150 with vertical legs 150v separated from the ground gate 140. The horizontal portion 150h of the channel 150 is directly disposed on the BL 115. Figure 6C As shown, the width of channel 150 can be wider than BL 115 to be suspended above BL 115. Suspending channel 150 above BL 115 makes all BL 115 below channel 150 contact a portion of channel 150 and provides more channel material at BL 115 for current transmission through channel 150.

[0031] exist Figure 7A , Figure 7B and Figure 7C In the middle, a gate insulating layer and a gate electrode are deposited on the channel 150 to fill the opening 145. Figure 7A It's a floor plan. Figure 7B It is along Figure 7A The cross-sectional view of line BB, and Figure 7C It is along Figure 7A A cross-sectional view of the CC line. The gate insulating layer 155 can be conformally deposited using any suitable technique, such as CVD, ALD, or a combination thereof. The gate insulating layer 155 is deposited over the channel 150 and lined with the opening 145 between the cleaved channels 150. The gate insulating layer 155 can be any suitable material, such as a high-k dielectric layer. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and can be greater than about 7.0. In some embodiments, the high-k dielectric material of the gate insulating layer 155 may include alumina, tantalum oxide, STO (strontium titanate), BST (barium strontium titanate), titanium oxide, hafnium oxide, zirconium oxide, lanthanum oxide, praseodymium oxide, etc. The gate insulating layer 155 can be deposited to a thickness between about 1 nm and about 100 nm.

[0032] After depositing the gate insulating layer 155, the gate electrode (as WL 160) is deposited in the remaining opening 145. WL 160 can be deposited using any suitable technique, such as electroplating, electroless plating, CVD, PVD, ALD, or combinations thereof. WL 160 may include one or more stacked conductive layers. Although not shown individually, the stacked layers can be distinguished from each other. In some embodiments, the deposition of the stacked layers can be performed using conformal deposition techniques such as ALD or CVD, and can be constructed from layers of distinct materials, including work function metals and dielectrics. Work function metals may include, for example, molybdenum, titanium nitride, tungsten, tantalum nitride, titanium aluminum nitride, and ruthenium oxide, or combinations thereof. The final layer of WL 160 may be a conductive filler deposited using a fill technique. The individual layers can work together to set the electrical characteristics of the gate, such as a voltage threshold that enables the gate to provide current flowing through channel 150.

[0033] After depositing gate insulating layers 155 and WL 160, gate insulating layers 155 and WL 160 can be planarized, for example, by a CMP process, to remove excess portions of gate insulating layers 155 and WL 160 and to make the ground gate 140, channel 150, and the upper surfaces of gate insulating layers 155 and WL 160 flush.

[0034] exist Figure 8A , Figure 8B and Figure 8C In this configuration, gate insulating layer 155, WL 160, and ground gate 140 are recessed, and an isolation layer 165 is deposited in the recess. The isolation layer 165 provides isolation between the subsequently formed cell capacitor and WL 160 and ground gate 140. Figure 8A It's a floor plan. Figure 8B It is along Figure 8A The cross-sectional view of line BB, and Figure 8C It is along Figure 8A A cross-sectional view of line CC. Figure 8AThe plan view incorporates a view including the ground gate 140, which is not visible from top to bottom. Recessing of the gate insulating layer 155, WL 160, and ground gate 140 can be performed using a suitable etchant for their respective materials. In some embodiments, etching can be performed using a dry etching process, such as using one or more suitable etching gases. In other embodiments, recessing of the gate insulating layer 155, WL 160, and ground gate 140 can be performed using a wet etching process using one or more suitable etching chemicals or solutions. Although the upper surfaces of each of the ground gate 140, gate insulating layer 155, and WL 160 are shown flush with each other, these upper surfaces may have different heights depending on the etching rate and etching conditions of the recessing process. In some embodiments, the gate insulating layer 155 may not be recessed.

[0035] After the recessed ground gate 140, gate insulating layer 155, and WL 160, an isolation layer 165 is deposited in the recess. In some embodiments, before depositing the isolation layer 165, the exposed extended legs of the channel 150 may be doped with a suitable dopant. For example, the dopant may include phosphorus, antimony, bismuth, hydrogen, nitrogen, another suitable dopant, or a combination thereof. The dopant may be included in situ during the deposition of the channel 150 and / or the dopant may be implanted during a separate implantation process. The implantation process may utilize angular implantation at an angle between 0° and 55°. After implantation, the concentration level of the dopant in the exposed extended legs of the channel 150 may be 10 16 atoms / cm 3 To about 10 20 atoms / cm 3 Between. In some embodiments, the doping concentration may have a decreasing gradient moving downwards along the legs of channel 150 (e.g., from the upper surface of ground gate 140) toward the horizontal portion 150h of the channel. In some embodiments, the doping concentration of the horizontal portion 150h of channel 150 may be less than the dopant concentration in the legs of channel 150. After implantation, annealing may be performed to repair channel 150 and activate the dopant.

[0036] The isolation layer 165 can be deposited using any suitable technique, such as CVD, PVD, or combinations thereof. The isolation layer 165 can be made of any suitable isolation material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, silicon carbonitride, or combinations thereof. During the deposition of the isolation layer 165, ambient hydrogen (e.g., H+ when used as a process gas) is deposited in the isolation layer 165. In subsequent processes, hydrogen can diffuse from the isolation layer 165 into the channel 150, combining with oxygen vacancies to enhance doping into the channel 150, through the resulting Vo as a shallow donor. O-H(Oxygen vacancies trap hydrogen) improve channel conductivity (i.e., provide additional electrons). After the deposition of the isolation layer 165, a planarization process, such as a CMP process, can be performed to make the upper surface of the isolation layer 165 flush with the upper surface of the channel 150. The thickness of the resulting isolation layer 165 can be in the range of about 1 nm to about 100 nm.

[0037] exist Figure 9A , Figure 9B and Figures 9C to 10A , Figure 10B and Figure 10C In some embodiments, a unit capacitor 190 is formed over each channel 150. The unit capacitor 190 can be formed using other processes to produce alternative configurations, such as... Figures 11A to 13D The configuration shown is in [the image]. Figure 9A , Figure 9B and Figure 9C In this process, the insulating layer 170 is deposited on the insulating layer 165 and on the exposed upper surface of the trench 150. Figure 9A It's a floor plan. Figure 9B It is along Figure 9A The cross-sectional view of line BB, and Figure 9C It is along Figure 9A A cross-sectional view of line CC.

[0038] The insulating layer 170 can be made of any suitable insulating material, such as a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition process. The insulating layer 170 can be formed of an oxygen-containing dielectric material, which can be a silicon oxide-based dielectric material, such as silicon oxide (e.g., formed using tetraethyl orthosilicate (TEOS) as a process gas), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.

[0039] After depositing the insulating layer 170, an opening 172 can be formed in the insulating layer 170. For example... Figure 9A , Figure 9B and Figure 9C As shown, opening 172 exposes the upper surface of the side channel 150 of each cell. Opening 172 can be formed using any suitable process, such as by photolithography and etching processes as described above. Although opening 172 is shown as having vertical sidewalls, the sidewalls may be tapered, such that the width of the top of opening 172 is greater than the width of the bottom of opening.

[0040] exist Figure 10A , Figure 10B and Figure 10C In this process, a metal-insulator-metal (MIM) unit capacitor 190 is formed in each opening 172. Figure 10A It's a floor plan. Figure 10BIt is along Figure 10A The cross-sectional view of line BB, and Figure 10C It is along Figure 10A A cross-sectional view of line CC. The unit capacitor 190 can be formed by any suitable process. In one process, a series of conformal layers are deposited in the opening 172 via a conformal deposition process (e.g., by ALD or CVD, etc.). The first such conformal layer is the bottom electrode layer 175. Next, a capacitor dielectric layer 180 is deposited on the bottom electrode layer 175 in the opening 172. Finally, a top electrode 185 is deposited on top of the capacitor dielectric layer 180. The bottom electrode 175, the capacitor dielectric layer 180, and the top electrode 185 together are referred to as the unit capacitor 190.

[0041] The bottom electrode layer 175 can be made of any suitable conductive material, such as titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof. The top electrode layer 185 can be made of any candidate material that serves as the bottom electrode 175, and in some embodiments, it can be made of the same material as the bottom electrode 175. The capacitor dielectric layer 180 may include a nitride layer, a silicon nitride layer, or other dielectric material layers with high dielectric constants. In some embodiments, the capacitor dielectric layer 180 is a silicon nitride layer deposited by a low-temperature CVD or plasma-enhanced CVD (PECVD) method.

[0042] After the top electrode layer 185 is formed, a planarization process can be used to remove excess material from the insulating layer 170. The planarization process also flushes the upper surfaces of the top electrode layer 185, the capacitor dielectric layer 180, and the bottom electrode layer 175.

[0043] Figure 11A , Figure 11B , Figure 11C and Figures 11D to 13A , Figure 13B , Figure 13C and Figure 13D Other processes and structures for forming capacitors according to some embodiments are shown. Figure 11A , Figure 11B , Figure 11C and Figures 11D to 13A , Figure 13B , Figure 13C and Figure 13D Each diagram in the diagram represents Figure 8B A partial cross-sectional view of the structure shown, and for Figure 8B The structure shown includes additional processes for forming the cell capacitor 190, which is a metal-insulator-metal (MIM) capacitor for each memory cell. Unless otherwise stated, the same references refer to the same elements that can be formed using the same materials in the same manner.

[0044] Figure 11A , Figure 11B , Figure 11C and Figure 11D The intermediate steps for forming a dual-MIM capacitor structure are shown. Figure 10A , Figure 10B and Figure 10C Compared to the single-unit capacitor 190 described herein, the dual-MIM structure offers the advantage of providing greater capacitance within similar space requirements. Figure 11A In this process, an insulating layer 170 is formed over the isolation layer 165 and the channel 150. The insulating layer 170 can be used in accordance with the above-mentioned... Figure 9A , Figure 9B and Figure 9C The process and materials are similar to those described above. Next, an opening is formed in the insulating layer 170, similar to the opening 172 described above. Then, the bottom electrode layer 175 of the unit capacitor 190 is formed in the opening. The bottom electrode layer 175 can be made of any suitable conductive material, such as titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof, using any suitable process (e.g., by spin coating, FVCD, etc., or combinations thereof).

[0045] like Figure 11A As shown, the bottom electrode layer 175 may extend above the upper surface of the insulating layer 170, or in some embodiments, may be planarized with the upper surface of the insulating layer 170. A photoresist is then deposited on the insulating layer 170 and the bottom electrode layer 175 and patterned to form a photomask 177. The photoresist material of the photomask 177 can be formed using any suitable organic photoresist material and can be deposited, for example, by spin coating, FCVD, or a combination thereof.

[0046] exist Figure 11B In this process, photomask 177 is used as a mask to etch opening 179 in the bottom electrode layer 175, leaving pillars 175p of the bottom electrode layer 175 and the bottom portion of the bottom electrode layer 175 remaining in opening 172. Etching can be performed using any suitable etching process, employing a suitable etchant selective for the material of the bottom electrode layer 175. In some embodiments, a dry etching process can be used to etch the bottom electrode layer 175. During the etching process of opening 179, photomask 177 may be consumed, and the upper surface of pillar 175p is recessed below the upper surface of insulating layer 170. If photomask 177 is not consumed by etching, it can be removed by an ashing process, and the patterned bottom electrode layer 175 is etched entirely to recess the upper surface of pillar 175p below the upper surface of insulating layer 170.

[0047] The pillar 175p can be manufactured using other processes, such as depositing the bottom horizontal portion of the bottom electrode 175p using electroplating or electroless plating. Then, a mask material can be formed in the opening 172, and the mask material can be patterned to correspond to the two openings of the pillar 175p. The pillar 175p can then be formed by electroplating or electroless plating. The mask can then be removed to obtain... Figure 11B The structure.

[0048] exist Figure 11C In this configuration, a capacitor dielectric layer 180 is formed over a bottom electrode layer 175, including a pillar 175p. The capacitor dielectric layer 180 may include a nitride layer, a silicon nitride layer, or other dielectric material layers with high dielectric constants. In some embodiments, the capacitor dielectric layer 180 is a silicon nitride layer deposited by a low-temperature CVD or plasma-enhanced CVD (PECVD) method. As shown, in some embodiments, the capacitor dielectric layer 180 may extend vertically along the sidewall of the insulating layer 170 in the opening 179.

[0049] exist Figure 11D In this configuration, a top electrode layer 185 is formed in the remaining opening 179 and can extend laterally over the insulating layer 170. The top electrode layer 185 can be made of any suitable conductive material, such as titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof, using any suitable process (e.g., spin coating, FVCD, etc., or combinations thereof). After deposition, the top electrode layer 185 can extend above the upper surface of the insulating layer 170 and extend laterally over the upper surface of the insulating layer 170. A planarization process can be used to make the upper surface of the top electrode layer 185 flush with the upper surface of the insulating layer 170.

[0050] Figure 12A , Figure 12B and Figure 12C Intermediate steps for forming a MIM cell capacitor 190 according to other embodiments are shown. Figure 12A , Figure 12B and Figure 12C The unit capacitor 190 uses a portion of the channel 150 as the bottom electrode layer 175, reducing structural complexity and size, resulting in higher production efficiency. Figure 12A In the process, before forming the insulating layer 170, the insulating layer 165 is recessed to expose the vertical protrusions of the channel 150. An etch-back process can be used to recess the insulating layer 165 to achieve this recess. Then, the insulating layer 170 can be applied using the methods described above. Figure 9A , Figure 9B and Figure 9C Similar processes and materials are used for deposition and patterning. Figure 12B In the middle, a capacitor dielectric layer 180 is deposited on the channel 150. The capacitor dielectric layer 180 can (e.g., similar to) Figure 11C Alternatively, it may not (as shown in the figure) extend perpendicularly along the sidewall of the insulating layer 170. Figure 12C In this process, a top electrode layer 185 is formed on top of the capacitor dielectric layer 180 and is planarized to form a unit capacitor 190.

[0051] Figure 13A , Figure 13B , Figure 13C and Figure 13D Intermediate steps for forming a MIM cell capacitor 190 according to other embodiments are shown. Figure 13A , Figure 13B , Figure 13C and Figure 13D The unit capacitor 190 uses a portion of the channel 150 to assist in shaping the unit capacitor 190. Figure 13A In the process, before the insulating layer 170 is formed, the insulating layer 165 is recessed to expose the vertical protrusions of the channel 150. An etch-back process can be used to recess the insulating layer 165 to achieve this recess.

[0052] exist Figure 13B In this process, a bottom electrode layer 175 can be deposited in the opening 172 and over the channel 150. The bottom electrode layer 175 can be formed using a conformal deposition process, such as ALD, CVD, or a combination thereof. In some embodiments, a plating process, such as electroplating or electroless plating, can be used, utilizing the channel 150 as a seed layer for the plating process.

[0053] exist Figure 13C In this process, a capacitor dielectric layer 180 can be deposited on top of the bottom electrode layer 175. Finally, in Figure 13D In the middle, the top electrode layer 185 is deposited and the device is planarized to form the memory cell 190.

[0054] Figure 14A and Figure 14B A cross-sectional view of the formation of a ground gate 140 according to some embodiments is shown, which is laterally surrounded by a dielectric layer 128, which is also interposed between the ground gate 140 and the channel 150 to be formed. The inclusion of the dielectric layer 128 improves the reduction of WL coupling by providing another channel insulating layer between the channel 150 and the ground gate 140. Figure 14A In the middle, the dielectric layer 128 is conformally deposited on Figure 2BThe structure shown contains the opening 125 and is above the insulating layer 120. The dielectric layer 128 may include any suitable dielectric material, such as a high-k dielectric material, such as any of the candidate materials described above regarding the gate insulating layer 155, and may be deposited using a process similar to that described above regarding the gate insulating layer 155. After depositing the dielectric layer 128, in some embodiments, the horizontal portion of the dielectric layer 128 may be removed by anisotropic etching, such as... Figure 14A As shown. In other embodiments, the horizontal portion of the dielectric layer 128 may remain at the bottom of the opening 125 (below the subsequently formed ground gate 140). The process described above can continue with the dielectric layer 128, except that the dielectric layer 128 may also be recessed before the formation of the isolation layer 165.

[0055] exist Figure 14B In, it is shown Figure 10B The structure differs in that it includes a dielectric layer 128. For example... Figure 14B As shown, the dielectric layer 128 is located between the channel 150 and the ground gate 140, and extends vertically from the isolation layer 165 to the insulating layer 120.

[0056] Additional processes can be performed to enable the memory cells to function within the storage device. For example, it is possible to... Figure 10C , Figure 11D , Figure 12C , Figure 13D or Figure 14B An intermediate dielectric material is formed on top of the memory cell 190. Openings can be formed in the intermediate dielectric material, and the top electrode layer 185 can be coupled to a reference voltage, such as ground, through vias formed in the openings. A ground gate 140 can be coupled to the same reference voltage (e.g., ground) as the top electrode layer 185. WL 160 can be coupled to a word line input / output of the memory device, and BL 115 can be coupled to a bit line input / output of the memory device.

[0057] The embodiment offers several advantages. By utilizing vertical channels, with gates positioned between vertical channels and ground gates positioned between adjacent memory cells, the resulting memory cells exhibit reduced or eliminated bulk effects and reduced or eliminated WL coupling. Due to the reduced bulk effects, the threshold voltage of each cell 190 is less likely to be significantly affected, resulting in better controllability of the gate by the WL 160. Furthermore, since the channels are located on the sides rather than inside each memory cell 190, future design capabilities are improved, as the width is not a design constraint and would affect the recovery time of the memory cell 190.

[0058] One embodiment is a semiconductor structure including a dielectric layer disposed on a substrate. The semiconductor structure also includes a gate electrode embedded in the dielectric layer. The semiconductor structure further includes a channel layer surrounding the gate electrode, and a conductive structure adjacent to the channel layer, the channel layer being disposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed on the conductive structure and the gate electrode, the channel layer extending upward through the dielectric structure. In one embodiment, the semiconductor structure further includes a unit capacitor disposed on and coupled to the channel layer. In one embodiment, the unit capacitor includes a bottom electrode, a capacitor dielectric layer disposed on the bottom electrode, and a top electrode disposed on the capacitor dielectric layer. In one embodiment, there is no dielectric structure on the upper portion of the channel layer, wherein the bottom electrode of the unit capacitor includes the upper portion of the channel layer, the capacitor dielectric layer extending along the sidewalls and upper surface of the upper portion of the channel layer. In one embodiment, the semiconductor structure further includes a channel insulating layer, disposed between the channel layer and the conductive structure. In one embodiment, the semiconductor structure further includes a conductive wire embedded in the substrate, the channel layer being coupled to the conductive wire. In one embodiment, the interface between the channel layer and the conductive wire is laterally surrounded by the dielectric layer. In one embodiment, the channel layer overlaps with the conductive lines.

[0059] Another embodiment is a method including forming a conductive line in a substrate. The method further includes depositing an insulating layer on the substrate. The method further includes patterning a first opening in the insulating layer, the first opening extending perpendicular to the conductive line. The method further includes forming a conductive structure in the first opening. The method further includes patterning a second opening in the insulating layer, the second opening exposing the sidewalls of the conductive structure and the conductive line. The method further includes depositing a channel layer in the second opening. The method further includes depositing a gate dielectric layer on the channel layer. The method further includes depositing a gate electrode on the gate dielectric layer. The method further includes recessing the gate dielectric layer, the gate electrode, and the conductive structure, the channel layer extending above the gate electrode. The method further includes depositing an isolation structure around the channel layer, the isolation structure having an upper surface flush with the upper surface of the channel layer. In one embodiment, after forming the conductive structure, a portion of the insulating layer remains between the conductive structure and the substrate. In one embodiment, forming the conductive structure includes: depositing a resist layer in the first opening; and filling the first opening with a metal-containing filler material. In one embodiment, forming the conductive structure further includes: depositing a dielectric layer in the first opening before depositing the resist layer. In one embodiment, the method further includes: depositing an insulating structure on the isolation structure; and forming a unit capacitor in the insulating structure, the unit capacitor being coupled to a channel layer. In one embodiment, forming the unit capacitor includes: depositing a capacitor insulating material on a first upper portion of the channel layer, and depositing an upper electrode on the capacitor insulating material.

[0060] Another embodiment is a method comprising depositing a channel structure in a first opening disposed between two conductive structures, the channel structure lining the first opening, the bottom of the channel structure extending along a conductive element embedded in a substrate, wherein a first isolation structure is interposed between the two conductive structures and the substrate, and the first opening exposes a portion of the first isolation structure. The method further comprises depositing a gate dielectric layer in the first opening, the gate dielectric layer lining the first opening on the channel structure. The method further comprises depositing a gate electrode in the first opening, the gate electrode filling the first opening. The method further comprises recessing the upper surfaces of the two conductive structures and the upper surface of the gate electrode, exposing a first portion of the channel structure from the two conductive structures and the gate electrode. The method further comprises depositing a second isolation structure over the upper surfaces of the two conductive structures and the upper surface of the gate electrode, the second isolation structure laterally surrounding the first portion of the channel structure. In one embodiment, a third isolation structure surrounds each of the two conductive structures such that the third isolation structure is interposed between each of the two conductive structures and the channel structure. In one embodiment, the second isolation structure is recessed to expose a second portion of the channel structure; a capacitor insulating layer of a capacitor is deposited over the second portion of the channel structure; and an upper electrode of a capacitor is deposited over the capacitor insulating layer. In one embodiment, the method further includes depositing a bottom electrode of a capacitor on a second portion of the channel structure prior to depositing an insulating layer for the capacitor. In one embodiment, the method further includes forming a cell capacitor on the channel structure, the bottom electrode of the cell capacitor contacting each of the two upper surfaces of the channel structure. In one embodiment, the method further includes coupling a conductive element to a bit line of the memory device; coupling a gate electrode to a word line of the memory device; and coupling the two conductive structures to the same reference voltage of the memory device.

[0061] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0062] Example 1 is a semiconductor structure comprising: a dielectric layer disposed on a substrate; a gate electrode embedded in the dielectric layer; a channel layer surrounding the gate electrode; a conductive structure adjacent to the channel layer, the channel layer being disposed between the gate electrode and the conductive structure; and a dielectric structure disposed on the conductive structure and the gate electrode, the channel layer extending upward through the dielectric structure.

[0063] Example 2 is the semiconductor structure described in Example 1, further comprising: a unit capacitor disposed on the channel layer and coupled to the channel layer.

[0064] Example 3 is the semiconductor structure described in Example 2, further comprising: an insulating layer disposed on the dielectric structure, wherein the unit capacitor comprises: a bottom electrode; a capacitor dielectric layer disposed on the bottom electrode; and a top electrode disposed on the capacitor dielectric layer.

[0065] Example 4 is the semiconductor structure described in Example 3, wherein the upper part of the channel layer does not have the dielectric structure, wherein the bottom electrode of the unit capacitor includes the upper part of the channel layer, and the capacitor dielectric layer extends along the sidewalls and upper surface of the upper part of the channel layer.

[0066] Example 5 is the semiconductor structure described in Example 1, further comprising: a channel insulating layer, between the channel layer and the conductive structure.

[0067] Example 6 is the semiconductor structure described in Example 1, further comprising: a conductive line embedded in the substrate, wherein the channel layer is coupled to the conductive line.

[0068] Example 7 is the semiconductor structure described in Example 6, wherein the interface between the channel layer and the conductive line is laterally surrounded by the dielectric layer.

[0069] Example 8 is the semiconductor structure described in Example 6, wherein the channel layer overlaps with the conductive line.

[0070] Example 9 is a method of forming a semiconductor structure, comprising: forming a conductive line in a substrate; depositing an insulating layer on the substrate; patterning a first opening in the insulating layer, the first opening extending perpendicular to the conductive line; forming a conductive structure in the first opening; patterning a second opening in the insulating layer, the second opening exposing sidewalls of the conductive structure and the conductive line; depositing a channel layer in the second opening; depositing a gate dielectric layer on the channel layer; depositing a gate electrode on the gate dielectric layer; recessing the gate dielectric layer, the gate electrode, and the conductive structure, the channel layer extending above the gate electrode; and depositing an isolation structure around the channel layer, the isolation structure having an upper surface flush with the upper surface of the channel layer.

[0071] Example 10 is the method of Example 9, wherein, after the conductive structure is formed, a portion of the insulating layer remains between the conductive structure and the substrate.

[0072] Example 11 is the method of Example 9, wherein forming the conductive structure includes: depositing an adhesive layer in the first opening; and filling the first opening with a metal-containing filler material.

[0073] Example 12 is the method of Example 11, wherein forming the conductive structure further includes depositing a dielectric layer in the first opening prior to depositing the adhesive layer.

[0074] Example 13 is the method of Example 9, further comprising: depositing an insulating structure on the isolation structure; and forming a unit capacitor in the insulating structure, the unit capacitor being coupled to the channel layer.

[0075] Example 14 is the method of Example 13, further comprising: recessing the upper surface of the insulating structure to expose a first upper portion of the channel layer prior to forming the insulating structure, wherein forming the unit capacitor comprises: depositing a capacitor insulating material over the first upper portion of the channel layer, and depositing an upper electrode over the capacitor insulating material.

[0076] Example 15 is a method of forming a semiconductor structure, comprising: depositing a channel structure in a first opening disposed between two conductive structures, the channel structure being lined within the first opening, the bottom of the channel structure extending along a conductive element embedded in a substrate, wherein a first isolation structure is interposed between the two conductive structures and the substrate, the first opening exposing a portion of the first isolation structure; depositing a gate dielectric layer in the first opening, the gate dielectric layer being lined within the first opening on the channel structure; depositing a gate electrode in the first opening, the gate electrode filling the first opening; recessing the upper surfaces of the two conductive structures and the upper surface of the gate electrode, the first portion of the channel structure being exposed from the two conductive structures and the gate electrode; and depositing a second isolation structure over the upper surfaces of the two conductive structures and the upper surface of the gate electrode, the second isolation structure laterally surrounding the first portion of the channel structure.

[0077] Example 16 is the method described in Example 15, wherein a third isolation structure surrounds each of the two conductive structures such that the third isolation structure is located between each of the two conductive structures and the channel structure.

[0078] Example 17 is the method of Example 15, further comprising: recessing the second isolation structure, wherein recessing the second isolation structure exposes a second portion of the channel structure; depositing a capacitor insulating layer of a capacitor over the second portion of the channel structure; and depositing an upper electrode of the capacitor over the capacitor insulating layer.

[0079] Example 18 is the method of Example 17, further comprising: depositing the bottom electrode of the capacitor on a second portion of the channel structure prior to depositing the capacitor insulating layer.

[0080] Example 19 is the method of Example 15, further comprising: forming a unit capacitor on the channel structure, the bottom electrode of the unit capacitor contacting each of the two upper surfaces of the channel structure.

[0081] Example 20 is the method of Example 15, further comprising: coupling the conductive element to a bit line of the memory device; coupling the gate electrode to a word line of the memory device; and coupling the two conductive structures to the same reference voltage of the memory device.

Claims

1. A semiconductor structure, comprising: A dielectric layer is disposed on the substrate; The gate electrode is embedded in the dielectric layer; A channel layer surrounding the gate electrode, wherein the channel layer has a first portion adjacent to the sidewall of the gate electrode and a second portion located below the gate electrode; A conductive structure adjacent to the channel layer, the channel layer being situated between the gate electrode and the conductive structure; and A dielectric structure is disposed above the conductive structure and the gate electrode, and the channel layer extends upward through the dielectric structure.

2. The semiconductor structure according to claim 1, further comprising: A unit capacitor is disposed above the channel layer and coupled to the channel layer.

3. The semiconductor structure according to claim 2, further comprising: An insulating layer is disposed on the dielectric structure, wherein the unit capacitor includes: Bottom electrode; A capacitor dielectric layer is disposed above the bottom electrode; and The top electrode is disposed on the dielectric layer of the capacitor.

4. The semiconductor structure according to claim 3, wherein, The upper part of the channel layer does not have the dielectric structure, wherein the bottom electrode of the unit capacitor includes the upper part of the channel layer, and the capacitor dielectric layer extends along the sidewall and upper surface of the upper part of the channel layer.

5. The semiconductor structure according to claim 1, further comprising: A channel insulating layer is located between the channel layer and the conductive structure.

6. The semiconductor structure according to claim 1, further comprising: Conductive lines are embedded in the substrate, and the channel layer is coupled to the conductive lines.

7. The semiconductor structure according to claim 6, wherein, The interface between the channel layer and the conductive line is laterally surrounded by the dielectric layer.

8. The semiconductor structure according to claim 6, wherein, The channel layer overlaps with the conductive line.

9. A method for forming a semiconductor structure, comprising: Conductive lines are formed in the substrate; An insulating layer is deposited on the substrate; A first opening is patterned in the insulating layer, the first opening extending perpendicular to the conductive line; A conductive structure is formed in the first opening; A second opening is patterned in the insulating layer, the second opening exposing the sidewalls of the conductive structure and the conductive lines; Deposit a channel layer in the second opening; A gate dielectric layer is deposited on the channel layer; A gate electrode is deposited on the gate dielectric layer; The gate dielectric layer, the gate electrode, and the conductive structure are recessed, and the channel layer extends above the gate electrode. as well as An isolation structure is deposited around the channel layer, the isolation structure having an upper surface flush with the upper surface of the channel layer.

10. The method according to claim 9, wherein, After the conductive structure is formed, a portion of the insulating layer remains between the conductive structure and the substrate.

11. The method according to claim 9, wherein, Forming the conductive structure includes: Deposit an adhesive layer in the first opening; and The first opening is filled with a metal-containing filler material.

12. The method according to claim 11, wherein, The formation of the conductive structure further includes: Before depositing the adhesive layer, a dielectric layer is deposited in the first opening.

13. The method of claim 9, further comprising: An insulating structure is deposited on the isolation structure; as well as A unit capacitor is formed in the insulating structure, and the unit capacitor is coupled to the channel layer.

14. The method of claim 13, further comprising: Before forming the insulating structure, the upper surface of the insulating structure is recessed to expose a first upper portion of the channel layer, wherein forming the unit capacitor includes: A capacitor insulating material is deposited on the first upper portion of the channel layer, and An electrode is deposited on the capacitor insulating material.

15. A method for forming a semiconductor structure, comprising: A channel structure is deposited in a first opening, the first opening being disposed between two conductive structures, the channel structure being lined within the first opening, the bottom of the channel structure extending along a conductive element embedded in a substrate, wherein a first isolation structure is situated between the two conductive structures and the substrate, and a portion of the first isolation structure is exposed by the first opening. A gate dielectric layer is deposited in the first opening, the gate dielectric layer being lined within the first opening in the channel structure; A gate electrode is deposited in the first opening, and the gate electrode fills the first opening; The upper surfaces of the two conductive structures and the upper surface of the gate electrode are recessed, and a first portion of the channel structure is exposed from the two conductive structures and the gate electrode; and A second isolation structure is deposited on the upper surfaces of the two conductive structures and the upper surface of the gate electrode, the second isolation structure laterally surrounding the first portion of the channel structure.

16. The method according to claim 15, wherein, A third isolation structure surrounds each of the two conductive structures, such that the third isolation structure is located between each of the two conductive structures and the channel structure.

17. The method of claim 15, further comprising: The second isolation structure is recessed, wherein the second isolation structure is recessed to expose a second portion of the channel structure; A capacitor insulating layer for the capacitor is deposited on the second portion of the channel structure; and The upper electrode of the capacitor is deposited on top of the capacitor's insulating layer.

18. The method of claim 17, further comprising: Before depositing the capacitor insulating layer, the bottom electrode of the capacitor is deposited on the second portion of the channel structure.

19. The method of claim 15, further comprising: A unit capacitor is formed on the channel structure, and the bottom electrode of the unit capacitor is in contact with each of the two upper surfaces of the channel structure.

20. The method of claim 15, further comprising: Couple the conductive element to the bit line of the memory device; The gate electrode is coupled to the word line of the memory device; as well as The two conductive structures are coupled to the same reference voltage of the storage device.

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