A method for manufacturing a three-dimensional memory and a three-dimensional memory

Abstract

The embodiment of the application discloses a three-dimensional memory manufacturing method and a three-dimensional memory. The manufacturing method comprises the following steps: providing a substrate; forming a stack structure on the substrate; forming a first mask plate on the side of the stack structure away from the substrate; etching the stack structure by a first thickness with the first mask plate as a mask to form a first channel hole in the stack structure; etching the stack structure by a second thickness with the first mask plate as a mask to form a second channel hole in the stack structure, and the second channel hole is communicated with the first channel hole; wherein the channel hole of the stack structure comprises the first channel hole and the second channel hole, the first channel hole and the second channel hole are formed in different etching steps, and the channel hole in the stack structure is formed by etching the stack structure for multiple times, so that the high aspect ratio requirement of the channel hole is met without upgrading the etching machine.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a method for fabricating a three-dimensional memory and the three-dimensional memory itself. Background Technology

[0002] With the continuous development of semiconductor technology, memory devices have received widespread attention, especially 3D memory, which features high integration and larger storage capacity and has become a research focus in recent years. However, as 3D memory technology advances, the number of stacked layers gradually increases, leading to larger aspect ratios of the vias in 3D memory. This makes it difficult for conventional etching equipment to meet the etching requirements of these increasingly larger aspect ratios, affecting the formation quality of the vias. Upgrading the etching equipment to meet the etching requirements would increase manufacturing costs. Therefore, how to complete the etching of 3D memory vias without upgrading the etching equipment has become a key research focus for those skilled in the art. Summary of the Invention

[0003] To address the aforementioned technical problems, this application provides a method for fabricating a three-dimensional memory and a three-dimensional memory itself. This method solves the problem of needing to upgrade the etching equipment to meet the etching requirements of the channel holes.

[0004] To address the above problems, the embodiments of this application provide the following technical solutions:

[0005] A method for fabricating a three-dimensional memory, the method comprising:

[0006] Provide a substrate;

[0007] A stacked structure is formed on the substrate;

[0008] A first mask is formed on the side of the stacked structure opposite to the substrate;

[0009] Using the first mask as a mask, the first thickness of the stacked structure is etched to form a first channel hole in the stacked structure;

[0010] Using the first mask as a mask, the second thickness of the stacked structure is etched to form a second channel hole in the stacked structure, and the second channel hole is connected to the first channel hole.

[0011] The channel holes in the stacked structure include the first channel hole and the second channel hole.

[0012] Optionally, the method further includes:

[0013] After the first channel hole is formed and before the second channel hole is formed, a first polysilicon layer is formed, which covers the sidewall of the first channel hole.

[0014] Optionally, forming a first polysilicon layer on the sidewall of the first channel hole after the first channel hole is formed and before the second channel hole is formed includes:

[0015] After the first channel hole is formed, a first polysilicon layer is formed, which covers the first mask, the sidewall of the first channel hole, and the bottom of the first channel hole.

[0016] Remove the portion of the first polysilicon layer located on the surface of the first mask and the portion of the first polysilicon layer located at the bottom of the first channel hole, and retain the portion of the first polysilicon layer located on the sidewall of the first channel hole.

[0017] Optionally, the method further includes:

[0018] After forming the second channel hole, the portion of the first polysilicon layer located on the sidewall of the first channel hole is removed.

[0019] Optionally, the method further includes:

[0020] After the first channel hole is formed and before the second through hole is formed, a second mask is formed on the surface of the first mask.

[0021] Using the first mask as a mask, etching the second thickness of the stacked structure to form a second channel hole in the stacked structure includes:

[0022] Using the mask structure composed of the first mask and the second mask as a mask, the second thickness of the stacked structure is etched to form a second channel hole in the stacked structure.

[0023] Optionally, the method further includes:

[0024] After forming the first polysilicon layer covering the first mask, the sidewall of the first channel hole, and the bottom of the first channel hole, before forming the second mask on the surface of the first mask, a first filler layer covering the surface of the first mask and filling the first channel hole is formed. The portion of the first filler layer located on the surface of the first mask is removed to form a first filler layer that only fills the first channel hole.

[0025] Optionally, if the first channel hole is filled with a first filling layer, the method further includes:

[0026] After forming the second mask and before forming the second channel hole, the first filler layer filling the first channel hole is removed.

[0027] Optionally, the method further includes:

[0028] After the channel hole is formed in the stacked structure, the channel hole structure is formed on the sidewall of the channel hole and on the portion of the substrate exposed in the channel hole.

[0029] This application also provides a three-dimensional memory, which includes:

[0030] Substrate;

[0031] A stacked structure located on the substrate, the stacked structure having channel holes, the channel holes including a first channel hole and a second channel hole, the first channel hole and the second channel hole being connected.

[0032] Optionally, the three-dimensional memory further includes a channel hole structure located on the sidewall of the channel hole and on the surface of the substrate exposed in the channel hole.

[0033] Compared with existing technologies, the above technical solution has the following advantages:

[0034] The technical solution provided in this application includes: providing a substrate; forming a stacked structure on the substrate; forming a first mask on the side of the stacked structure opposite to the substrate; using the first mask as a mask, etching a first thickness of the stacked structure to form a first channel hole in the stacked structure; using the first mask as a mask, etching a second thickness of the stacked structure to form a second channel hole in the stacked structure, the second channel hole communicating with the first channel hole; wherein the channel hole of the stacked structure includes the first channel hole and the second channel hole, and the first channel hole and the second channel hole are formed in different etching steps. Therefore, the fabrication method provided in this application, by repeatedly etching the stacked structure to form channel holes in the stacked structure, can meet the high aspect ratio requirements of the channel holes without upgrading the etching equipment. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figures 1-6This is a cross-sectional view of the structure formed after different technological steps in an existing method for manufacturing a three-dimensional memory.

[0037] Figure 7 A cross-sectional view of a channel hole satisfying the aspect ratio in a three-dimensional memory stack structure;

[0038] Figure 8 A cross-sectional view of a channel hole with uneven depth in a three-dimensional memory stack structure;

[0039] Figure 9 A flowchart illustrating a method for fabricating a three-dimensional memory according to an embodiment of this application;

[0040] Figures 10-27 This is a cross-sectional view of the structure formed after different process steps in a three-dimensional memory fabrication method provided in an embodiment of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0043] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0044] As described in the background section, with the increase in the number of stacked layers of 3D memory, conventional etching equipment is no longer able to meet the etching requirements of channel holes with gradually increasing aspect ratios. Therefore, how to complete the etching of 3D memory channel holes without upgrading the etching equipment has become a research focus for those skilled in the art.

[0045] Existing methods for fabricating three-dimensional memory include: such as Figure 1As shown, a substrate 11 is provided; a stacked structure 12 is formed on the substrate 11, and a photomask 13 is formed on the side of the stacked structure 12 opposite to the substrate 11; a photoresist layer 14 is formed on the photoresist layer 14, the photoresist layer 14 having a channel hole pattern; as shown Figure 2 As shown, the photoresist layer 14 with the channel hole pattern is used as a mask to etch the mask 13, transferring the channel hole pattern onto the mask 13; as Figure 3 As shown, using the mask 13 as a mask, the stacked structure 12 is dry etched to form a channel hole 15. The channel hole 15 is perpendicular to the substrate 11 and extends through the stacked structure 12 to the surface of the substrate 11; Figure 4 As shown, after forming the channel hole 15, a single-crystal silicon layer 16 is formed on the portion of the substrate 11 exposed in the channel hole 15 using epitaxial growth. Next, a gate dielectric layer 17 is formed covering the single-crystal silicon layer 16, the sidewalls of the channel hole 15, and the surface of the mask 13; as shown... Figure 5 As shown, a portion of the gate dielectric layer 17 located at the bottom of the channel hole 15 is removed using dry etching to expose a portion of the single-crystal silicon layer 16 and the portion of the gate dielectric layer located on the surface of the mask 13; as Figure 6 As shown, a polysilicon layer 18 is formed on the side of the gate dielectric layer 17 away from the sidewall of the channel hole 15, and a silicon oxide layer 19 is filled in the channel hole 15. The upper surface of the silicon oxide layer 19 is lower than the upper surface of the mask 13. A polysilicon plunger 191 is formed on the upper surface of the silicon oxide layer 19, and the upper surface of the polysilicon plunger 191 is flush with the upper surface of the mask 13.

[0046] As mentioned above, in existing 3D memory fabrication methods, the channel holes in the stacked structure are formed through a single-step etching process. However, with the development of 3D memory, the number of stacked layers in its stacked structure is gradually increasing, resulting in a gradually larger thickness of the stacked structure. This places increasingly higher demands on dry etching equipment, requiring sufficiently high power and well-configured equipment to form the desired channel holes in the stacked structure. Figure 7 The channel holes shown in the diagram penetrate the stacked structure and meet the aspect ratio requirements. However, during the formation of channel holes with high density and large aspect ratio, the channel hole depth, wall morphology, diameter, and overall depth cannot be controlled, easily leading to uneven depth in the formed channel holes. Figure 8 As shown, some channel holes are too deep or too shallow, and the quality of channel hole formation is poor.

[0047] In view of this, embodiments of this application provide a method for fabricating a three-dimensional memory, such as... Figure 9 As shown, the manufacturing method includes:

[0048] S1: Provide a substrate 10, such as Figure 10 As shown;

[0049] S2: A stacked structure 20 is formed on the substrate, such as Figure 11 As shown;

[0050] S3: A first mask is formed on the side of the stacked structure opposite to the substrate;

[0051] Specifically, in one embodiment of this application, forming a first mask on the side of the stacked structure opposite to the substrate includes: as follows Figure 12 As shown, a first mask layer 311 is formed on the side of the stacked structure 20 opposite to the substrate 10, and a photoresist layer 312 is formed on the first mask layer 311. The photoresist layer 312 has a channel hole pattern, such as... Figure 13 As shown, the first mask layer 311 is etched using a photoresist layer 312 with a channel hole pattern as a mask, transferring the channel hole pattern onto the first mask layer 311 to form a first mask 31, and then the photoresist layer 312 is removed. It should be noted that in this embodiment, forming the first mask on the side of the stacked structure away from the substrate can protect the non-channel hole portions of the stacked structure, preventing damage to these portions during subsequent channel hole formation and ensuring the integrity of the three-dimensional memory.

[0052] S4: Using the first mask as a mask, etch the first thickness of the stacked structure to form a first channel hole in the stacked structure.

[0053] Specifically, based on the above embodiments, in one embodiment of this application, such as Figure 14 As shown, forming the first channel hole 40 in the stacked structure 20 includes: etching the stacked structure 20 to a first thickness using the first mask 31 as a mask, thereby forming the first channel hole 40 in the stacked structure 20. The extension direction of the first channel hole 40 is perpendicular to the substrate 10. The first thickness is less than the thickness of the stacked structure, thereby reducing the number of stacked layers etched by the etching equipment in a single operation, i.e., reducing the thickness of the stacked structure etched in a single operation. This allows a general etching equipment to complete the etching of the first thickness of the stacked structure and form the first channel hole in the stacked structure without upgrading the etching equipment, thus saving costs. The number of stacked layers etched to the first thickness of the stacked structure in a single operation can be selected according to the etching capability of the etching equipment used.

[0054] Optionally, in this embodiment, the process of etching the first thickness of the stacked structure to form the first channel hole is dry etching, but this application does not limit it and it depends on the specific situation.

[0055] S5: Using the first mask as a mask, etch the second thickness of the stacked structure to form a second channel hole in the stacked structure. The second channel hole is connected to the first channel hole, wherein the channel hole of the stacked structure includes the first channel hole and the second channel hole.

[0056] It should be noted that with the development of 3D memory, the number of stacked layers in the 3D memory stacked structure is also gradually increasing. When the number of stacked layers increases, the thickness of the stacked structure will also increase accordingly, which in turn leads to an increase in the aspect ratio of the channel holes in the stacked structure. This makes it impossible for general etching equipment to form channel holes that meet the aspect ratio requirements in one etching, thus increasing the difficulty of etching the stacked structure to form channel holes.

[0057] The manufacturing method provided in this application embodiment first forms a first channel hole in the stacked structure, and then forms a second channel hole in the stacked structure. The second channel hole is connected to the first channel hole. By etching the stacked structure multiple times, the channel hole is formed in the stacked structure, thereby meeting the high aspect ratio requirement of the channel hole without upgrading the etching equipment.

[0058] Based on any of the above embodiments, in one embodiment of this application, the channel hole includes only a first channel hole and a second channel hole, that is, the channel hole is composed of the first channel hole and the second channel hole. However, this application does not limit this. In other embodiments of this application, the channel hole may also include at least three interconnected sub-channel holes, that is, the channel hole is composed of at least three interconnected sub-channel holes, depending on the specific situation.

[0059] Specifically, in one embodiment of this application, the channel holes in the stacked structure include a first channel hole, a second channel hole, ..., an nth channel hole. These first channel holes, second channel holes, ..., nth channel holes are formed in different etching steps. This reduces the number of layers etched in a single etching operation, thus reducing the thickness of the stacked structure in a single etching operation. The channel holes can be formed in the stacked structure through multiple etching operations. This allows for etching of the stacked structure without upgrading the etching equipment when the number of stacked layers is large, preventing conventional etching equipment from forming the channel holes in a single operation, and thus satisfying the aspect ratio requirements of the channel holes. Here, n can be any positive integer not less than 2.

[0060] It should be noted that, in the embodiments of this application, during the process of forming a channel hole by repeatedly etching the stacked structure, the number of times the stacked structure is etched can be adjusted according to the number of stacked layers of the stacked structure, that is, the number of stacked layers of the stacked structure is adjusted in a single etching, which is also the thickness of the stacked structure in a single etching, so as to form a channel hole that meets the high aspect ratio requirement in the stacked structure by repeatedly etching. It should also be noted that when selecting the number of etching cycles for the stacked structure based on the number of stacked layers, the etching capability of the etching equipment itself needs to be considered. Generally, an integer multiple of the number of stacked layers that the etching equipment can etch can be selected. For example, if the number of stacked layers that the etching equipment can normally etch in one cycle is 32, then a stacked structure with 64 stacked layers will require two etching cycles, a stacked structure with 128 stacked layers will require four etching cycles, and so on. This application does not limit the number of etching cycles for the stacked structure; it depends on the specific circumstances. Furthermore, the specific number of layers etched in a single cycle depends on the etching capability of the etching equipment used, which this application does not limit; it depends on the specific circumstances.

[0061] The following describes the fabrication method of the three-dimensional memory provided in the embodiments of this application, taking the stacked structure as an example where the channel holes only include the first channel hole and the second channel hole.

[0062] Based on any of the above embodiments, in one embodiment of this application, the fabrication method further includes: forming a first polysilicon layer after the first channel hole is formed and before the second channel hole is formed, the first polysilicon layer covering the sidewall of the first channel hole, so that the first polysilicon layer can protect the sidewall of the first channel hole in the subsequent process of forming the second channel hole, preventing the sidewall of the first channel hole from being damaged in the subsequent process of forming the second channel hole, thus affecting the goodness of the three-dimensional memory.

[0063] Specifically, based on the above embodiments, in one embodiment of this application, forming a first polysilicon layer on the sidewall of the first channel hole after the first channel hole is formed and before the second channel hole is formed includes: Figure 15As shown, after the first channel hole 40 is formed, a first polysilicon layer 41 is formed, covering the first mask 31, the sidewall of the first channel hole 40, and the bottom of the first channel hole 40. Then, the portion of the first polysilicon layer located on the surface of the first mask and the portion of the first polysilicon layer located at the bottom of the first channel hole are removed, leaving the portion of the first polysilicon layer located on the sidewall of the first channel hole, thus forming the first polysilicon layer on the sidewall of the first channel hole. It should be noted that, in this embodiment, the first polysilicon layer located on the sidewall of the channel hole can protect the sidewall of the first channel hole during the subsequent process of forming the second channel hole, preventing damage to the sidewall of the first channel hole during the formation of the second channel hole and affecting the quality of the three-dimensional storage.

[0064] It should be noted that, in this embodiment of the application, during the process of forming the channel hole in the stacked structure, the etching process gradually consumes the first mask located on the surface of the stacked structure. When the first mask is completely consumed, the stacked structure will be damaged, affecting the performance of the memory. If a thicker first mask is formed on the surface of the stacked structure to prevent the first mask from being consumed and causing damage to the stacked structure, the first mask has high hardness. When the thickness of the first mask is too large, it will increase the difficulty of etching the first mask, affecting the etching of the first mask.

[0065] Therefore, in one embodiment of this application, the method further includes: forming a second mask on the surface of the first mask after forming the first channel hole and before forming the second channel hole, which can prevent damage to the non-channel hole portion of the stacked structure in subsequent etching processes due to the exhaustion of the first mask, thus affecting the goodness of the 3D memory. In this embodiment of the application, etching the second thickness of the stacked structure using the first mask as a mask to form the second channel hole in the stacked structure includes: using a mask structure composed of the first mask and the second mask as a mask to etch the second thickness of the stacked structure to form the second channel hole in the stacked structure.

[0066] It should be noted that, since the first mask exposes the first channel hole, when the method includes forming a second mask on the surface of the first mask, in order to facilitate the formation of the second mask, the method further includes: after forming a first polysilicon layer covering the first mask, the sidewall of the first channel hole, and the bottom of the first channel hole, before forming the second mask on the surface of the first mask, forming a first filler layer covering the surface of the first mask and filling the first channel hole, removing the portion of the first filler layer located on the surface of the first mask, forming a first filler layer that only fills the first channel hole, so that after the first filler layer fills the first channel hole, a second mask layer is formed on the first filler layer and the surface of the first mask, and then the second mask layer is etched to form the second mask.

[0067] Specifically, based on the above embodiments, in one embodiment of this application, if a first polysilicon layer is formed on the sidewall of the first channel hole, forming a first filling layer that only fills the first channel hole includes: after forming the first polysilicon layer covering the first mask, the sidewall of the first channel hole, and the bottom of the first channel hole, before forming the second mask on the surface of the first mask, such as... Figure 16 As shown, a first filling layer 42 is formed covering the surface of the first mask 31 and the first channel hole 40; as Figure 17 As shown, the portion of the first filling layer 42 located on the surface of the first mask 31 and the portion of the first polysilicon layer 41 located on the surface of the first mask 31 are removed using a chemical mechanical polishing (CMP) process, forming the first filling layer 42 that only fills the first channel hole 40.

[0068] It should be noted that, in this embodiment of the application, since the stacked structure in the three-dimensional memory has a large number of stacked layers, when the first channel hole is formed in the stacked structure, the stacked structure will generate pressure around the first channel hole. In this embodiment of the application, the first filling layer in the first channel hole can play a role in supporting the first channel hole and preventing the first channel hole from deforming and affecting the performance of the three-dimensional memory.

[0069] Optionally, in this embodiment, the first filling layer is a silicon oxide layer, but this application does not limit this and it depends on the specific circumstances.

[0070] Specifically, based on the above embodiments, in one embodiment of this application, forming the second mask on the surface of the first mask includes: as follows Figure 18As shown, after forming the first filling layer 42 that only fills the first channel hole 40, the second mask layer 321 is formed on the surface of the first mask 31; as Figure 19 As shown, the second mask layer 321 is etched to form the second mask 32, wherein the projections of the first mask 31 and the second mask 32 on the plane of the substrate 10 coincide, which can prevent the non-channel hole portion in the stacked structure from being damaged in subsequent etching processes due to the exhaustion of the first mask.

[0071] In another embodiment of this application, after forming the first channel hole and before forming the second channel hole, if it can be ensured that the first mask will not be completely consumed by the etching process in the subsequent process of forming the second channel hole, the first mask can be directly used as a mask to etch the second thickness of the stacked structure and form the second channel hole in the stacked structure. It is not necessary to form the first filling layer that only fills the first channel hole, nor is it necessary to form the second mask on the surface of the first mask. Using the mask structure composed of the first mask and the second mask as a mask to etch the second thickness of the stacked structure and form the second channel hole in the stacked structure can reduce the manufacturing cost of the three-dimensional memory. However, this application does not limit this and it depends on the specific circumstances.

[0072] Based on the above embodiments, in one embodiment of this application, if the first channel hole is filled with a first filling layer, the method further includes: Figure 20 As shown, after the second mask 32 is formed on the surface of the first mask 31, the first filler layer 42 that fills the first channel hole 40 is removed so that the second channel hole 50 can be formed in the stacked structure 20 subsequently.

[0073] Optionally, in one embodiment of this application, the process for removing the first filling layer in the first channel hole is a wet etching process, and the etching solution can be a dilute HF solution. However, this application does not limit this process and it depends on the specific circumstances.

[0074] It should be noted that, in the embodiments of this application, if a first polysilicon layer is formed on the sidewall of the first channel hole and a first filling layer is also filled inside the first channel hole, such as Figure 21As shown, the method further includes: forming a second mask on the surface of the first mask, and after removing the first filling layer 42 filling the first channel hole 40, removing the portion of the first polysilicon layer 41 located at the bottom of the channel hole 40, leaving only the portion of the first polysilicon layer located on the sidewall of the first channel hole. In other embodiments of this application, if a second mask is not formed on the surface of the first mask, and a first filling layer filling the first channel hole is not formed, then after forming the first polysilicon layer covering the first mask, the sidewall of the first channel hole, and the bottom of the first channel hole, the portion of the first polysilicon layer located on the surface of the first mask and the portion of the first polysilicon layer located at the bottom of the first channel hole are directly removed, leaving the portion of the first polysilicon layer located on the sidewall of the first channel hole. However, this application does not limit this, and it depends on the specific circumstances.

[0075] Optionally, in one embodiment of this application, the process for removing the portion of the first polysilicon layer located at the bottom of the first channel hole is a dry etching process, but this application does not limit this process and it depends on the specific circumstances.

[0076] Based on any of the above embodiments, in one embodiment of this application, if a second mask is formed on the surface of the first mask after the first channel hole is formed and before the second through hole is formed, then in this embodiment of the application, using the first mask as a mask to etch the second thickness of the stacked structure to form the second channel hole in the stacked structure includes: Figure 22 As shown, using the mask structure 30 composed of the first mask 31 and the second mask 32 as a mask, the second thickness of the stacked structure 20 is etched to form the second channel hole 50 in the stacked structure 20, thereby forming the channel hole 60 in the stacked structure 20. The channel hole 60 extends perpendicularly to the substrate 10 and extends to the surface of the substrate 10. In another embodiment of this application, if it can be determined that the first mask will not be completely consumed after the first channel hole is formed and before the second through hole is formed, such as... Figure 23 As shown, the first mask 31 is used directly as a mask to etch the second thickness of the stacked structure 20, forming the second channel 50 in the stacked structure 20. However, this application does not limit this, and it depends on the specific circumstances.

[0077] Optionally, in this embodiment, the process of etching the second thickness of the stacked structure to form the second channel hole in the stacked structure is a dry etching process, but this application does not limit it and it depends on the specific situation.

[0078] It should be noted that, in the embodiments of this application, the second channel hole is connected to the first channel hole. The channel hole in the stacked structure includes the first channel hole and the second channel hole, and the first channel hole and the second channel hole are formed in different etching steps. That is, the stacked structure can be etched in multiple steps to form the channel hole that penetrates the stacked structure, is perpendicular to the substrate, and extends to the surface of the substrate. Compared with single-step etching of the stacked structure, forming the channel hole in the stacked structure reduces the number of stacked layers in a single etching of the stacked structure, that is, reduces the thickness of the stacked structure in a single etching. It is possible to etch the stacked structure without upgrading the etching equipment and form a channel hole in the stacked structure that meets the requirements of high aspect ratio.

[0079] Based on the above embodiments, in one embodiment of this application, if a first polysilicon layer is formed on the sidewall of the first channel hole, such as Figure 24 As shown, the method further includes: after the second channel hole 50 is formed, removing the portion of the first polysilicon layer 31 located on the sidewall of the first channel hole 40 to complete the formation of the channel hole 60 in the stacked structure 20.

[0080] Optionally, in this embodiment, the process for removing the first polysilicon layer is a wet etching process, but this application does not limit this to a specific method, and it depends on the circumstances.

[0081] Based on any of the above embodiments, in one embodiment of this application, the method further includes:

[0082] S6: After the channel hole is formed in the stacked structure, a channel hole structure is formed on the sidewall of the channel hole and on the surface of the substrate exposed in the channel hole.

[0083] Specifically, based on any of the above embodiments, in one embodiment of this application, such as Figure 25 As shown, after forming the channel hole 60 in the stacked structure 20, forming a channel hole structure 70 on the sidewall of the channel hole 60 and the portion of the substrate 10 exposed in the channel hole 60 includes: forming a single-crystal silicon layer 71 on the portion of the substrate 10 exposed in the channel hole 60; forming a gate dielectric layer 72, the gate dielectric layer 72 covering the surface of the second mask 32, the sidewall of the channel hole 60, and the surface of the single-crystal silicon layer 71; as shown. Figure 26As shown, a portion of the gate dielectric layer 72 located at the bottom of the channel hole 60 is removed to expose part of the single-crystal silicon layer 71, and a portion of the gate dielectric layer 72 located on the surface of the second mask 32 is also removed. It should be noted that the method for forming the single-crystal silicon layer on the surface of the substrate exposed in the channel hole is epitaxial growth, but this application does not limit this method; it depends on the specific circumstances. It should also be noted that the method for removing the gate dielectric layer is dry etching, but this application does not limit this method; it depends on the specific circumstances.

[0084] In another embodiment of this application, if the second mask is not formed on the surface of the first mask, then when the gate dielectric layer is formed, the gate dielectric layer covers the surface of the first mask, the sidewall of the channel hole, and the surface of the single crystal silicon layer. This application does not limit this, and it depends on the specific situation.

[0085] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 25 As shown, forming the gate dielectric layer 72 covering the surface of the second mask 32, the sidewall of the channel hole 60, and the surface of the single crystal silicon layer 71 includes: forming a tunneling layer 721 on the surface of the second mask 32, the sidewall of the channel hole 60, and the surface of the single crystal silicon layer 70, the tunneling layer 721 being used to generate charge; forming a storage layer 722 on the surface of the tunneling layer 721, the storage layer 722 being used to store charge; forming a barrier layer 723 on the surface of the storage layer 722, the barrier layer 723 being used to block charge outflow; and forming a protective layer 724 on the surface of the barrier layer 723, the protective layer 724 being used to protect the barrier layer 723 from damage in subsequent processes. However, this application does not limit this, and it depends on the specific circumstances.

[0086] Based on the above embodiments, in one embodiment of this application, such as Figure 27 As shown, forming a channel hole structure 70 on the surface of the substrate 10 exposed in the first channel hole 60 further includes: removing the portion of the gate dielectric layer 72 located on the surface of the second mask 32 and the portion of the gate dielectric layer located at the bottom of the channel hole; forming a second polysilicon layer 73 on the sidewall of the gate dielectric layer 72 away from the channel hole 60; filling the channel hole 60 with a second filler layer 74, the upper surface of the second filler layer 74 being flush with the lower surface of the first mask 31; and forming a first polysilicon plug 75 on the upper surface of the second filler layer 74, the upper surface of the polysilicon plug 75 being flush with the upper surface of the second mask 32.

[0087] Furthermore, this application also provides a three-dimensional memory, which is fabricated using the fabrication method provided in any of the above embodiments. For example... Figure 24As shown in this embodiment, the three-dimensional memory includes:

[0088] Substrate 10;

[0089] A stacked structure 20 is located on the substrate 10, the stacked structure 20 having a channel hole 60, the channel hole 60 including a first channel hole 40 and a second channel hole 50, the first channel hole 40 and the second channel hole 50 being connected.

[0090] It should be noted that when the number of stacked layers in the stacked structure of the three-dimensional memory increases, the thickness of the stacked structure will also increase accordingly, which in turn leads to an increase in the aspect ratio of the channel holes in the stacked structure. This makes it impossible for a general etching machine to form channel holes that meet the aspect ratio requirements in a single etching process, thus increasing the difficulty of etching the stacked structure to form channel holes that meet the aspect ratio requirements.

[0091] Based on this, in the three-dimensional memory provided in the embodiments of this application, the channel holes in the stacked structure include a first channel hole and a second channel hole, and the first channel hole and the second channel hole are formed in different etching steps. By etching the stacked structure multiple times, channel holes are formed in the stacked structure. Compared with etching the stacked structure in a single step, forming channel holes in the stacked structure can reduce the number of layers etched in a single step, that is, reduce the thickness of the stacked structure etched in a single step. As a result, a general etching machine can form channel holes by etching the stacked structure multiple times. Channel holes can be formed in the stacked structure without upgrading the etching machine, and the aspect ratio requirements of the channel holes can be met.

[0092] It should be noted that, based on any of the above embodiments, in one embodiment of this application, the channel hole only includes a first channel hole and a second channel hole, that is, the channel hole is composed of the first channel hole and the second channel hole. However, this application does not limit this. In other embodiments of this application, the channel hole may also include at least three interconnected sub-channel holes, that is, the channel hole is composed of at least three interconnected sub-channel holes, depending on the specific situation.

[0093] Specifically, in one embodiment of this application, the channel holes in the stacked structure include a first channel hole, a second channel hole, ..., an nth channel hole. These first channel holes, second channel holes, ..., nth channel holes are formed in different etching steps. This reduces the number of layers etched in a single etching operation, thus reducing the thickness of the stacked structure in a single etching operation. In other words, the channel holes can be formed in the stacked structure through multiple etching operations. This allows for etching of the stacked structure without upgrading the etching equipment when the number of stacked layers is large, preventing conventional etching equipment from forming the channel holes in a single operation, and thus meeting the aspect ratio requirements of the channel holes. Here, n can be any positive integer not less than 2.

[0094] It should be noted that, in the embodiments of this application, the number of stacked layers of the first channel hole and the second channel hole in the stacked structure can be selected according to the capability of the currently used etching equipment. That is, the thickness of the first channel hole and the second channel hole can be selected according to the capability of the currently used etching equipment. Generally, it is selected as an integer multiple of the number of stacked layers that the etching equipment can etch. For example, if the number of stacked structure layers that the etching equipment can normally etch at one time is 32, then a stacked structure with 64 stacked layers will need to be etched twice, a stacked structure with 128 stacked layers will need to be etched four times, and so on. This application does not limit the number of times the stacked structure can be etched, but it depends on the specific situation. Furthermore, the specific number of layers of the stacked structure etched at one time depends on the etching capability of the etching equipment used, which this application does not limit, but depends on the specific situation.

[0095] Based on the above embodiments, in one embodiment of this application, such as Figure 27 As shown, the three-dimensional memory further includes: a channel hole structure 70 located on the sidewall of the channel hole 60 and on the surface of the substrate 10 exposed in the channel hole 60. The channel hole structure 70 includes: a single-crystal silicon layer 71 located on the surface of the substrate 10 exposed in the channel hole 60, and a gate dielectric layer 72 and a second polysilicon layer 73 sequentially covering the sidewall of the channel hole 60. The second polysilicon layer 73 is located on the side of the gate dielectric layer 72 away from the sidewall of the channel hole 60. A second filling layer 74 fills the channel hole 60. The upper surface of the second filling layer 74 is flush with the lower surface of the first mask 31. A polysilicon plug 75 is located on the surface of the second filling layer 74 and is flush with the upper surface of the second mask 32. However, this application does not limit this and the specific details depend on the situation.

[0096] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 27As shown, the first gate dielectric layer 72 includes: a tunneling layer 721, a storage layer 722, a barrier layer 723, and a protective layer 724 that sequentially cover the sidewall of the channel hole 60. The tunneling layer 721 is used to generate charge, the storage layer 722 is used to store charge, the barrier layer 723 is used to block charge outflow, and the protective layer 724 is used to protect the barrier layer 723 from damage. However, this application does not limit this, and it depends on the specific situation.

[0097] It should be noted that the three-dimensional memory provided in this application embodiment is a three-dimensional memory manufactured using the manufacturing method described in any of the above embodiments. The manufacturing method of the three-dimensional memory has been described in detail in the above embodiments and will not be repeated here.

[0098] Therefore, in the method for fabricating a three-dimensional memory and the three-dimensional memory using the method provided in this application, the channel holes of the stacked structure include the first channel hole and the second channel hole, and the first channel hole and the second channel hole are formed in different etching steps, so that the channel holes are formed in the stacked structure by etching the stacked structure multiple times, thereby meeting the high aspect ratio requirements of the channel holes without upgrading the etching equipment.

[0099] The various parts of this manual are described in a combination of parallel and progressive methods. Each part focuses on the differences between the other parts, and the same or similar parts can be referred to each other.

[0100] The features described above regarding the disclosed embodiments can be substituted or combined with each other to enable those skilled in the art to implement or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: Provide a substrate; A stacked structure is formed on the substrate; A first mask is formed on the side of the stacked structure opposite to the substrate; Using the first mask as a mask, the first thickness of the stacked structure is etched to form a first channel hole in the stacked structure; A first filler layer is formed that covers the surface of the first mask and fills the first channel hole; the portion of the first filler layer located on the surface of the first mask is removed to form a first filler layer that only fills the first channel hole. A second mask layer is formed on the surface of the first filler layer and the first mask, and then the second mask layer is etched to form a second mask on the surface of the first mask. Remove the first filler layer that fills the first channel hole; Using the mask structure composed of the first mask and the second mask as a mask, the second thickness of the stacked structure is etched to form a second channel hole in the stacked structure, and the second channel hole is connected to the first channel hole; The channel holes in the stacked structure include the first channel hole and the second channel hole.

2. The manufacturing method according to claim 1, characterized in that, The method also includes: After the first channel hole is formed and before the second channel hole is formed, a first polysilicon layer is formed, which covers the sidewall of the first channel hole.

3. The manufacturing method according to claim 2, characterized in that, Forming a first polysilicon layer on the sidewall of the first channel hole after the first channel hole is formed and before the second channel hole is formed includes: After the first channel hole is formed, a first polysilicon layer is formed, which covers the first mask, the sidewall of the first channel hole, and the bottom of the first channel hole. Remove the portion of the first polysilicon layer located on the surface of the first mask and the portion of the first polysilicon layer located at the bottom of the first channel hole, and retain the portion of the first polysilicon layer located on the sidewall of the first channel hole.

4. The manufacturing method according to claim 3, further comprising: After forming the second channel hole, the portion of the first polysilicon layer located on the sidewall of the first channel hole is removed.

5. The manufacturing method according to claim 4, further comprising: After forming the first polysilicon layer covering the first mask, the sidewall of the first channel hole, and the bottom of the first channel hole, before forming the second mask on the surface of the first mask, a first filler layer covering the surface of the first mask and filling the first channel hole is formed. The portion of the first filler layer located on the surface of the first mask is removed to form a first filler layer that only fills the first channel hole.

6. The manufacturing method according to claim 1, characterized in that, The method also includes: After the channel hole is formed in the stacked structure, the channel hole structure is formed on the sidewall of the channel hole and on the portion of the substrate exposed in the channel hole.

7. A three-dimensional memory, characterized in that, include: Substrate; A stacked structure located on the substrate, the stacked structure having channel holes, the channel holes including a first channel hole and a second channel hole, the first channel hole and the second channel hole being connected; The method for fabricating this three-dimensional memory includes: Provide a substrate; A stacked structure is formed on the substrate; A first mask is formed on the side of the stacked structure opposite to the substrate; Using the first mask as a mask, the first thickness of the stacked structure is etched to form a first channel hole in the stacked structure; A first filler layer is formed that covers the surface of the first mask and fills the first channel hole; the portion of the first filler layer located on the surface of the first mask is removed to form a first filler layer that only fills the first channel hole. A second mask layer is formed on the surface of the first filler layer and the first mask, and then the second mask layer is etched to form a second mask on the surface of the first mask. Remove the first filler layer that fills the first channel hole; Using the mask structure composed of the first mask and the second mask as a mask, the second thickness of the stacked structure is etched to form a second channel hole in the stacked structure, and the second channel hole is connected to the first channel hole; The channel holes in the stacked structure include the first channel hole and the second channel hole.

8. The three-dimensional memory according to claim 7, characterized in that, Also includes: The channel hole structure is located on the sidewall of the channel hole and on the surface of the substrate exposed in the channel hole.

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